
D:/Project/MCU/APT32F172/LIB/APT32F172_Release_V1_13/Source//Obj/apt32f172a.elf:     file format elf32-csky-little


Disassembly of section .text:

00000000 <vector_table>:
       0:	00000104 	.long	0x00000104
       4:	00005230 	.long	0x00005230
       8:	00005208 	.long	0x00005208
       c:	0000017c 	.long	0x0000017c
      10:	0000521c 	.long	0x0000521c
      14:	0000516e 	.long	0x0000516e
      18:	0000017c 	.long	0x0000017c
      1c:	000051f4 	.long	0x000051f4
      20:	000051e0 	.long	0x000051e0
      24:	0000017c 	.long	0x0000017c
      28:	0000017c 	.long	0x0000017c
      2c:	0000017c 	.long	0x0000017c
      30:	0000017c 	.long	0x0000017c
      34:	0000017c 	.long	0x0000017c
      38:	0000017c 	.long	0x0000017c
      3c:	0000017c 	.long	0x0000017c
      40:	000051cc 	.long	0x000051cc
      44:	000051b8 	.long	0x000051b8
      48:	000051a4 	.long	0x000051a4
      4c:	00005190 	.long	0x00005190
      50:	0000017c 	.long	0x0000017c
      54:	0000017c 	.long	0x0000017c
      58:	0000017c 	.long	0x0000017c
      5c:	0000017c 	.long	0x0000017c
      60:	0000017c 	.long	0x0000017c
      64:	0000017c 	.long	0x0000017c
      68:	0000017c 	.long	0x0000017c
      6c:	0000017c 	.long	0x0000017c
      70:	0000017c 	.long	0x0000017c
      74:	0000017c 	.long	0x0000017c
      78:	0000017c 	.long	0x0000017c
      7c:	0000517c 	.long	0x0000517c
      80:	000048ec 	.long	0x000048ec
      84:	00004900 	.long	0x00004900
      88:	000049ac 	.long	0x000049ac
      8c:	00004eac 	.long	0x00004eac
      90:	00004bf4 	.long	0x00004bf4
      94:	00004c70 	.long	0x00004c70
      98:	00004cec 	.long	0x00004cec
      9c:	000049f8 	.long	0x000049f8
      a0:	00004a14 	.long	0x00004a14
      a4:	00004fa4 	.long	0x00004fa4
      a8:	00004d8e 	.long	0x00004d8e
      ac:	00004e0e 	.long	0x00004e0e
      b0:	00004e7e 	.long	0x00004e7e
      b4:	00004b3a 	.long	0x00004b3a
      b8:	00004b7a 	.long	0x00004b7a
      bc:	0000017c 	.long	0x0000017c
      c0:	0000017c 	.long	0x0000017c
      c4:	00004be0 	.long	0x00004be0
      c8:	0000017c 	.long	0x0000017c
      cc:	00004f42 	.long	0x00004f42
      d0:	0000017c 	.long	0x0000017c
      d4:	00004a30 	.long	0x00004a30
      d8:	00004a5a 	.long	0x00004a5a
      dc:	00004ab0 	.long	0x00004ab0
      e0:	0000017c 	.long	0x0000017c
      e4:	00005172 	.long	0x00005172
      e8:	0000017c 	.long	0x0000017c
      ec:	00004f1a 	.long	0x00004f1a
      f0:	00005108 	.long	0x00005108
      f4:	00005130 	.long	0x00005130
      f8:	0000017c 	.long	0x0000017c
      fc:	0000017c 	.long	0x0000017c
     100:	00000006 	.long	0x00000006

00000104 <__start>:
.text
.export __start
//  .long __start
__start:
  //initialize all registers
  movi r0, 0
     104:	3000      	movi      	r0, 0
  movi r1, 0
     106:	3100      	movi      	r1, 0
  movi r2, 0
     108:	3200      	movi      	r2, 0
  movi r3, 0
     10a:	3300      	movi      	r3, 0
  movi r4, 0
     10c:	3400      	movi      	r4, 0
  movi r5, 0
     10e:	3500      	movi      	r5, 0
  movi r6, 0
     110:	3600      	movi      	r6, 0
  movi r7, 0
     112:	3700      	movi      	r7, 0
  //movi r13, 0
  //movi r14, 0
  //movi r15, 0

//set VBR
  lrw r2, vector_table
     114:	105b      	lrw      	r2, 0	// 180 <DummyHandler+0x4>
  mtcr r2, cr<1,0>
     116:	c0026421 	mtcr      	r2, cr<1, 0>

//enable EE bit of psr
  mfcr r2, cr<0,0>
     11a:	c0006022 	mfcr      	r2, cr<0, 0>
  bseti r2, r2, 8
     11e:	3aa8      	bseti      	r2, r2, 8
  mtcr r2, cr<0,0>
     120:	c0026420 	mtcr      	r2, cr<0, 0>
//  st.w    r2, (r1,0x4)
//  movi    r2, 0x1
//  st.w    r2, (r1,0x0)

//disable power peak 
  lrw     r1, 0xe000ef90
     124:	1038      	lrw      	r1, 0xe000ef90	// 184 <DummyHandler+0x8>
  movi    r2, 0x0
     126:	3200      	movi      	r2, 0
  st.w    r2, (r1, 0x0)
     128:	b140      	st.w      	r2, (r1, 0)

//initialize kernel stack
  lrw  r7, __kernel_stack
     12a:	10f8      	lrw      	r7, 0x200017f8	// 188 <DummyHandler+0xc>
  mov r14,r7
     12c:	6f9f      	mov      	sp, r7
  subi r6,r7,0x4
     12e:	5fcf      	subi      	r6, r7, 4
  lrw  r3, 0x40
     130:	3340      	movi      	r3, 64
  subu r4, r7, r3
     132:	5f8d      	subu      	r4, r7, r3
  lrw  r5, 0x0
     134:	3500      	movi      	r5, 0

00000136 <INIT_KERLE_STACK>:
INIT_KERLE_STACK:
  addi r4, 0x4
     136:	2403      	addi      	r4, 4
  st.w r5, (r4)
     138:	b4a0      	st.w      	r5, (r4, 0)
  //cmphs r7, r4
  cmphs r6, r4
     13a:	6518      	cmphs      	r6, r4
  bt  INIT_KERLE_STACK
     13c:	0bfd      	bt      	0x136	// 136 <INIT_KERLE_STACK>

0000013e <__to_main>:
        
__to_main:
  lrw r0,__main
     13e:	1014      	lrw      	r0, 0x1ac	// 18c <DummyHandler+0x10>
  jsr r0
     140:	7bc1      	jsr      	r0
  mov r0, r0
     142:	6c03      	mov      	r0, r0
  mov r0, r0
     144:	6c03      	mov      	r0, r0

  lrw r15, __exit
     146:	ea8f0013 	lrw      	r15, 0x158	// 190 <DummyHandler+0x14>
  lrw r0,main
     14a:	1013      	lrw      	r0, 0x53bc	// 194 <DummyHandler+0x18>
  jmp r0
     14c:	7800      	jmp      	r0
  mov r0, r0
     14e:	6c03      	mov      	r0, r0
  mov r0, r0
     150:	6c03      	mov      	r0, r0
  mov r0, r0
     152:	6c03      	mov      	r0, r0
  mov r0, r0
     154:	6c03      	mov      	r0, r0
  mov r0, r0
     156:	6c03      	mov      	r0, r0

00000158 <__exit>:

.export __exit
__exit:

  lrw r4, 0x20003000
     158:	1090      	lrw      	r4, 0x20003000	// 198 <DummyHandler+0x1c>
  //lrw r5, 0x0
  mov r5, r0
     15a:	6d43      	mov      	r5, r0
  st.w r5, (r4)
     15c:	b4a0      	st.w      	r5, (r4, 0)

  mfcr r1, cr<0,0>
     15e:	c0006021 	mfcr      	r1, cr<0, 0>
  lrw  r1, 0xFFFF
     162:	102f      	lrw      	r1, 0xffff	// 19c <DummyHandler+0x20>
  mtcr r1, cr<11,0>
     164:	c001642b 	mtcr      	r1, cr<11, 0>
  lrw     r1, 0xFFF
     168:	102e      	lrw      	r1, 0xfff	// 1a0 <DummyHandler+0x24>
  movi    r0, 0x0
     16a:	3000      	movi      	r0, 0
  st      r1, (r0)
     16c:	b020      	st.w      	r1, (r0, 0)

0000016e <__fail>:

.export __fail
__fail:
  lrw  r1, 0xEEEE
     16e:	102e      	lrw      	r1, 0xeeee	// 1a4 <DummyHandler+0x28>
  mtcr r1, cr<11,0>
     170:	c001642b 	mtcr      	r1, cr<11, 0>
  lrw     r1, 0xEEE
     174:	102d      	lrw      	r1, 0xeee	// 1a8 <DummyHandler+0x2c>
  movi    r0, 0x0
     176:	3000      	movi      	r0, 0
  st      r1, (r0)
     178:	b020      	st.w      	r1, (r0, 0)

0000017a <__dummy>:

__dummy:
  br      __fail
     17a:	07fa      	br      	0x16e	// 16e <__fail>

0000017c <DummyHandler>:

.export DummyHandler
DummyHandler:
  br      __fail
     17c:	07f9      	br      	0x16e	// 16e <__fail>
     17e:	0000      	.short	0x0000
     180:	00000000 	.long	0x00000000
     184:	e000ef90 	.long	0xe000ef90
     188:	200017f8 	.long	0x200017f8
     18c:	000001ac 	.long	0x000001ac
     190:	00000158 	.long	0x00000158
     194:	000053bc 	.long	0x000053bc
     198:	20003000 	.long	0x20003000
     19c:	0000ffff 	.long	0x0000ffff
     1a0:	00000fff 	.long	0x00000fff
     1a4:	0000eeee 	.long	0x0000eeee
     1a8:	00000eee 	.long	0x00000eee

000001ac <__main>:
extern char _bss_start[];
extern char _ebss[];


void __main( void ) 
{
     1ac:	14d0      	push      	r15

  /* if the start of data (dst)
     is not equal to end of text (src) then
     copy it, else it's already in the right place
     */
  if( _start_data != _end_rodata ) {
     1ae:	1009      	lrw      	r0, 0x20000000	// 1d0 <__main+0x24>
     1b0:	1029      	lrw      	r1, 0x53d8	// 1d4 <__main+0x28>
     1b2:	6442      	cmpne      	r0, r1
     1b4:	0c05      	bf      	0x1be	// 1be <__main+0x12>
//    __memcpy_fast( dst, src, (_end_data - _start_data));
    memcpy( dst, src, (_end_data - _start_data));
     1b6:	1049      	lrw      	r2, 0x20000068	// 1d8 <__main+0x2c>
     1b8:	6082      	subu      	r2, r0
     1ba:	e000288b 	bsr      	0x52d0	// 52d0 <__memcpy_fast>
  }

  /* zero the bss 
   */
  if( _ebss - _bss_start ) {
     1be:	1048      	lrw      	r2, 0x200002d8	// 1dc <__main+0x30>
     1c0:	1008      	lrw      	r0, 0x20000068	// 1e0 <__main+0x34>
     1c2:	640a      	cmpne      	r2, r0
     1c4:	0c05      	bf      	0x1ce	// 1ce <__main+0x22>
//    __memset_fast( _bss_start, 0x00, ( _ebss - _bss_start ));
    memset( _bss_start, 0x00, ( _ebss - _bss_start ));
     1c6:	6082      	subu      	r2, r0
     1c8:	3100      	movi      	r1, 0
     1ca:	e00028b5 	bsr      	0x5334	// 5334 <__memset_fast>
  }
}
     1ce:	1490      	pop      	r15
     1d0:	20000000 	.long	0x20000000
     1d4:	000053d8 	.long	0x000053d8
     1d8:	20000068 	.long	0x20000068
     1dc:	200002d8 	.long	0x200002d8
     1e0:	20000068 	.long	0x20000068

000001e4 <CK801_int_Init>:


void CK801_int_Init(void)
{
        /* Initial the Interrupt source priority level registers */
        CK801->IPR[0] = 0xC0804000;
     1e4:	1072      	lrw      	r3, 0x20000064	// 22c <CK801_int_Init+0x48>
     1e6:	3180      	movi      	r1, 128
     1e8:	9360      	ld.w      	r3, (r3, 0)
     1ea:	4123      	lsli      	r1, r1, 3
     1ec:	1051      	lrw      	r2, 0xc0804000	// 230 <CK801_int_Init+0x4c>
     1ee:	604c      	addu      	r1, r3
     1f0:	b140      	st.w      	r2, (r1, 0)
        CK801->IPR[1] = 0xC0804000;
     1f2:	1031      	lrw      	r1, 0x404	// 234 <CK801_int_Init+0x50>
     1f4:	604c      	addu      	r1, r3
     1f6:	b140      	st.w      	r2, (r1, 0)
        CK801->IPR[2] = 0xC0804000;
     1f8:	3181      	movi      	r1, 129
     1fa:	4123      	lsli      	r1, r1, 3
     1fc:	604c      	addu      	r1, r3
     1fe:	b140      	st.w      	r2, (r1, 0)
        CK801->IPR[3] = 0xC0804000;
     200:	102e      	lrw      	r1, 0x40c	// 238 <CK801_int_Init+0x54>
     202:	604c      	addu      	r1, r3
     204:	b140      	st.w      	r2, (r1, 0)
        CK801->IPR[4] = 0xC0804000;
     206:	3182      	movi      	r1, 130
     208:	4123      	lsli      	r1, r1, 3
     20a:	604c      	addu      	r1, r3
     20c:	b140      	st.w      	r2, (r1, 0)
        CK801->IPR[5] = 0xC0804000;
     20e:	102c      	lrw      	r1, 0x414	// 23c <CK801_int_Init+0x58>
     210:	604c      	addu      	r1, r3
     212:	b140      	st.w      	r2, (r1, 0)
        CK801->IPR[6] = 0xC0804000;
     214:	3183      	movi      	r1, 131
     216:	4123      	lsli      	r1, r1, 3
     218:	604c      	addu      	r1, r3
     21a:	b140      	st.w      	r2, (r1, 0)
        CK801->IPR[7] = 0xC0804000;
     21c:	1029      	lrw      	r1, 0x41c	// 240 <CK801_int_Init+0x5c>
     21e:	604c      	addu      	r1, r3
     220:	b140      	st.w      	r2, (r1, 0)

        CK801->IPTR 	 = 0x00000000;//disable threshold
     222:	1049      	lrw      	r2, 0xc04	// 244 <CK801_int_Init+0x60>
     224:	60c8      	addu      	r3, r2
     226:	3200      	movi      	r2, 0
     228:	b340      	st.w      	r2, (r3, 0)
}
     22a:	783c      	rts
     22c:	20000064 	.long	0x20000064
     230:	c0804000 	.long	0xc0804000
     234:	00000404 	.long	0x00000404
     238:	0000040c 	.long	0x0000040c
     23c:	00000414 	.long	0x00000414
     240:	0000041c 	.long	0x0000041c
     244:	00000c04 	.long	0x00000c04

00000248 <force_interrupt>:

void force_interrupt(IRQn_Type IRQn)
{
	CK801->ISPR = (1 << (uint32_t)(IRQn));
     248:	1068      	lrw      	r3, 0x20000064	// 268 <CK_CPU_DisAllNormalIrq+0x8>
     24a:	3180      	movi      	r1, 128
     24c:	9360      	ld.w      	r3, (r3, 0)
     24e:	4122      	lsli      	r1, r1, 2
     250:	3201      	movi      	r2, 1
     252:	7080      	lsl      	r2, r0
     254:	60c4      	addu      	r3, r1
     256:	b340      	st.w      	r2, (r3, 0)
}
     258:	783c      	rts

0000025a <CK_CPU_EnAllNormalIrq>:


void CK_CPU_EnAllNormalIrq(void)
{
  asm  ("psrset ee,ie");
     25a:	c1807420 	psrset      	ee, ie
}
     25e:	783c      	rts

00000260 <CK_CPU_DisAllNormalIrq>:

void CK_CPU_DisAllNormalIrq(void)
{
 asm  ("psrclr ie");
     260:	c0807020 	psrclr      	ie
}
     264:	783c      	rts
     266:	0000      	bkpt
     268:	20000064 	.long	0x20000064

0000026c <CMP_RESET_VALUE>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void CMP_RESET_VALUE(void)
{
		CMP->CEDR=CMP_CEDR_RST;     			/**< CMP_CEDR  reset value  */
     26c:	106f      	lrw      	r3, 0x20000004	// 2a8 <CMP_RESET_VALUE+0x3c>
     26e:	1050      	lrw      	r2, 0x2090000	// 2ac <CMP_RESET_VALUE+0x40>
     270:	9360      	ld.w      	r3, (r3, 0)
     272:	b340      	st.w      	r2, (r3, 0)
		CMP->CR0=CMP_CR0_RST;     				/**< CMP_CR0  reset value  	*/
     274:	3240      	movi      	r2, 64
     276:	b341      	st.w      	r2, (r3, 0x4)
		CMP->CR1=CMP_CR1_RST;					/**< CMP_CR1  reset value  	*/
     278:	b342      	st.w      	r2, (r3, 0x8)
		CMP->CR2=CMP_CR2_RST;     				/**< CMP_CR2  reset value  	*/
     27a:	b343      	st.w      	r2, (r3, 0xc)
		CMP->CR3=CMP_CR3_RST;     				/**< CMP_CR3  reset value  	*/
     27c:	b344      	st.w      	r2, (r3, 0x10)
		CMP->CR4=CMP_CR4_RST;     				/**< CMP_CR4  reset value  	*/
     27e:	b345      	st.w      	r2, (r3, 0x14)
		CMP->FLTCR0=CMP_FLTCR0_RST;     		/**< CMP_FLTCR0  reset value*/
     280:	3200      	movi      	r2, 0
     282:	b346      	st.w      	r2, (r3, 0x18)
		CMP->FLTCR1=CMP_FLTCR1_RST;     		/**< CMP_FLTCR1  reset value*/
     284:	b347      	st.w      	r2, (r3, 0x1c)
		CMP->FLTCR2=CMP_FLTCR2_RST;     		/**< CMP_FLTCR2  reset value*/
     286:	b348      	st.w      	r2, (r3, 0x20)
		CMP->FLTCR3=CMP_FLTCR3_RST;     		/**< CMP_FLTCR3  reset value*/
     288:	b349      	st.w      	r2, (r3, 0x24)
		CMP->FLTCR4=CMP_FLTCR4_RST;     		/**< CMP_FLTCR4  reset value*/
     28a:	b34a      	st.w      	r2, (r3, 0x28)
		CMP->WCNT0=CMP_WCNT0_RST;				/**< CMP_WCNT0   reset value*/
     28c:	b34b      	st.w      	r2, (r3, 0x2c)
		CMP->WCNT1=CMP_WCNT1_RST;				/**< CMP_WCNT1   reset value*/
     28e:	b34c      	st.w      	r2, (r3, 0x30)
		CMP->WCNT2=CMP_WCNT2_RST;				/**< CMP_WCNT2   reset value*/
     290:	b34d      	st.w      	r2, (r3, 0x34)
		CMP->INPCR0=CMP_INPCR0_RST;				/**< CMP_INPCR0  reset value*/
     292:	b34e      	st.w      	r2, (r3, 0x38)
		CMP->INPCR1=CMP_INPCR1_RST;				/**< CMP_INPCR1  reset value*/
     294:	b34f      	st.w      	r2, (r3, 0x3c)
		CMP->INPCR2=CMP_INPCR2_RST;				/**< CMP_INPCR2  reset value*/
     296:	b350      	st.w      	r2, (r3, 0x40)
		CMP->INPCR3=CMP_INPCR3_RST;				/**< CMP_INPCR3  reset value*/
     298:	b351      	st.w      	r2, (r3, 0x44)
		CMP->INPCR4=CMP_INPCR4_RST;				/**< CMP_INPCR4  reset value*/
     29a:	b352      	st.w      	r2, (r3, 0x48)
		CMP->TRGCR=CMP_TRGCR_RST;				/**< CMP_TRGCR   reset value*/	
     29c:	b353      	st.w      	r2, (r3, 0x4c)
		CMP->IMCR=CMP_IMCR_RST;					/**< CMP_IMCR    reset value*/	
     29e:	b354      	st.w      	r2, (r3, 0x50)
		CMP->RISR=CMP_RISR_RST;					/**< CMP_RISR    reset value*/	
     2a0:	b355      	st.w      	r2, (r3, 0x54)
		CMP->MISR=CMP_MISR_RST;					/**< CMP_MISR    reset value*/	
     2a2:	b356      	st.w      	r2, (r3, 0x58)
		CMP->ICR=CMP_ICR_RST;					/**< CMP_ICR     reset value*/	
     2a4:	b357      	st.w      	r2, (r3, 0x5c)
}
     2a6:	783c      	rts
     2a8:	20000004 	.long	0x20000004
     2ac:	02090000 	.long	0x02090000

000002b0 <CMP_software_reset>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void CMP_software_reset(void)
{
	CMP->CEDR|=(0X01<<7);
     2b0:	127d      	lrw      	r3, 0x20000004	// 424 <CMP_IO_Init+0xf8>
     2b2:	9340      	ld.w      	r2, (r3, 0)
     2b4:	9260      	ld.w      	r3, (r2, 0)
     2b6:	3ba7      	bseti      	r3, r3, 7
     2b8:	b260      	st.w      	r3, (r2, 0)
}
     2ba:	783c      	rts

000002bc <CMP_CLK_CMD>:
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/  
void CMP_CLK_CMD(CMPx_selecte_TypeDef CMPx_NUM , FunctionalStatus NewState)
{
	if(CMPx_NUM==CMP0_NUM)
     2bc:	3840      	cmpnei      	r0, 0
     2be:	080b      	bt      	0x2d4	// 2d4 <CMP_CLK_CMD+0x18>
     2c0:	1279      	lrw      	r3, 0x20000004	// 424 <CMP_IO_Init+0xf8>
	{
		if(NewState != DISABLE)
     2c2:	3940      	cmpnei      	r1, 0
		{
			CMP->CEDR|=0X01;
     2c4:	9340      	ld.w      	r2, (r3, 0)
     2c6:	9260      	ld.w      	r3, (r2, 0)
		if(NewState != DISABLE)
     2c8:	0c04      	bf      	0x2d0	// 2d0 <CMP_CLK_CMD+0x14>
			CMP->CEDR|=0X01;
     2ca:	3ba0      	bseti      	r3, r3, 0
		{
			CMP->CEDR|=0X10;
		}
		else
		{
			CMP->CEDR&=0XFFFFFFEF;
     2cc:	b260      	st.w      	r3, (r2, 0)
		}
	}
}
     2ce:	783c      	rts
			CMP->CEDR&=0XFFFFFFFE;
     2d0:	3b80      	bclri      	r3, r3, 0
     2d2:	07fd      	br      	0x2cc	// 2cc <CMP_CLK_CMD+0x10>
	else if(CMPx_NUM==CMP1_NUM)
     2d4:	3841      	cmpnei      	r0, 1
     2d6:	080a      	bt      	0x2ea	// 2ea <CMP_CLK_CMD+0x2e>
     2d8:	1273      	lrw      	r3, 0x20000004	// 424 <CMP_IO_Init+0xf8>
		if(NewState != DISABLE)
     2da:	3940      	cmpnei      	r1, 0
			CMP->CEDR|=0X02;
     2dc:	9340      	ld.w      	r2, (r3, 0)
     2de:	9260      	ld.w      	r3, (r2, 0)
		if(NewState != DISABLE)
     2e0:	0c03      	bf      	0x2e6	// 2e6 <CMP_CLK_CMD+0x2a>
			CMP->CEDR|=0X02;
     2e2:	3ba1      	bseti      	r3, r3, 1
     2e4:	07f4      	br      	0x2cc	// 2cc <CMP_CLK_CMD+0x10>
			CMP->CEDR&=0XFFFFFFFD;
     2e6:	3b81      	bclri      	r3, r3, 1
     2e8:	07f2      	br      	0x2cc	// 2cc <CMP_CLK_CMD+0x10>
	else if(CMPx_NUM==CMP2_NUM)
     2ea:	3842      	cmpnei      	r0, 2
     2ec:	080a      	bt      	0x300	// 300 <CMP_CLK_CMD+0x44>
     2ee:	126e      	lrw      	r3, 0x20000004	// 424 <CMP_IO_Init+0xf8>
		if(NewState != DISABLE)
     2f0:	3940      	cmpnei      	r1, 0
			CMP->CEDR|=0X04;
     2f2:	9340      	ld.w      	r2, (r3, 0)
     2f4:	9260      	ld.w      	r3, (r2, 0)
		if(NewState != DISABLE)
     2f6:	0c03      	bf      	0x2fc	// 2fc <CMP_CLK_CMD+0x40>
			CMP->CEDR|=0X04;
     2f8:	3ba2      	bseti      	r3, r3, 2
     2fa:	07e9      	br      	0x2cc	// 2cc <CMP_CLK_CMD+0x10>
			CMP->CEDR&=0XFFFFFFFB;
     2fc:	3b82      	bclri      	r3, r3, 2
     2fe:	07e7      	br      	0x2cc	// 2cc <CMP_CLK_CMD+0x10>
	else if(CMPx_NUM==CMP3_NUM)
     300:	3843      	cmpnei      	r0, 3
     302:	080a      	bt      	0x316	// 316 <CMP_CLK_CMD+0x5a>
     304:	1268      	lrw      	r3, 0x20000004	// 424 <CMP_IO_Init+0xf8>
		if(NewState != DISABLE)
     306:	3940      	cmpnei      	r1, 0
			CMP->CEDR|=0X8;
     308:	9340      	ld.w      	r2, (r3, 0)
     30a:	9260      	ld.w      	r3, (r2, 0)
		if(NewState != DISABLE)
     30c:	0c03      	bf      	0x312	// 312 <CMP_CLK_CMD+0x56>
			CMP->CEDR|=0X8;
     30e:	3ba3      	bseti      	r3, r3, 3
     310:	07de      	br      	0x2cc	// 2cc <CMP_CLK_CMD+0x10>
			CMP->CEDR&=0XFFFFFFF7;
     312:	3b83      	bclri      	r3, r3, 3
     314:	07dc      	br      	0x2cc	// 2cc <CMP_CLK_CMD+0x10>
	else if(CMPx_NUM==CMP4_NUM)
     316:	3844      	cmpnei      	r0, 4
     318:	0bdb      	bt      	0x2ce	// 2ce <CMP_CLK_CMD+0x12>
     31a:	1263      	lrw      	r3, 0x20000004	// 424 <CMP_IO_Init+0xf8>
		if(NewState != DISABLE)
     31c:	3940      	cmpnei      	r1, 0
			CMP->CEDR|=0X10;
     31e:	9340      	ld.w      	r2, (r3, 0)
     320:	9260      	ld.w      	r3, (r2, 0)
		if(NewState != DISABLE)
     322:	0c03      	bf      	0x328	// 328 <CMP_CLK_CMD+0x6c>
			CMP->CEDR|=0X10;
     324:	3ba4      	bseti      	r3, r3, 4
     326:	07d3      	br      	0x2cc	// 2cc <CMP_CLK_CMD+0x10>
			CMP->CEDR&=0XFFFFFFEF;
     328:	3b84      	bclri      	r3, r3, 4
     32a:	07d1      	br      	0x2cc	// 2cc <CMP_CLK_CMD+0x10>

0000032c <CMP_IO_Init>:
//CMP_IO_MODE_X:0~1
//ReturnValue:NONE
/*************************************************************/  
void CMP_IO_Init(CMP_IO_MODE_TypeDef  CMP_IO_MODE_X , U8_T CMP_IO_G )
{
	if(CMP_IO_MODE_X==CPINP0)
     32c:	3840      	cmpnei      	r0, 0
     32e:	080b      	bt      	0x344	// 344 <CMP_IO_Init+0x18>
	{
		if(CMP_IO_G==0)
     330:	3940      	cmpnei      	r1, 0
     332:	0849      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
		{
			GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFFF0)|0x0000000A;										//CPINP0(PB0.00->AF7)
     334:	117d      	lrw      	r3, 0x20000048	// 428 <CMP_IO_Init+0xfc>
	}
	else if(CMP_IO_MODE_X==CPINN1)
	{
		if(CMP_IO_G==0)
		{
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x0000000A;										//CPINN1(PA0.00->AF7)
     336:	9340      	ld.w      	r2, (r3, 0)
     338:	9260      	ld.w      	r3, (r2, 0)
     33a:	310f      	movi      	r1, 15
     33c:	68c5      	andn      	r3, r1
     33e:	3ba1      	bseti      	r3, r3, 1
     340:	3ba3      	bseti      	r3, r3, 3
     342:	0427      	br      	0x390	// 390 <CMP_IO_Init+0x64>
	else if(CMP_IO_MODE_X==CPINP1)
     344:	3841      	cmpnei      	r0, 1
     346:	080c      	bt      	0x35e	// 35e <CMP_IO_Init+0x32>
		if(CMP_IO_G==0)
     348:	3940      	cmpnei      	r1, 0
     34a:	083d      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFF0FFFFF)|0x00A00000;										//CPINP1(PA0.05->AF7)
     34c:	1178      	lrw      	r3, 0x20000050	// 42c <CMP_IO_Init+0x100>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00A00000;										//CPINP9(PA1.5->AF7)
     34e:	9320      	ld.w      	r1, (r3, 0)
     350:	32f0      	movi      	r2, 240
     352:	9160      	ld.w      	r3, (r1, 0)
     354:	4250      	lsli      	r2, r2, 16
     356:	68c9      	andn      	r3, r2
     358:	3bb5      	bseti      	r3, r3, 21
     35a:	3bb7      	bseti      	r3, r3, 23
     35c:	040d      	br      	0x376	// 376 <CMP_IO_Init+0x4a>
	else if(CMP_IO_MODE_X==CPINP2)
     35e:	3842      	cmpnei      	r0, 2
     360:	080d      	bt      	0x37a	// 37a <CMP_IO_Init+0x4e>
		if(CMP_IO_G==0)
     362:	3940      	cmpnei      	r1, 0
     364:	0830      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XF0FFFFFF)|0x0A000000;										//CPINP2(PA0.06->AF7)
     366:	1172      	lrw      	r3, 0x20000050	// 42c <CMP_IO_Init+0x100>
     368:	32f0      	movi      	r2, 240
     36a:	9320      	ld.w      	r1, (r3, 0)
     36c:	9160      	ld.w      	r3, (r1, 0)
     36e:	4254      	lsli      	r2, r2, 20
     370:	68c9      	andn      	r3, r2
     372:	3bb9      	bseti      	r3, r3, 25
     374:	3bbb      	bseti      	r3, r3, 27
	}
	else if(CMP_IO_MODE_X==CP3_OUT)
	{
		if(CMP_IO_G==0)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFF0FFFF)|0x00060000;										//CP3_OUT(PA1.4->AF3)
     376:	b160      	st.w      	r3, (r1, 0)
     378:	0426      	br      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
	else if(CMP_IO_MODE_X==CPINP3)
     37a:	3843      	cmpnei      	r0, 3
     37c:	080c      	bt      	0x394	// 394 <CMP_IO_Init+0x68>
		if(CMP_IO_G==0)
     37e:	3940      	cmpnei      	r1, 0
     380:	0822      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0X0FFFFFFF)|0xA0000000;										//CPINP3(PA0.07->AF7)
     382:	116b      	lrw      	r3, 0x20000050	// 42c <CMP_IO_Init+0x100>
     384:	9340      	ld.w      	r2, (r3, 0)
     386:	9260      	ld.w      	r3, (r2, 0)
     388:	4364      	lsli      	r3, r3, 4
     38a:	4b64      	lsri      	r3, r3, 4
     38c:	3bbd      	bseti      	r3, r3, 29
     38e:	3bbf      	bseti      	r3, r3, 31
	}
	else if(CMP_IO_MODE_X==CP4_OUT)
	{
		if(CMP_IO_G==0)
		{
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFFFF0)|0x00000007;										//CP4_OUT(PC0.0->AF4)
     390:	b260      	st.w      	r3, (r2, 0)
		}
	}
}
     392:	0419      	br      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
	else if(CMP_IO_MODE_X==CPINP4)
     394:	3844      	cmpnei      	r0, 4
     396:	080b      	bt      	0x3ac	// 3ac <CMP_IO_Init+0x80>
		if(CMP_IO_G==0)
     398:	3940      	cmpnei      	r1, 0
     39a:	0815      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFFF0)|0x0000000A;										//CPINN2(PA0.08->AF7)
     39c:	1164      	lrw      	r3, 0x20000050	// 42c <CMP_IO_Init+0x100>
     39e:	310f      	movi      	r1, 15
     3a0:	9340      	ld.w      	r2, (r3, 0)
     3a2:	9261      	ld.w      	r3, (r2, 0x4)
     3a4:	68c5      	andn      	r3, r1
     3a6:	3ba1      	bseti      	r3, r3, 1
     3a8:	3ba3      	bseti      	r3, r3, 3
     3aa:	040c      	br      	0x3c2	// 3c2 <CMP_IO_Init+0x96>
	else if(CMP_IO_MODE_X==CPINP5)
     3ac:	3845      	cmpnei      	r0, 5
     3ae:	080c      	bt      	0x3c6	// 3c6 <CMP_IO_Init+0x9a>
		if(CMP_IO_G==0)
     3b0:	3940      	cmpnei      	r1, 0
     3b2:	0809      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFF0F)|0x000000A0;										//CPINP5(PA0.09->AF7)
     3b4:	107e      	lrw      	r3, 0x20000050	// 42c <CMP_IO_Init+0x100>
     3b6:	31f0      	movi      	r1, 240
     3b8:	9340      	ld.w      	r2, (r3, 0)
     3ba:	9261      	ld.w      	r3, (r2, 0x4)
     3bc:	68c5      	andn      	r3, r1
     3be:	3ba5      	bseti      	r3, r3, 5
     3c0:	3ba7      	bseti      	r3, r3, 7
     3c2:	b261      	st.w      	r3, (r2, 0x4)
}
     3c4:	783c      	rts
	else if(CMP_IO_MODE_X==CPINP6)
     3c6:	3846      	cmpnei      	r0, 6
     3c8:	080d      	bt      	0x3e2	// 3e2 <CMP_IO_Init+0xb6>
		if(CMP_IO_G==0)
     3ca:	3940      	cmpnei      	r1, 0
     3cc:	0bfc      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFF0FFFF)|0x000A0000;										//CPINP6(PA0.12->AF7)
     3ce:	1078      	lrw      	r3, 0x20000050	// 42c <CMP_IO_Init+0x100>
     3d0:	32f0      	movi      	r2, 240
     3d2:	9320      	ld.w      	r1, (r3, 0)
     3d4:	9161      	ld.w      	r3, (r1, 0x4)
     3d6:	424c      	lsli      	r2, r2, 12
     3d8:	68c9      	andn      	r3, r2
     3da:	3bb1      	bseti      	r3, r3, 17
     3dc:	3bb3      	bseti      	r3, r3, 19
			GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x70000000;										//CP2_OUT(PA0.15->AF4)
     3de:	b161      	st.w      	r3, (r1, 0x4)
     3e0:	07f2      	br      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
	else if(CMP_IO_MODE_X==CPINP7)
     3e2:	3847      	cmpnei      	r0, 7
     3e4:	080c      	bt      	0x3fc	// 3fc <CMP_IO_Init+0xd0>
		if(CMP_IO_G==0)
     3e6:	3940      	cmpnei      	r1, 0
     3e8:	0bee      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x0A000000;										//CPINP7(PA0.14->AF7)
     3ea:	1071      	lrw      	r3, 0x20000050	// 42c <CMP_IO_Init+0x100>
     3ec:	32f0      	movi      	r2, 240
     3ee:	9320      	ld.w      	r1, (r3, 0)
     3f0:	9161      	ld.w      	r3, (r1, 0x4)
     3f2:	4254      	lsli      	r2, r2, 20
     3f4:	68c9      	andn      	r3, r2
     3f6:	3bb9      	bseti      	r3, r3, 25
     3f8:	3bbb      	bseti      	r3, r3, 27
     3fa:	07f2      	br      	0x3de	// 3de <CMP_IO_Init+0xb2>
	else if(CMP_IO_MODE_X==CPINP8)
     3fc:	3848      	cmpnei      	r0, 8
     3fe:	080c      	bt      	0x416	// 416 <CMP_IO_Init+0xea>
		if(CMP_IO_G==0)
     400:	3940      	cmpnei      	r1, 0
     402:	0be1      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFF0FFFF)|0x000A0000;										//CPINP8(PA1.4->AF7)
     404:	106b      	lrw      	r3, 0x2000004c	// 430 <CMP_IO_Init+0x104>
     406:	32f0      	movi      	r2, 240
     408:	9320      	ld.w      	r1, (r3, 0)
     40a:	9160      	ld.w      	r3, (r1, 0)
     40c:	424c      	lsli      	r2, r2, 12
     40e:	68c9      	andn      	r3, r2
     410:	3bb1      	bseti      	r3, r3, 17
     412:	3bb3      	bseti      	r3, r3, 19
     414:	07b1      	br      	0x376	// 376 <CMP_IO_Init+0x4a>
	else if(CMP_IO_MODE_X==CPINP9)
     416:	3849      	cmpnei      	r0, 9
     418:	080e      	bt      	0x434	// 434 <CMP_IO_Init+0x108>
		if(CMP_IO_G==0)
     41a:	3940      	cmpnei      	r1, 0
     41c:	0bd4      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00A00000;										//CPINP9(PA1.5->AF7)
     41e:	1065      	lrw      	r3, 0x2000004c	// 430 <CMP_IO_Init+0x104>
     420:	0797      	br      	0x34e	// 34e <CMP_IO_Init+0x22>
     422:	0000      	bkpt
     424:	20000004 	.long	0x20000004
     428:	20000048 	.long	0x20000048
     42c:	20000050 	.long	0x20000050
     430:	2000004c 	.long	0x2000004c
	else if(CMP_IO_MODE_X==CPINN0)
     434:	384a      	cmpnei      	r0, 10
     436:	080b      	bt      	0x44c	// 44c <CMP_IO_Init+0x120>
		if(CMP_IO_G==0)
     438:	3940      	cmpnei      	r1, 0
     43a:	0bc5      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x000000A0;										//CPINN0(PB0.01->AF7)
     43c:	1361      	lrw      	r3, 0x20000048	// 5c0 <CMP_CR_Config+0x4>
     43e:	31f0      	movi      	r1, 240
     440:	9340      	ld.w      	r2, (r3, 0)
     442:	9260      	ld.w      	r3, (r2, 0)
     444:	68c5      	andn      	r3, r1
     446:	3ba5      	bseti      	r3, r3, 5
     448:	3ba7      	bseti      	r3, r3, 7
     44a:	07a3      	br      	0x390	// 390 <CMP_IO_Init+0x64>
	else if(CMP_IO_MODE_X==CPINN1)
     44c:	384b      	cmpnei      	r0, 11
     44e:	0805      	bt      	0x458	// 458 <CMP_IO_Init+0x12c>
		if(CMP_IO_G==0)
     450:	3940      	cmpnei      	r1, 0
     452:	0bb9      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x0000000A;										//CPINN1(PA0.00->AF7)
     454:	127c      	lrw      	r3, 0x20000050	// 5c4 <CMP_CR_Config+0x8>
     456:	0770      	br      	0x336	// 336 <CMP_IO_Init+0xa>
	else if(CMP_IO_MODE_X==CPINN2)
     458:	384c      	cmpnei      	r0, 12
     45a:	0f9f      	bf      	0x398	// 398 <CMP_IO_Init+0x6c>
	else if(CMP_IO_MODE_X==CPINN3)
     45c:	384d      	cmpnei      	r0, 13
     45e:	080c      	bt      	0x476	// 476 <CMP_IO_Init+0x14a>
		if(CMP_IO_G==0)
     460:	3940      	cmpnei      	r1, 0
     462:	0bb1      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFF0FF)|0x00000A00;										//CPINN3(PA0.10->AF7)
     464:	1278      	lrw      	r3, 0x20000050	// 5c4 <CMP_CR_Config+0x8>
     466:	32f0      	movi      	r2, 240
     468:	9320      	ld.w      	r1, (r3, 0)
     46a:	9161      	ld.w      	r3, (r1, 0x4)
     46c:	4244      	lsli      	r2, r2, 4
     46e:	68c9      	andn      	r3, r2
     470:	3ba9      	bseti      	r3, r3, 9
     472:	3bab      	bseti      	r3, r3, 11
     474:	07b5      	br      	0x3de	// 3de <CMP_IO_Init+0xb2>
	else if(CMP_IO_MODE_X==CPINN4)
     476:	384e      	cmpnei      	r0, 14
     478:	080c      	bt      	0x490	// 490 <CMP_IO_Init+0x164>
		if(CMP_IO_G==0)
     47a:	3940      	cmpnei      	r1, 0
     47c:	0ba4      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFF0FFFFF)|0x00A00000;										//CPINN4(PA0.13->AF7)
     47e:	1272      	lrw      	r3, 0x20000050	// 5c4 <CMP_CR_Config+0x8>
     480:	32f0      	movi      	r2, 240
     482:	9320      	ld.w      	r1, (r3, 0)
     484:	9161      	ld.w      	r3, (r1, 0x4)
     486:	4250      	lsli      	r2, r2, 16
     488:	68c9      	andn      	r3, r2
     48a:	3bb5      	bseti      	r3, r3, 21
     48c:	3bb7      	bseti      	r3, r3, 23
     48e:	07a8      	br      	0x3de	// 3de <CMP_IO_Init+0xb2>
	else if(CMP_IO_MODE_X==CP0_OUT)
     490:	384f      	cmpnei      	r0, 15
     492:	0813      	bt      	0x4b8	// 4b8 <CMP_IO_Init+0x18c>
		if(CMP_IO_G==0)
     494:	3940      	cmpnei      	r1, 0
     496:	0807      	bt      	0x4a4	// 4a4 <CMP_IO_Init+0x178>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000007;										//CP0_OUT(PA0.0->AF4)
     498:	126b      	lrw      	r3, 0x20000050	// 5c4 <CMP_CR_Config+0x8>
     49a:	9340      	ld.w      	r2, (r3, 0)
     49c:	9260      	ld.w      	r3, (r2, 0)
     49e:	68c1      	andn      	r3, r0
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFFFF0)|0x00000007;										//CP4_OUT(PC0.0->AF4)
     4a0:	3107      	movi      	r1, 7
     4a2:	0415      	br      	0x4cc	// 4cc <CMP_IO_Init+0x1a0>
		else if(CMP_IO_G==1)
     4a4:	3941      	cmpnei      	r1, 1
     4a6:	0b8f      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFF0F)|0x00000060;										//CP0_OUT(PA0.1->AF3)
     4a8:	1267      	lrw      	r3, 0x20000050	// 5c4 <CMP_CR_Config+0x8>
     4aa:	31f0      	movi      	r1, 240
     4ac:	9340      	ld.w      	r2, (r3, 0)
     4ae:	9260      	ld.w      	r3, (r2, 0)
     4b0:	68c5      	andn      	r3, r1
     4b2:	3ba5      	bseti      	r3, r3, 5
     4b4:	3ba6      	bseti      	r3, r3, 6
     4b6:	076d      	br      	0x390	// 390 <CMP_IO_Init+0x64>
	else if(CMP_IO_MODE_X==CP1_OUT)
     4b8:	3850      	cmpnei      	r0, 16
     4ba:	080b      	bt      	0x4d0	// 4d0 <CMP_IO_Init+0x1a4>
		if(CMP_IO_G==0)
     4bc:	3940      	cmpnei      	r1, 0
     4be:	0b83      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFF0F)|0x00000070;										//CP1_OUT(PA0.1->AF4)
     4c0:	1261      	lrw      	r3, 0x20000050	// 5c4 <CMP_CR_Config+0x8>
     4c2:	31f0      	movi      	r1, 240
     4c4:	9340      	ld.w      	r2, (r3, 0)
     4c6:	9260      	ld.w      	r3, (r2, 0)
     4c8:	68c5      	andn      	r3, r1
     4ca:	3170      	movi      	r1, 112
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFFFF0)|0x00000007;										//CP4_OUT(PC0.0->AF4)
     4cc:	6cc4      	or      	r3, r1
     4ce:	0761      	br      	0x390	// 390 <CMP_IO_Init+0x64>
	else if(CMP_IO_MODE_X==CP2_OUT)
     4d0:	3851      	cmpnei      	r0, 17
     4d2:	080c      	bt      	0x4ea	// 4ea <CMP_IO_Init+0x1be>
		if(CMP_IO_G==0)
     4d4:	3940      	cmpnei      	r1, 0
     4d6:	0b77      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x70000000;										//CP2_OUT(PA0.15->AF4)
     4d8:	117b      	lrw      	r3, 0x20000050	// 5c4 <CMP_CR_Config+0x8>
     4da:	32e0      	movi      	r2, 224
     4dc:	9320      	ld.w      	r1, (r3, 0)
     4de:	9161      	ld.w      	r3, (r1, 0x4)
     4e0:	4364      	lsli      	r3, r3, 4
     4e2:	4b64      	lsri      	r3, r3, 4
     4e4:	4257      	lsli      	r2, r2, 23
     4e6:	6cc8      	or      	r3, r2
     4e8:	077b      	br      	0x3de	// 3de <CMP_IO_Init+0xb2>
	else if(CMP_IO_MODE_X==CP3_OUT)
     4ea:	3852      	cmpnei      	r0, 18
     4ec:	080c      	bt      	0x504	// 504 <CMP_IO_Init+0x1d8>
		if(CMP_IO_G==0)
     4ee:	3940      	cmpnei      	r1, 0
     4f0:	0b6a      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFF0FFFF)|0x00060000;										//CP3_OUT(PA1.4->AF3)
     4f2:	1176      	lrw      	r3, 0x2000004c	// 5c8 <CMP_CR_Config+0xc>
     4f4:	32f0      	movi      	r2, 240
     4f6:	9320      	ld.w      	r1, (r3, 0)
     4f8:	9160      	ld.w      	r3, (r1, 0)
     4fa:	424c      	lsli      	r2, r2, 12
     4fc:	68c9      	andn      	r3, r2
     4fe:	3bb1      	bseti      	r3, r3, 17
     500:	3bb2      	bseti      	r3, r3, 18
     502:	073a      	br      	0x376	// 376 <CMP_IO_Init+0x4a>
	else if(CMP_IO_MODE_X==CP4_OUT)
     504:	3853      	cmpnei      	r0, 19
     506:	0b5f      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
		if(CMP_IO_G==0)
     508:	3940      	cmpnei      	r1, 0
     50a:	0b5d      	bt      	0x3c4	// 3c4 <CMP_IO_Init+0x98>
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFFFF0)|0x00000007;										//CP4_OUT(PC0.0->AF4)
     50c:	1170      	lrw      	r3, 0x20000044	// 5cc <CMP_CR_Config+0x10>
     50e:	310f      	movi      	r1, 15
     510:	9340      	ld.w      	r2, (r3, 0)
     512:	9260      	ld.w      	r3, (r2, 0)
     514:	68c5      	andn      	r3, r1
     516:	07c5      	br      	0x4a0	// 4a0 <CMP_IO_Init+0x174>

00000518 <CMP_INPCRX_Config>:
//9:CPINP9
//13:OPA1X
//14:OPA0X
//-------------------------------------
void CMP_INPCRX_Config(CMPx_selecte_TypeDef CMPx_NUM , U8_T CMPX_NSEL , U8_T CMPX_PSEL )
{
     518:	14c1      	push      	r4
	if(CMPx_NUM==CMP0_NUM)
     51a:	3840      	cmpnei      	r0, 0
     51c:	080d      	bt      	0x536	// 536 <CMP_INPCRX_Config+0x1e>
	{
		CMP->INPCR0&=0xfffff000;
     51e:	116d      	lrw      	r3, 0x20000004	// 5d0 <CMP_CR_Config+0x14>
     520:	118d      	lrw      	r4, 0xfff	// 5d4 <CMP_CR_Config+0x18>
     522:	9360      	ld.w      	r3, (r3, 0)
     524:	930e      	ld.w      	r0, (r3, 0x38)
     526:	6811      	andn      	r0, r4
     528:	b30e      	st.w      	r0, (r3, 0x38)
		CMP->INPCR0|=CMPX_NSEL|(CMPX_PSEL<<8);
     52a:	4248      	lsli      	r2, r2, 8
     52c:	930e      	ld.w      	r0, (r3, 0x38)
     52e:	6c84      	or      	r2, r1
     530:	6c80      	or      	r2, r0
     532:	b34e      	st.w      	r2, (r3, 0x38)
	else if(CMPx_NUM==CMP4_NUM)
	{
		CMP->INPCR4&=0xfffff000;
		CMP->INPCR4|=CMPX_NSEL|(CMPX_PSEL<<8);
	}
}
     534:	1481      	pop      	r4
	else if(CMPx_NUM==CMP1_NUM)
     536:	3841      	cmpnei      	r0, 1
     538:	080d      	bt      	0x552	// 552 <CMP_INPCRX_Config+0x3a>
		CMP->INPCR1&=0xfffff000;
     53a:	1166      	lrw      	r3, 0x20000004	// 5d0 <CMP_CR_Config+0x14>
     53c:	1186      	lrw      	r4, 0xfff	// 5d4 <CMP_CR_Config+0x18>
     53e:	9360      	ld.w      	r3, (r3, 0)
     540:	930f      	ld.w      	r0, (r3, 0x3c)
     542:	6811      	andn      	r0, r4
     544:	b30f      	st.w      	r0, (r3, 0x3c)
		CMP->INPCR1|=CMPX_NSEL|(CMPX_PSEL<<8);
     546:	4248      	lsli      	r2, r2, 8
     548:	930f      	ld.w      	r0, (r3, 0x3c)
     54a:	6c84      	or      	r2, r1
     54c:	6c80      	or      	r2, r0
     54e:	b34f      	st.w      	r2, (r3, 0x3c)
     550:	07f2      	br      	0x534	// 534 <CMP_INPCRX_Config+0x1c>
	else if(CMPx_NUM==CMP2_NUM)
     552:	3842      	cmpnei      	r0, 2
     554:	080d      	bt      	0x56e	// 56e <CMP_INPCRX_Config+0x56>
		CMP->INPCR2&=0xfffff000;
     556:	107f      	lrw      	r3, 0x20000004	// 5d0 <CMP_CR_Config+0x14>
     558:	109f      	lrw      	r4, 0xfff	// 5d4 <CMP_CR_Config+0x18>
     55a:	9360      	ld.w      	r3, (r3, 0)
     55c:	9310      	ld.w      	r0, (r3, 0x40)
     55e:	6811      	andn      	r0, r4
     560:	b310      	st.w      	r0, (r3, 0x40)
		CMP->INPCR2|=CMPX_NSEL|(CMPX_PSEL<<8);
     562:	4248      	lsli      	r2, r2, 8
     564:	9310      	ld.w      	r0, (r3, 0x40)
     566:	6c84      	or      	r2, r1
     568:	6c80      	or      	r2, r0
     56a:	b350      	st.w      	r2, (r3, 0x40)
     56c:	07e4      	br      	0x534	// 534 <CMP_INPCRX_Config+0x1c>
	else if(CMPx_NUM==CMP3_NUM)
     56e:	3843      	cmpnei      	r0, 3
     570:	080d      	bt      	0x58a	// 58a <CMP_INPCRX_Config+0x72>
		CMP->INPCR3&=0xfffff000;
     572:	1078      	lrw      	r3, 0x20000004	// 5d0 <CMP_CR_Config+0x14>
     574:	1098      	lrw      	r4, 0xfff	// 5d4 <CMP_CR_Config+0x18>
     576:	9360      	ld.w      	r3, (r3, 0)
     578:	9311      	ld.w      	r0, (r3, 0x44)
     57a:	6811      	andn      	r0, r4
     57c:	b311      	st.w      	r0, (r3, 0x44)
		CMP->INPCR3|=CMPX_NSEL|(CMPX_PSEL<<8);
     57e:	4248      	lsli      	r2, r2, 8
     580:	9311      	ld.w      	r0, (r3, 0x44)
     582:	6c84      	or      	r2, r1
     584:	6c80      	or      	r2, r0
     586:	b351      	st.w      	r2, (r3, 0x44)
     588:	07d6      	br      	0x534	// 534 <CMP_INPCRX_Config+0x1c>
	else if(CMPx_NUM==CMP4_NUM)
     58a:	3844      	cmpnei      	r0, 4
     58c:	0bd4      	bt      	0x534	// 534 <CMP_INPCRX_Config+0x1c>
		CMP->INPCR4&=0xfffff000;
     58e:	1071      	lrw      	r3, 0x20000004	// 5d0 <CMP_CR_Config+0x14>
     590:	1091      	lrw      	r4, 0xfff	// 5d4 <CMP_CR_Config+0x18>
     592:	9360      	ld.w      	r3, (r3, 0)
     594:	9312      	ld.w      	r0, (r3, 0x48)
     596:	6811      	andn      	r0, r4
     598:	b312      	st.w      	r0, (r3, 0x48)
		CMP->INPCR4|=CMPX_NSEL|(CMPX_PSEL<<8);
     59a:	4248      	lsli      	r2, r2, 8
     59c:	9312      	ld.w      	r0, (r3, 0x48)
     59e:	6c84      	or      	r2, r1
     5a0:	6c80      	or      	r2, r0
     5a2:	b352      	st.w      	r2, (r3, 0x48)
}
     5a4:	07c8      	br      	0x534	// 534 <CMP_INPCRX_Config+0x1c>

000005a6 <CMPOutput_Read>:
//EntryParameter:CMPx_NUM
//ReturnValue:NONE
/*************************************************************/ 
void CMPOutput_Read(void)
{
	CMPOUTPUT_DATE=CMP->CR0&0XF0000000;
     5a6:	106b      	lrw      	r3, 0x20000004	// 5d0 <CMP_CR_Config+0x14>
     5a8:	104c      	lrw      	r2, 0x20000078	// 5d8 <CMP_CR_Config+0x1c>
     5aa:	9360      	ld.w      	r3, (r3, 0)
     5ac:	9361      	ld.w      	r3, (r3, 0x4)
     5ae:	4b7c      	lsri      	r3, r3, 28
     5b0:	437c      	lsli      	r3, r3, 28
     5b2:	b260      	st.w      	r3, (r2, 0)
	CMPOUTPUT_DATE=CMPOUTPUT_DATE>>27;
     5b4:	9260      	ld.w      	r3, (r2, 0)
     5b6:	4b7b      	lsri      	r3, r3, 27
     5b8:	b260      	st.w      	r3, (r2, 0)
}
     5ba:	783c      	rts

000005bc <CMP_CR_Config>:
//CPOS_X:CPOS_0,CPOS_1
//ReturnValue:NONE
/*************************************************************/ 
void CMP_CR_Config(CMPx_selecte_TypeDef CMPx_NUM , CMPx_NHYST_TypeDef NHYST_Xmv , CMPx_PHYST_TypeDef PHYST_Xmv , 
						CMPx_POLARITY_TypeDef POLARITY_X , CMPx_EVE_SEL_TypeDef EVE_SEL_X , CMPx_FLTEN_TypeDef X_FLTEN , CMPx_CPOS_TypeDef CPOS_X)
{
     5bc:	14c4      	push      	r4-r7
     5be:	040f      	br      	0x5dc	// 5dc <CMP_CR_Config+0x20>
     5c0:	20000048 	.long	0x20000048
     5c4:	20000050 	.long	0x20000050
     5c8:	2000004c 	.long	0x2000004c
     5cc:	20000044 	.long	0x20000044
     5d0:	20000004 	.long	0x20000004
     5d4:	00000fff 	.long	0x00000fff
     5d8:	20000078 	.long	0x20000078
     5dc:	1421      	subi      	sp, sp, 4
     5de:	9885      	ld.w      	r4, (sp, 0x14)
	if(CMPx_NUM==CMP0_NUM)
     5e0:	3840      	cmpnei      	r0, 0
{
     5e2:	b880      	st.w      	r4, (sp, 0)
     5e4:	98a6      	ld.w      	r5, (sp, 0x18)
     5e6:	9887      	ld.w      	r4, (sp, 0x1c)
	if(CMPx_NUM==CMP0_NUM)
     5e8:	0812      	bt      	0x60c	// 60c <CMP_CR_Config+0x50>
	{
		CMP->CR0&=0xffff7861;
     5ea:	1217      	lrw      	r0, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     5ec:	12f7      	lrw      	r7, 0x879e	// 748 <CMPX_FLTCR_Config+0xc>
     5ee:	9000      	ld.w      	r0, (r0, 0)
     5f0:	90c1      	ld.w      	r6, (r0, 0x4)
     5f2:	699d      	andn      	r6, r7
     5f4:	b0c1      	st.w      	r6, (r0, 0x4)
		CMP->CR0|=NHYST_Xmv|PHYST_Xmv|POLARITY_X|EVE_SEL_X|X_FLTEN|CPOS_X;
     5f6:	90c1      	ld.w      	r6, (r0, 0x4)
     5f8:	6d18      	or      	r4, r6
     5fa:	6d50      	or      	r5, r4
     5fc:	9880      	ld.w      	r4, (sp, 0)
     5fe:	6d50      	or      	r5, r4
     600:	6cd4      	or      	r3, r5
     602:	6c8c      	or      	r2, r3
     604:	6c48      	or      	r1, r2
     606:	b021      	st.w      	r1, (r0, 0x4)
	else if(CMPx_NUM==CMP4_NUM)
	{
		CMP->CR4&=0xffff7861;
		CMP->CR4|=NHYST_Xmv|PHYST_Xmv|POLARITY_X|EVE_SEL_X|X_FLTEN|CPOS_X;
	}
}
     608:	1401      	addi      	sp, sp, 4
     60a:	1484      	pop      	r4-r7
	else if(CMPx_NUM==CMP1_NUM)
     60c:	3841      	cmpnei      	r0, 1
     60e:	0811      	bt      	0x630	// 630 <CMP_CR_Config+0x74>
		CMP->CR1&=0xffff7861;
     610:	120d      	lrw      	r0, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     612:	12ee      	lrw      	r7, 0x879e	// 748 <CMPX_FLTCR_Config+0xc>
     614:	9000      	ld.w      	r0, (r0, 0)
     616:	90c2      	ld.w      	r6, (r0, 0x8)
     618:	699d      	andn      	r6, r7
     61a:	b0c2      	st.w      	r6, (r0, 0x8)
		CMP->CR1|=NHYST_Xmv|PHYST_Xmv|POLARITY_X|EVE_SEL_X|X_FLTEN|CPOS_X;
     61c:	90c2      	ld.w      	r6, (r0, 0x8)
     61e:	6d18      	or      	r4, r6
     620:	6d50      	or      	r5, r4
     622:	9880      	ld.w      	r4, (sp, 0)
     624:	6d50      	or      	r5, r4
     626:	6cd4      	or      	r3, r5
     628:	6c8c      	or      	r2, r3
     62a:	6c48      	or      	r1, r2
     62c:	b022      	st.w      	r1, (r0, 0x8)
     62e:	07ed      	br      	0x608	// 608 <CMP_CR_Config+0x4c>
	else if(CMPx_NUM==CMP2_NUM)
     630:	3842      	cmpnei      	r0, 2
     632:	0811      	bt      	0x654	// 654 <CMP_CR_Config+0x98>
		CMP->CR2&=0xffff7861;
     634:	1204      	lrw      	r0, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     636:	12e5      	lrw      	r7, 0x879e	// 748 <CMPX_FLTCR_Config+0xc>
     638:	9000      	ld.w      	r0, (r0, 0)
     63a:	90c3      	ld.w      	r6, (r0, 0xc)
     63c:	699d      	andn      	r6, r7
     63e:	b0c3      	st.w      	r6, (r0, 0xc)
		CMP->CR2|=NHYST_Xmv|PHYST_Xmv|POLARITY_X|EVE_SEL_X|X_FLTEN|CPOS_X;
     640:	90c3      	ld.w      	r6, (r0, 0xc)
     642:	6d18      	or      	r4, r6
     644:	6d50      	or      	r5, r4
     646:	9880      	ld.w      	r4, (sp, 0)
     648:	6d50      	or      	r5, r4
     64a:	6cd4      	or      	r3, r5
     64c:	6c8c      	or      	r2, r3
     64e:	6c48      	or      	r1, r2
     650:	b023      	st.w      	r1, (r0, 0xc)
     652:	07db      	br      	0x608	// 608 <CMP_CR_Config+0x4c>
	else if(CMPx_NUM==CMP3_NUM)
     654:	3843      	cmpnei      	r0, 3
     656:	0811      	bt      	0x678	// 678 <CMP_CR_Config+0xbc>
		CMP->CR3&=0xffff7861;
     658:	111b      	lrw      	r0, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     65a:	11fc      	lrw      	r7, 0x879e	// 748 <CMPX_FLTCR_Config+0xc>
     65c:	9000      	ld.w      	r0, (r0, 0)
     65e:	90c4      	ld.w      	r6, (r0, 0x10)
     660:	699d      	andn      	r6, r7
     662:	b0c4      	st.w      	r6, (r0, 0x10)
		CMP->CR3|=NHYST_Xmv|PHYST_Xmv|POLARITY_X|EVE_SEL_X|X_FLTEN|CPOS_X;
     664:	90c4      	ld.w      	r6, (r0, 0x10)
     666:	6d18      	or      	r4, r6
     668:	6d50      	or      	r5, r4
     66a:	9880      	ld.w      	r4, (sp, 0)
     66c:	6d50      	or      	r5, r4
     66e:	6cd4      	or      	r3, r5
     670:	6c8c      	or      	r2, r3
     672:	6c48      	or      	r1, r2
     674:	b024      	st.w      	r1, (r0, 0x10)
     676:	07c9      	br      	0x608	// 608 <CMP_CR_Config+0x4c>
	else if(CMPx_NUM==CMP4_NUM)
     678:	3844      	cmpnei      	r0, 4
     67a:	0bc7      	bt      	0x608	// 608 <CMP_CR_Config+0x4c>
		CMP->CR4&=0xffff7861;
     67c:	1112      	lrw      	r0, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     67e:	11f3      	lrw      	r7, 0x879e	// 748 <CMPX_FLTCR_Config+0xc>
     680:	9000      	ld.w      	r0, (r0, 0)
     682:	90c5      	ld.w      	r6, (r0, 0x14)
     684:	699d      	andn      	r6, r7
     686:	b0c5      	st.w      	r6, (r0, 0x14)
		CMP->CR4|=NHYST_Xmv|PHYST_Xmv|POLARITY_X|EVE_SEL_X|X_FLTEN|CPOS_X;
     688:	90c5      	ld.w      	r6, (r0, 0x14)
     68a:	6d18      	or      	r4, r6
     68c:	6d50      	or      	r5, r4
     68e:	9880      	ld.w      	r4, (sp, 0)
     690:	6d50      	or      	r5, r4
     692:	6cd4      	or      	r3, r5
     694:	6c8c      	or      	r2, r3
     696:	6c48      	or      	r1, r2
     698:	b025      	st.w      	r1, (r0, 0x14)
}
     69a:	07b7      	br      	0x608	// 608 <CMP_CR_Config+0x4c>

0000069c <CMP_Open>:
//CMPx_selecte:CMP0_NUM,CMP1_NUM,CMP2_NUM,CMP3_NUM,CMP4_NUM
//ReturnValue:NONE
/*************************************************************/ 
void CMP_Open(CMPx_selecte_TypeDef CMPx_selecte)
{
	if(CMPx_selecte==CMP0_NUM)
     69c:	3840      	cmpnei      	r0, 0
     69e:	0807      	bt      	0x6ac	// 6ac <CMP_Open+0x10>
	{
		CMP->CR0|=0x01;									//比较器0打开
     6a0:	1169      	lrw      	r3, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     6a2:	9340      	ld.w      	r2, (r3, 0)
     6a4:	9261      	ld.w      	r3, (r2, 0x4)
     6a6:	3ba0      	bseti      	r3, r3, 0
     6a8:	b261      	st.w      	r3, (r2, 0x4)
	}
	else if(CMPx_selecte==CMP4_NUM)
	{
		CMP->CR4|=0x01;									//比较器4打开
	}
}
     6aa:	783c      	rts
	else if(CMPx_selecte==CMP1_NUM)
     6ac:	3841      	cmpnei      	r0, 1
     6ae:	0807      	bt      	0x6bc	// 6bc <CMP_Open+0x20>
		CMP->CR1|=0x01;									//比较器1打开
     6b0:	1165      	lrw      	r3, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     6b2:	9340      	ld.w      	r2, (r3, 0)
     6b4:	9262      	ld.w      	r3, (r2, 0x8)
     6b6:	6c0c      	or      	r0, r3
     6b8:	b202      	st.w      	r0, (r2, 0x8)
     6ba:	07f8      	br      	0x6aa	// 6aa <CMP_Open+0xe>
	else if(CMPx_selecte==CMP2_NUM)
     6bc:	3842      	cmpnei      	r0, 2
     6be:	0807      	bt      	0x6cc	// 6cc <CMP_Open+0x30>
		CMP->CR2|=0x01;									//比较器2打开
     6c0:	1161      	lrw      	r3, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     6c2:	9340      	ld.w      	r2, (r3, 0)
     6c4:	9263      	ld.w      	r3, (r2, 0xc)
     6c6:	3ba0      	bseti      	r3, r3, 0
     6c8:	b263      	st.w      	r3, (r2, 0xc)
     6ca:	07f0      	br      	0x6aa	// 6aa <CMP_Open+0xe>
	else if(CMPx_selecte==CMP3_NUM)
     6cc:	3843      	cmpnei      	r0, 3
     6ce:	0807      	bt      	0x6dc	// 6dc <CMP_Open+0x40>
		CMP->CR3|=0x01;									//比较器3打开
     6d0:	107d      	lrw      	r3, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     6d2:	9340      	ld.w      	r2, (r3, 0)
     6d4:	9264      	ld.w      	r3, (r2, 0x10)
     6d6:	3ba0      	bseti      	r3, r3, 0
     6d8:	b264      	st.w      	r3, (r2, 0x10)
     6da:	07e8      	br      	0x6aa	// 6aa <CMP_Open+0xe>
	else if(CMPx_selecte==CMP4_NUM)
     6dc:	3844      	cmpnei      	r0, 4
     6de:	0be6      	bt      	0x6aa	// 6aa <CMP_Open+0xe>
		CMP->CR4|=0x01;									//比较器4打开
     6e0:	1079      	lrw      	r3, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     6e2:	9340      	ld.w      	r2, (r3, 0)
     6e4:	9265      	ld.w      	r3, (r2, 0x14)
     6e6:	3ba0      	bseti      	r3, r3, 0
     6e8:	b265      	st.w      	r3, (r2, 0x14)
}
     6ea:	07e0      	br      	0x6aa	// 6aa <CMP_Open+0xe>

000006ec <CMP_Close>:
//CMPx_selecte:CMP0_NUM,CMP1_NUM,CMP2_NUM,CMP3_NUM,CMP4_NUM
//ReturnValue:NONE
/*************************************************************/ 
void CMP_Close(CMPx_selecte_TypeDef CMPx_selecte)
{
	if(CMPx_selecte==CMP0_NUM)
     6ec:	3840      	cmpnei      	r0, 0
     6ee:	0807      	bt      	0x6fc	// 6fc <CMP_Close+0x10>
	{
		CMP->CR0&=0xfffffffe;									//比较器0关闭
     6f0:	1075      	lrw      	r3, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     6f2:	9340      	ld.w      	r2, (r3, 0)
     6f4:	9261      	ld.w      	r3, (r2, 0x4)
     6f6:	3b80      	bclri      	r3, r3, 0
     6f8:	b261      	st.w      	r3, (r2, 0x4)
	}
	else if(CMPx_selecte==CMP4_NUM)
	{
		CMP->CR4&=0xfffffffe;									//比较器4关闭
	}
}
     6fa:	783c      	rts
	else if(CMPx_selecte==CMP1_NUM)
     6fc:	3841      	cmpnei      	r0, 1
     6fe:	0807      	bt      	0x70c	// 70c <CMP_Close+0x20>
		CMP->CR1&=0xfffffffe;									//比较器1关闭
     700:	1071      	lrw      	r3, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     702:	9340      	ld.w      	r2, (r3, 0)
     704:	9262      	ld.w      	r3, (r2, 0x8)
     706:	3b80      	bclri      	r3, r3, 0
     708:	b262      	st.w      	r3, (r2, 0x8)
     70a:	07f8      	br      	0x6fa	// 6fa <CMP_Close+0xe>
	else if(CMPx_selecte==CMP2_NUM)
     70c:	3842      	cmpnei      	r0, 2
     70e:	0807      	bt      	0x71c	// 71c <CMP_Close+0x30>
		CMP->CR2&=0xfffffffe;									//比较器2关闭
     710:	106d      	lrw      	r3, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     712:	9340      	ld.w      	r2, (r3, 0)
     714:	9263      	ld.w      	r3, (r2, 0xc)
     716:	3b80      	bclri      	r3, r3, 0
     718:	b263      	st.w      	r3, (r2, 0xc)
     71a:	07f0      	br      	0x6fa	// 6fa <CMP_Close+0xe>
	else if(CMPx_selecte==CMP3_NUM)
     71c:	3843      	cmpnei      	r0, 3
     71e:	0807      	bt      	0x72c	// 72c <CMP_Close+0x40>
		CMP->CR3&=0xfffffffe;									//比较器3关闭
     720:	1069      	lrw      	r3, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     722:	9340      	ld.w      	r2, (r3, 0)
     724:	9264      	ld.w      	r3, (r2, 0x10)
     726:	3b80      	bclri      	r3, r3, 0
     728:	b264      	st.w      	r3, (r2, 0x10)
     72a:	07e8      	br      	0x6fa	// 6fa <CMP_Close+0xe>
	else if(CMPx_selecte==CMP4_NUM)
     72c:	3844      	cmpnei      	r0, 4
     72e:	0be6      	bt      	0x6fa	// 6fa <CMP_Close+0xe>
		CMP->CR4&=0xfffffffe;									//比较器4关闭
     730:	1065      	lrw      	r3, 0x20000004	// 744 <CMPX_FLTCR_Config+0x8>
     732:	9340      	ld.w      	r2, (r3, 0)
     734:	9265      	ld.w      	r3, (r2, 0x14)
     736:	3b80      	bclri      	r3, r3, 0
     738:	b265      	st.w      	r3, (r2, 0x14)
}
     73a:	07e0      	br      	0x6fa	// 6fa <CMP_Close+0xe>

0000073c <CMPX_FLTCR_Config>:
//CMPX_DIVM:0~255
//ReturnValue:NONE
/*************************************************************/ 
//FLT_CK = PCLK/(CMPX_DIVM+1)/2^CMPX_DIVN
void CMPX_FLTCR_Config(CMPx_selecte_TypeDef CMPx_NUM , CMPX_CLK_Selecte_TypeDef CMPX_CLK_Selecte_x , U8_T CMPX_DIVN , U8_T CMPX_DIVM)
{
     73c:	14c1      	push      	r4
	if(CMPx_NUM==CMP0_NUM)
     73e:	3840      	cmpnei      	r0, 0
     740:	0814      	bt      	0x768	// 768 <CMPX_FLTCR_Config+0x2c>
     742:	0405      	br      	0x74c	// 74c <CMPX_FLTCR_Config+0x10>
     744:	20000004 	.long	0x20000004
     748:	0000879e 	.long	0x0000879e
	{
		CMP->FLTCR0&=0xffff0000;
     74c:	121b      	lrw      	r0, 0x20000004	// 8b8 <CMP_TRGCR_Config+0x66>
		CMP->FLTCR0|=CMPX_CLK_Selecte_x|(CMPX_DIVN<<3)|(CMPX_DIVM<<8);
     74e:	4368      	lsli      	r3, r3, 8
		CMP->FLTCR0&=0xffff0000;
     750:	9080      	ld.w      	r4, (r0, 0)
     752:	9406      	ld.w      	r0, (r4, 0x18)
     754:	4810      	lsri      	r0, r0, 16
     756:	4010      	lsli      	r0, r0, 16
     758:	b406      	st.w      	r0, (r4, 0x18)
		CMP->FLTCR0|=CMPX_CLK_Selecte_x|(CMPX_DIVN<<3)|(CMPX_DIVM<<8);
     75a:	9406      	ld.w      	r0, (r4, 0x18)
     75c:	6c40      	or      	r1, r0
     75e:	6c4c      	or      	r1, r3
     760:	4243      	lsli      	r2, r2, 3
     762:	6c84      	or      	r2, r1
     764:	b446      	st.w      	r2, (r4, 0x18)
	else if(CMPx_NUM==CMP4_NUM)
	{
		CMP->FLTCR4&=0xffff0000;
		CMP->FLTCR4|=CMPX_CLK_Selecte_x|(CMPX_DIVN<<3)|(CMPX_DIVM<<8);
	}
}
     766:	1481      	pop      	r4
	else if(CMPx_NUM==CMP1_NUM)
     768:	3841      	cmpnei      	r0, 1
     76a:	080f      	bt      	0x788	// 788 <CMPX_FLTCR_Config+0x4c>
		CMP->FLTCR1&=0xffff0000;
     76c:	1213      	lrw      	r0, 0x20000004	// 8b8 <CMP_TRGCR_Config+0x66>
		CMP->FLTCR1|=CMPX_CLK_Selecte_x|(CMPX_DIVN<<3)|(CMPX_DIVM<<8);
     76e:	4368      	lsli      	r3, r3, 8
		CMP->FLTCR1&=0xffff0000;
     770:	9080      	ld.w      	r4, (r0, 0)
     772:	9407      	ld.w      	r0, (r4, 0x1c)
     774:	4810      	lsri      	r0, r0, 16
     776:	4010      	lsli      	r0, r0, 16
     778:	b407      	st.w      	r0, (r4, 0x1c)
		CMP->FLTCR1|=CMPX_CLK_Selecte_x|(CMPX_DIVN<<3)|(CMPX_DIVM<<8);
     77a:	9407      	ld.w      	r0, (r4, 0x1c)
     77c:	6c40      	or      	r1, r0
     77e:	6c4c      	or      	r1, r3
     780:	4243      	lsli      	r2, r2, 3
     782:	6c84      	or      	r2, r1
     784:	b447      	st.w      	r2, (r4, 0x1c)
     786:	07f0      	br      	0x766	// 766 <CMPX_FLTCR_Config+0x2a>
	else if(CMPx_NUM==CMP2_NUM)
     788:	3842      	cmpnei      	r0, 2
     78a:	080f      	bt      	0x7a8	// 7a8 <CMPX_FLTCR_Config+0x6c>
		CMP->FLTCR2&=0xffff0000;
     78c:	120b      	lrw      	r0, 0x20000004	// 8b8 <CMP_TRGCR_Config+0x66>
		CMP->FLTCR2|=CMPX_CLK_Selecte_x|(CMPX_DIVN<<3)|(CMPX_DIVM<<8);
     78e:	4368      	lsli      	r3, r3, 8
		CMP->FLTCR2&=0xffff0000;
     790:	9080      	ld.w      	r4, (r0, 0)
     792:	9408      	ld.w      	r0, (r4, 0x20)
     794:	4810      	lsri      	r0, r0, 16
     796:	4010      	lsli      	r0, r0, 16
     798:	b408      	st.w      	r0, (r4, 0x20)
		CMP->FLTCR2|=CMPX_CLK_Selecte_x|(CMPX_DIVN<<3)|(CMPX_DIVM<<8);
     79a:	9408      	ld.w      	r0, (r4, 0x20)
     79c:	6c40      	or      	r1, r0
     79e:	6c4c      	or      	r1, r3
     7a0:	4243      	lsli      	r2, r2, 3
     7a2:	6c84      	or      	r2, r1
     7a4:	b448      	st.w      	r2, (r4, 0x20)
     7a6:	07e0      	br      	0x766	// 766 <CMPX_FLTCR_Config+0x2a>
	else if(CMPx_NUM==CMP3_NUM)
     7a8:	3843      	cmpnei      	r0, 3
     7aa:	080f      	bt      	0x7c8	// 7c8 <CMPX_FLTCR_Config+0x8c>
		CMP->FLTCR3&=0xffff0000;
     7ac:	1203      	lrw      	r0, 0x20000004	// 8b8 <CMP_TRGCR_Config+0x66>
		CMP->FLTCR3|=CMPX_CLK_Selecte_x|(CMPX_DIVN<<3)|(CMPX_DIVM<<8);
     7ae:	4368      	lsli      	r3, r3, 8
		CMP->FLTCR3&=0xffff0000;
     7b0:	9080      	ld.w      	r4, (r0, 0)
     7b2:	9409      	ld.w      	r0, (r4, 0x24)
     7b4:	4810      	lsri      	r0, r0, 16
     7b6:	4010      	lsli      	r0, r0, 16
     7b8:	b409      	st.w      	r0, (r4, 0x24)
		CMP->FLTCR3|=CMPX_CLK_Selecte_x|(CMPX_DIVN<<3)|(CMPX_DIVM<<8);
     7ba:	9409      	ld.w      	r0, (r4, 0x24)
     7bc:	6c40      	or      	r1, r0
     7be:	6c4c      	or      	r1, r3
     7c0:	4243      	lsli      	r2, r2, 3
     7c2:	6c84      	or      	r2, r1
     7c4:	b449      	st.w      	r2, (r4, 0x24)
     7c6:	07d0      	br      	0x766	// 766 <CMPX_FLTCR_Config+0x2a>
	else if(CMPx_NUM==CMP4_NUM)
     7c8:	3844      	cmpnei      	r0, 4
     7ca:	0bce      	bt      	0x766	// 766 <CMPX_FLTCR_Config+0x2a>
		CMP->FLTCR4&=0xffff0000;
     7cc:	111b      	lrw      	r0, 0x20000004	// 8b8 <CMP_TRGCR_Config+0x66>
		CMP->FLTCR4|=CMPX_CLK_Selecte_x|(CMPX_DIVN<<3)|(CMPX_DIVM<<8);
     7ce:	4368      	lsli      	r3, r3, 8
		CMP->FLTCR4&=0xffff0000;
     7d0:	9000      	ld.w      	r0, (r0, 0)
     7d2:	908a      	ld.w      	r4, (r0, 0x28)
     7d4:	4c90      	lsri      	r4, r4, 16
     7d6:	4490      	lsli      	r4, r4, 16
     7d8:	b08a      	st.w      	r4, (r0, 0x28)
		CMP->FLTCR4|=CMPX_CLK_Selecte_x|(CMPX_DIVN<<3)|(CMPX_DIVM<<8);
     7da:	908a      	ld.w      	r4, (r0, 0x28)
     7dc:	6c50      	or      	r1, r4
     7de:	6cc4      	or      	r3, r1
     7e0:	4243      	lsli      	r2, r2, 3
     7e2:	6cc8      	or      	r3, r2
     7e4:	b06a      	st.w      	r3, (r0, 0x28)
}
     7e6:	07c0      	br      	0x766	// 766 <CMPX_FLTCR_Config+0x2a>

000007e8 <CMP_WCNT_Config>:
/*************************************************************/  
//捕捉宽度时间:(CMP_WCNT+1)*PCLK/CLKDIV
//延时宽度时间:(CMP_DCNT+1)*PCLK/CLKDIV,如果CMP_DCNT=0，延时时间=0
void CMP_WCNT_Config(CMPx_selecte_TypeDef CMPx_NUM , CMPX_First_output_startue_TypeDef HLS_X , CMPX_Trgsel_selecte_TypeDef CMPX_Trgsel_X , 
				     CMPX_MSKMOD_Control_TypeDef CMPX_MSKMOD_X , CMPX_CLKDIV_TypeDef CMPX_CLKDIV_X , U8_T CMP_DCNT , U16_T CMP_WCNT)
{
     7e8:	14c4      	push      	r4-r7
	if(CMPx_NUM==CMP2_NUM)
     7ea:	3842      	cmpnei      	r0, 2
{
     7ec:	98c4      	ld.w      	r6, (sp, 0x10)
     7ee:	d8ae0014 	ld.b      	r5, (sp, 0x14)
     7f2:	d88e100c 	ld.h      	r4, (sp, 0x18)
	if(CMPx_NUM==CMP2_NUM)
     7f6:	080f      	bt      	0x814	// 814 <CMP_WCNT_Config+0x2c>
	{
		CMP->WCNT0&=0x0;
     7f8:	1110      	lrw      	r0, 0x20000004	// 8b8 <CMP_TRGCR_Config+0x66>
     7fa:	9000      	ld.w      	r0, (r0, 0)
     7fc:	90eb      	ld.w      	r7, (r0, 0x2c)
     7fe:	3700      	movi      	r7, 0
     800:	b0eb      	st.w      	r7, (r0, 0x2c)
		CMP->WCNT0|=HLS_X|CMPX_Trgsel_X|CMPX_MSKMOD_X|CMPX_CLKDIV_X|CMP_DCNT|CMP_WCNT;
     802:	90eb      	ld.w      	r7, (r0, 0x2c)
     804:	6d1c      	or      	r4, r7
     806:	6d18      	or      	r4, r6
     808:	6d14      	or      	r4, r5
     80a:	6cd0      	or      	r3, r4
     80c:	6c8c      	or      	r2, r3
     80e:	6c48      	or      	r1, r2
     810:	b02b      	st.w      	r1, (r0, 0x2c)
	else if(CMPx_NUM==CMP4_NUM)
	{
		CMP->WCNT2=0x0;
		CMP->WCNT2|=HLS_X|CMPX_Trgsel_X|CMPX_MSKMOD_X|CMPX_CLKDIV_X|CMP_DCNT|CMP_WCNT;
	}
}
     812:	1484      	pop      	r4-r7
	else if(CMPx_NUM==CMP3_NUM)
     814:	3843      	cmpnei      	r0, 3
     816:	080f      	bt      	0x834	// 834 <CMP_WCNT_Config+0x4c>
		CMP->WCNT1&=0x0;
     818:	1108      	lrw      	r0, 0x20000004	// 8b8 <CMP_TRGCR_Config+0x66>
     81a:	9000      	ld.w      	r0, (r0, 0)
     81c:	90ec      	ld.w      	r7, (r0, 0x30)
     81e:	3700      	movi      	r7, 0
     820:	b0ec      	st.w      	r7, (r0, 0x30)
		CMP->WCNT1|=HLS_X|CMPX_Trgsel_X|CMPX_MSKMOD_X|CMPX_CLKDIV_X|CMP_DCNT|CMP_WCNT;
     822:	90ec      	ld.w      	r7, (r0, 0x30)
     824:	6d1c      	or      	r4, r7
     826:	6d18      	or      	r4, r6
     828:	6d14      	or      	r4, r5
     82a:	6cd0      	or      	r3, r4
     82c:	6c8c      	or      	r2, r3
     82e:	6c48      	or      	r1, r2
     830:	b02c      	st.w      	r1, (r0, 0x30)
     832:	07f0      	br      	0x812	// 812 <CMP_WCNT_Config+0x2a>
	else if(CMPx_NUM==CMP4_NUM)
     834:	3844      	cmpnei      	r0, 4
     836:	0bee      	bt      	0x812	// 812 <CMP_WCNT_Config+0x2a>
		CMP->WCNT2=0x0;
     838:	1100      	lrw      	r0, 0x20000004	// 8b8 <CMP_TRGCR_Config+0x66>
     83a:	3700      	movi      	r7, 0
     83c:	9000      	ld.w      	r0, (r0, 0)
     83e:	b0ed      	st.w      	r7, (r0, 0x34)
		CMP->WCNT2|=HLS_X|CMPX_Trgsel_X|CMPX_MSKMOD_X|CMPX_CLKDIV_X|CMP_DCNT|CMP_WCNT;
     840:	90ed      	ld.w      	r7, (r0, 0x34)
     842:	6d1c      	or      	r4, r7
     844:	6d18      	or      	r4, r6
     846:	6d14      	or      	r4, r5
     848:	6cd0      	or      	r3, r4
     84a:	6c8c      	or      	r2, r3
     84c:	6c48      	or      	r1, r2
     84e:	b02d      	st.w      	r1, (r0, 0x34)
}
     850:	07e1      	br      	0x812	// 812 <CMP_WCNT_Config+0x2a>

00000852 <CMP_TRGCR_Config>:
//CMP_TC_CIN_X:CMP_TC_CIN_Enable,CMP_TC_CIN_Disable
//CMP_AD_TRG_X:CMP_AD_TRG_Enable,CMP_AD_TRG2_Disable
//ReturnValue:NONE
/*************************************************************/  
void CMP_TRGCR_Config(CMPx_selecte_TypeDef CMPx_NUM , CMP_TC_TRG_TypeDef CMP_TC_TRG_X , CMP_TC_CIN_CMD_TypeDef CMP_TC_CIN_X , CMP_AD_TRG_CMD_TypeDef CMP_AD_TRG_X)
{
     852:	14c3      	push      	r4-r6
	CMP->TRGCR&=0xfffffff8;
     854:	1099      	lrw      	r4, 0x20000004	// 8b8 <CMP_TRGCR_Config+0x66>
     856:	3607      	movi      	r6, 7
     858:	9480      	ld.w      	r4, (r4, 0)
     85a:	94b3      	ld.w      	r5, (r4, 0x4c)
     85c:	6959      	andn      	r5, r6
     85e:	b4b3      	st.w      	r5, (r4, 0x4c)
	CMP->TRGCR|=CMP_TC_TRG_X;										//TC1启动触发
     860:	94b3      	ld.w      	r5, (r4, 0x4c)
     862:	6c54      	or      	r1, r5
	if(CMPx_NUM==CMP0_NUM)
     864:	3840      	cmpnei      	r0, 0
	CMP->TRGCR|=CMP_TC_TRG_X;										//TC1启动触发
     866:	b433      	st.w      	r1, (r4, 0x4c)
	if(CMPx_NUM==CMP0_NUM)
     868:	080e      	bt      	0x884	// 884 <CMP_TRGCR_Config+0x32>
	{
		CMP->TRGCR&=0xfffffef7;
     86a:	9433      	ld.w      	r1, (r4, 0x4c)
     86c:	3983      	bclri      	r1, r1, 3
     86e:	3988      	bclri      	r1, r1, 8
     870:	b433      	st.w      	r1, (r4, 0x4c)
		CMP->TRGCR|=CMP_TC_CIN_X<<3;								//CMP0输出作为TC1的Capture/CLK输入
     872:	9433      	ld.w      	r1, (r4, 0x4c)
     874:	4243      	lsli      	r2, r2, 3
     876:	6c84      	or      	r2, r1
     878:	b453      	st.w      	r2, (r4, 0x4c)
		CMP->TRGCR|=CMP_AD_TRG_X<<8;								//CMP0启动ADC触发
     87a:	9453      	ld.w      	r2, (r4, 0x4c)
     87c:	4368      	lsli      	r3, r3, 8
	}
	else if(CMPx_NUM==CMP4_NUM)
	{
		CMP->TRGCR&=0xffffef7f;
		CMP->TRGCR|=CMP_TC_CIN_X<<7;								//CMP4输出作为TC1的Capture/CLK输入
		CMP->TRGCR|=CMP_AD_TRG_X<<12;								//CMP4启动ADC触发
     87e:	6cc8      	or      	r3, r2
     880:	b473      	st.w      	r3, (r4, 0x4c)
	}
}
     882:	1483      	pop      	r4-r6
	else if(CMPx_NUM==CMP1_NUM)
     884:	3841      	cmpnei      	r0, 1
     886:	080c      	bt      	0x89e	// 89e <CMP_TRGCR_Config+0x4c>
		CMP->TRGCR&=0xfffffdef;
     888:	9433      	ld.w      	r1, (r4, 0x4c)
     88a:	3984      	bclri      	r1, r1, 4
     88c:	3989      	bclri      	r1, r1, 9
     88e:	b433      	st.w      	r1, (r4, 0x4c)
		CMP->TRGCR|=CMP_TC_CIN_X<<4;								//CMP1输出作为TC1的Capture/CLK输入
     890:	9433      	ld.w      	r1, (r4, 0x4c)
     892:	4244      	lsli      	r2, r2, 4
     894:	6c84      	or      	r2, r1
     896:	b453      	st.w      	r2, (r4, 0x4c)
		CMP->TRGCR|=CMP_AD_TRG_X<<9;								//CMP1启动ADC触发
     898:	9453      	ld.w      	r2, (r4, 0x4c)
     89a:	4369      	lsli      	r3, r3, 9
     89c:	07f1      	br      	0x87e	// 87e <CMP_TRGCR_Config+0x2c>
	else if(CMPx_NUM==CMP2_NUM)
     89e:	3842      	cmpnei      	r0, 2
     8a0:	080e      	bt      	0x8bc	// 8bc <CMP_TRGCR_Config+0x6a>
		CMP->TRGCR&=0xfffffbdf;
     8a2:	9433      	ld.w      	r1, (r4, 0x4c)
     8a4:	3985      	bclri      	r1, r1, 5
     8a6:	398a      	bclri      	r1, r1, 10
     8a8:	b433      	st.w      	r1, (r4, 0x4c)
		CMP->TRGCR|=CMP_TC_CIN_X<<5;								//CMP2输出作为TC1的Capture/CLK输入
     8aa:	9433      	ld.w      	r1, (r4, 0x4c)
     8ac:	4245      	lsli      	r2, r2, 5
     8ae:	6c84      	or      	r2, r1
     8b0:	b453      	st.w      	r2, (r4, 0x4c)
		CMP->TRGCR|=CMP_AD_TRG_X<<10;								//CMP2启动ADC触发
     8b2:	9453      	ld.w      	r2, (r4, 0x4c)
     8b4:	436a      	lsli      	r3, r3, 10
     8b6:	07e4      	br      	0x87e	// 87e <CMP_TRGCR_Config+0x2c>
     8b8:	20000004 	.long	0x20000004
	else if(CMPx_NUM==CMP3_NUM)
     8bc:	3843      	cmpnei      	r0, 3
     8be:	080c      	bt      	0x8d6	// 8d6 <CMP_TRGCR_Config+0x84>
		CMP->TRGCR&=0xfffff7bf;
     8c0:	9433      	ld.w      	r1, (r4, 0x4c)
     8c2:	3986      	bclri      	r1, r1, 6
     8c4:	398b      	bclri      	r1, r1, 11
     8c6:	b433      	st.w      	r1, (r4, 0x4c)
		CMP->TRGCR|=CMP_TC_CIN_X<<6;								//CMP3输出作为TC1的Capture/CLK输入
     8c8:	9433      	ld.w      	r1, (r4, 0x4c)
     8ca:	4246      	lsli      	r2, r2, 6
     8cc:	6c84      	or      	r2, r1
     8ce:	b453      	st.w      	r2, (r4, 0x4c)
		CMP->TRGCR|=CMP_AD_TRG_X<<11;								//CMP3启动ADC触发
     8d0:	9453      	ld.w      	r2, (r4, 0x4c)
     8d2:	436b      	lsli      	r3, r3, 11
     8d4:	07d5      	br      	0x87e	// 87e <CMP_TRGCR_Config+0x2c>
	else if(CMPx_NUM==CMP4_NUM)
     8d6:	3844      	cmpnei      	r0, 4
     8d8:	0bd5      	bt      	0x882	// 882 <CMP_TRGCR_Config+0x30>
		CMP->TRGCR&=0xffffef7f;
     8da:	9433      	ld.w      	r1, (r4, 0x4c)
     8dc:	3987      	bclri      	r1, r1, 7
     8de:	398c      	bclri      	r1, r1, 12
     8e0:	b433      	st.w      	r1, (r4, 0x4c)
		CMP->TRGCR|=CMP_TC_CIN_X<<7;								//CMP4输出作为TC1的Capture/CLK输入
     8e2:	9433      	ld.w      	r1, (r4, 0x4c)
     8e4:	4247      	lsli      	r2, r2, 7
     8e6:	6c84      	or      	r2, r1
     8e8:	b453      	st.w      	r2, (r4, 0x4c)
		CMP->TRGCR|=CMP_AD_TRG_X<<12;								//CMP4启动ADC触发
     8ea:	9453      	ld.w      	r2, (r4, 0x4c)
     8ec:	436c      	lsli      	r3, r3, 12
     8ee:	07c8      	br      	0x87e	// 87e <CMP_TRGCR_Config+0x2c>

000008f0 <CMP_ConfigInterrupt_CMD>:
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void CMP_ConfigInterrupt_CMD(CMP_INT_TypeDef CMP_INT_X , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
     8f0:	3940      	cmpnei      	r1, 0
     8f2:	1167      	lrw      	r3, 0x20000004	// 98c <CMP1_Wakeup_Disable+0x12>
     8f4:	0c06      	bf      	0x900	// 900 <CMP_ConfigInterrupt_CMD+0x10>
	{
		CMP->IMCR  |= CMP_INT_X;						//SET
     8f6:	9340      	ld.w      	r2, (r3, 0)
     8f8:	9274      	ld.w      	r3, (r2, 0x50)
     8fa:	6c0c      	or      	r0, r3
     8fc:	b214      	st.w      	r0, (r2, 0x50)
	}
	else
	{
		CMP->IMCR  &= ~CMP_INT_X;						//CLR
	}
}
     8fe:	783c      	rts
		CMP->IMCR  &= ~CMP_INT_X;						//CLR
     900:	9360      	ld.w      	r3, (r3, 0)
     902:	9354      	ld.w      	r2, (r3, 0x50)
     904:	6c02      	nor      	r0, r0
     906:	6808      	and      	r0, r2
     908:	b314      	st.w      	r0, (r3, 0x50)
}
     90a:	07fa      	br      	0x8fe	// 8fe <CMP_ConfigInterrupt_CMD+0xe>

0000090c <CMP0_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CMP0_Int_Enable(void)
{
    INTC_ISER_WRITE(CMP0_INT);    
     90c:	1161      	lrw      	r3, 0x20000064	// 990 <CMP1_Wakeup_Disable+0x16>
     90e:	3280      	movi      	r2, 128
     910:	9360      	ld.w      	r3, (r3, 0)
     912:	23ff      	addi      	r3, 256
     914:	4255      	lsli      	r2, r2, 21
     916:	b340      	st.w      	r2, (r3, 0)
}
     918:	783c      	rts

0000091a <CMP0_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CMP0_Int_Disable(void)
{
    INTC_ICER_WRITE(CMP0_INT);    
     91a:	107e      	lrw      	r3, 0x20000064	// 990 <CMP1_Wakeup_Disable+0x16>
     91c:	32c0      	movi      	r2, 192
     91e:	9360      	ld.w      	r3, (r3, 0)
     920:	4241      	lsli      	r2, r2, 1
     922:	60c8      	addu      	r3, r2
     924:	3280      	movi      	r2, 128
     926:	4255      	lsli      	r2, r2, 21
     928:	b340      	st.w      	r2, (r3, 0)
}
     92a:	783c      	rts

0000092c <CMP0_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CMP0_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(CMP0_INT);    
     92c:	1079      	lrw      	r3, 0x20000064	// 990 <CMP1_Wakeup_Disable+0x16>
     92e:	3280      	movi      	r2, 128
     930:	9360      	ld.w      	r3, (r3, 0)
     932:	23ff      	addi      	r3, 256
     934:	4255      	lsli      	r2, r2, 21
     936:	b350      	st.w      	r2, (r3, 0x40)
}
     938:	783c      	rts

0000093a <CMP0_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CMP0_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(CMP0_INT);    
     93a:	1076      	lrw      	r3, 0x20000064	// 990 <CMP1_Wakeup_Disable+0x16>
     93c:	32e0      	movi      	r2, 224
     93e:	9360      	ld.w      	r3, (r3, 0)
     940:	4241      	lsli      	r2, r2, 1
     942:	60c8      	addu      	r3, r2
     944:	3280      	movi      	r2, 128
     946:	4255      	lsli      	r2, r2, 21
     948:	b340      	st.w      	r2, (r3, 0)
}
     94a:	783c      	rts

0000094c <CMP1_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CMP1_Int_Enable(void)
{
    INTC_ISER_WRITE(CMP1_INT);    
     94c:	1071      	lrw      	r3, 0x20000064	// 990 <CMP1_Wakeup_Disable+0x16>
     94e:	3280      	movi      	r2, 128
     950:	9360      	ld.w      	r3, (r3, 0)
     952:	23ff      	addi      	r3, 256
     954:	4256      	lsli      	r2, r2, 22
     956:	b340      	st.w      	r2, (r3, 0)
}
     958:	783c      	rts

0000095a <CMP1_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CMP1_Int_Disable(void)
{
    INTC_ICER_WRITE(CMP1_INT);    
     95a:	106e      	lrw      	r3, 0x20000064	// 990 <CMP1_Wakeup_Disable+0x16>
     95c:	32c0      	movi      	r2, 192
     95e:	9360      	ld.w      	r3, (r3, 0)
     960:	4241      	lsli      	r2, r2, 1
     962:	60c8      	addu      	r3, r2
     964:	3280      	movi      	r2, 128
     966:	4256      	lsli      	r2, r2, 22
     968:	b340      	st.w      	r2, (r3, 0)
}
     96a:	783c      	rts

0000096c <CMP1_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CMP1_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(CMP1_INT);    
     96c:	1069      	lrw      	r3, 0x20000064	// 990 <CMP1_Wakeup_Disable+0x16>
     96e:	3280      	movi      	r2, 128
     970:	9360      	ld.w      	r3, (r3, 0)
     972:	23ff      	addi      	r3, 256
     974:	4256      	lsli      	r2, r2, 22
     976:	b350      	st.w      	r2, (r3, 0x40)
}
     978:	783c      	rts

0000097a <CMP1_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CMP1_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(CMP1_INT);    
     97a:	1066      	lrw      	r3, 0x20000064	// 990 <CMP1_Wakeup_Disable+0x16>
     97c:	32e0      	movi      	r2, 224
     97e:	9360      	ld.w      	r3, (r3, 0)
     980:	4241      	lsli      	r2, r2, 1
     982:	60c8      	addu      	r3, r2
     984:	3280      	movi      	r2, 128
     986:	4256      	lsli      	r2, r2, 22
     988:	b340      	st.w      	r2, (r3, 0)
}
     98a:	783c      	rts
     98c:	20000004 	.long	0x20000004
     990:	20000064 	.long	0x20000064

00000994 <EPWM_RESET_VALUE>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void EPWM_RESET_VALUE(void)
{
		EPWM->CR=PWM_CR_RST;     				/**< CR  reset value  	*/
     994:	107e      	lrw      	r3, 0x2000001c	// a0c <EPWM_RESET_VALUE+0x78>
     996:	3280      	movi      	r2, 128
     998:	9360      	ld.w      	r3, (r3, 0)
     99a:	4250      	lsli      	r2, r2, 16
     99c:	b340      	st.w      	r2, (r3, 0)
		EPWM->LKCR=PWM_LKCR_RST;     			/**< LKCR  reset value 	*/
     99e:	3200      	movi      	r2, 0
     9a0:	b341      	st.w      	r2, (r3, 0x4)
		EPWM->LKTRG=PWM_LKTRG_RST;     			/**< LKTRG  reset value */
     9a2:	b342      	st.w      	r2, (r3, 0x8)
		EPWM->CNTR0=PWM_CNTR0_RST;     			/**< CNTR0  reset value */
     9a4:	b343      	st.w      	r2, (r3, 0xc)
		EPWM->CNTBR0=PWM_CNTBR0_RST;     		/**< CNTBR0  reset value */
     9a6:	b344      	st.w      	r2, (r3, 0x10)
		EPWM->PCNTR0=PWM_PCNTR0_RST;     		/**< PCNTR0  reset value */
     9a8:	b345      	st.w      	r2, (r3, 0x14)
		EPWM->SLPCNTR0=PWM_SLPCNTR0_RST;     	/**< SLPCNTR0  reset value */
     9aa:	b346      	st.w      	r2, (r3, 0x18)
		EPWM->CNTR1=PWM_CNTR1_RST;     			/**< CNTR1  reset value */
     9ac:	b347      	st.w      	r2, (r3, 0x1c)
		EPWM->CNTBR1=PWM_CNTBR1_RST;     		/**< CNTBR1  reset value */
     9ae:	b348      	st.w      	r2, (r3, 0x20)
		EPWM->PCNTR1=PWM_PCNTR1_RST;     		/**< PCNTR1  reset value */
     9b0:	b349      	st.w      	r2, (r3, 0x24)
		EPWM->SLPCNTR1=PWM_SLPCNTR1_RST;     	/**< SLPCNTR1  reset value */
     9b2:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->CNTR2=PWM_CNTR2_RST;     			/**< CNTR2  reset value */
     9b4:	b34b      	st.w      	r2, (r3, 0x2c)
		EPWM->CNTBR2=PWM_CNTBR2_RST;     		/**< CNTBR2  reset value */
     9b6:	b34c      	st.w      	r2, (r3, 0x30)
		EPWM->PCNTR2=PWM_PCNTR2_RST;     		/**< PCNTR2  reset value */
     9b8:	b34d      	st.w      	r2, (r3, 0x34)
		EPWM->SLPCNTR2=PWM_SLPCNTR2_RST;     	/**< SLPCNTR2  reset value */
     9ba:	b34e      	st.w      	r2, (r3, 0x38)
		EPWM->CMPAR0=PWM_CMPAR0_RST;     		/**< CMPAR0  reset value */
     9bc:	b34f      	st.w      	r2, (r3, 0x3c)
		EPWM->PCMPAR0=PWM_PCMPAR0_RST;     		/**< PCMPAR0  reset value */
     9be:	b350      	st.w      	r2, (r3, 0x40)
		EPWM->SLPCMPAR0=PWM_SLPCMPAR0_RST;     	/**< SLPCMPAR0  reset value */
     9c0:	b351      	st.w      	r2, (r3, 0x44)
		EPWM->CMPBR0=PWM_CMPBR0_RST;     		/**< CMPBR0  reset value */
     9c2:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->PCMPBR0=PWM_PCMPBR0_RST;     		/**< PCMPBR0  reset value */
     9c4:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->SLPCMPBR0=PWM_SLPCMPBR0_RST;     	/**< SLPCMPBR0  reset value */
     9c6:	b354      	st.w      	r2, (r3, 0x50)
		EPWM->CMPAR1=PWM_CMPAR1_RST;     		/**< CMPAR1  reset value */
     9c8:	b355      	st.w      	r2, (r3, 0x54)
		EPWM->PCMPAR1=PWM_PCMPAR1_RST;     		/**< PCMPAR1  reset value */
     9ca:	b356      	st.w      	r2, (r3, 0x58)
		EPWM->SLPCMPAR1=PWM_SLPCMPAR1_RST;     	/**< SLPCMPAR1  reset value */
     9cc:	b357      	st.w      	r2, (r3, 0x5c)
		EPWM->CMPBR1=PWM_CMPBR1_RST;     		/**< CMPBR1  reset value */
     9ce:	b358      	st.w      	r2, (r3, 0x60)
		EPWM->PCMPBR1=PWM_PCMPBR1_RST;     		/**< PCMPBR1 reset value */
     9d0:	b359      	st.w      	r2, (r3, 0x64)
		EPWM->SLPCMPBR1=PWM_SLPCMPBR1_RST;     	/**< SLPCMPBR1  reset value */
     9d2:	b35a      	st.w      	r2, (r3, 0x68)
		EPWM->CMPAR2=PWM_CMPAR2_RST;     		/**< CMPAR2  reset value */
     9d4:	b35b      	st.w      	r2, (r3, 0x6c)
		EPWM->PCMPAR2=PWM_PCMPAR2_RST;    		/**< PCMPAR2  reset value */
     9d6:	b35c      	st.w      	r2, (r3, 0x70)
		EPWM->SLPCMPAR2=PWM_SLPCMPAR2_RST;     	/**< SLPCMPAR2  reset value */
     9d8:	b35d      	st.w      	r2, (r3, 0x74)
		EPWM->CMPBR2=PWM_CMPBR2_RST;     		/**< CMPBR2  reset value */
     9da:	b35e      	st.w      	r2, (r3, 0x78)
		EPWM->PCMPBR2=PWM_PCMPBR2_RST;     		/**< PCMPBR2 reset value */
     9dc:	b35f      	st.w      	r2, (r3, 0x7c)
		EPWM->SLPCMPBR2=PWM_SLPCMPBR2_RST;     	/**< SLPCMPBR2  reset value */
     9de:	237f      	addi      	r3, 128
     9e0:	b340      	st.w      	r2, (r3, 0)
		EPWM->WGCR0=PWM_WGCR0_RST;     			/**< WGCR0  reset value */
     9e2:	b341      	st.w      	r2, (r3, 0x4)
		EPWM->WGCR1=PWM_WGCR1_RST;     			/**< WGCR1  reset value */
     9e4:	b342      	st.w      	r2, (r3, 0x8)
		EPWM->WGCR2=PWM_WGCR2_RST;     			/**< WGCR2  reset value */
     9e6:	b343      	st.w      	r2, (r3, 0xc)
		EPWM->OUTCR0=PWM_OUTCR0_RST;     		/**< OUTCR0  reset value */
     9e8:	b344      	st.w      	r2, (r3, 0x10)
		EPWM->OUTCR1=PWM_OUTCR1_RST;     		/**< OUTCR1  reset value */
     9ea:	b345      	st.w      	r2, (r3, 0x14)
		EPWM->OUTCR2=PWM_OUTCR2_RST;     		/**< OUTCR2  reset value */
     9ec:	b346      	st.w      	r2, (r3, 0x18)
		EPWM->CFCR0=PWM_CFCR0_RST;     			/**< CFCR0  reset value */
     9ee:	b347      	st.w      	r2, (r3, 0x1c)
		EPWM->CFCR1=PWM_CFCR1_RST;     			/**< CFCR1  reset value */
     9f0:	b348      	st.w      	r2, (r3, 0x20)
		EPWM->CFCR2=PWM_CFCR2_RST;     			/**< CFCR2  reset value */
     9f2:	b349      	st.w      	r2, (r3, 0x24)
		EPWM->EMR=PWM_EMR_RST;     				/**< EMR  reset value */
     9f4:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->SLCON=PWM_SLCON_RST;     			/**< SLCON  reset value */
     9f6:	b34b      	st.w      	r2, (r3, 0x2c)
		EPWM->SLSTEP0=PWM_SLSTEP0_RST;     		/**< SLSTEP0  reset value */
     9f8:	b34c      	st.w      	r2, (r3, 0x30)
		EPWM->SLSTEP1=PWM_SLSTEP1_RST;     		/**< SLSTEP1 reset value */
     9fa:	b34d      	st.w      	r2, (r3, 0x34)
		EPWM->IER=PWM_IER_RST;     				/**< IER reset value */
     9fc:	b34e      	st.w      	r2, (r3, 0x38)
		EPWM->ICR=PWM_ICR_RST;     				/**< ICR reset value */
     9fe:	b34f      	st.w      	r2, (r3, 0x3c)
		EPWM->RISR=PWM_RISR_RST;     			/**< RISR reset value */
     a00:	b350      	st.w      	r2, (r3, 0x40)
		EPWM->MISR=PWM_MISR_RST;     			/**< MISR reset value */
     a02:	b351      	st.w      	r2, (r3, 0x44)
		EPWM->EXTRG0=PWM_EXTRG0_RST;     		/**< EXTRG0 reset value */
     a04:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG1=PWM_EXTRG1_RST;     		/**< EXTRG1 reset value */
     a06:	b353      	st.w      	r2, (r3, 0x4c)
}
     a08:	783c      	rts
     a0a:	0000      	bkpt
     a0c:	2000001c 	.long	0x2000001c

00000a10 <EPWM_IO_Init>:
//PWM_EP4(0->PA1.5)
//ReturnValue:NONE
/*************************************************************/
void EPWM_IO_Init(EPWM_IO_MODE_TypeDef  EPWM_IO_MODE_X , U8_T EPWM_IO_G )
{
	if(EPWM_IO_MODE_X==PWM_X0)
     a10:	3840      	cmpnei      	r0, 0
     a12:	083a      	bt      	0xa86	// a86 <EPWM_IO_Init+0x76>
	{
		if(EPWM_IO_G==0)
     a14:	3940      	cmpnei      	r1, 0
     a16:	0809      	bt      	0xa28	// a28 <EPWM_IO_Init+0x18>
		{
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFF0F)|0x00000040;										//EPWM0_X(PA0.09->AF1)
     a18:	1367      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     a1a:	31f0      	movi      	r1, 240
     a1c:	9340      	ld.w      	r2, (r3, 0)
     a1e:	9261      	ld.w      	r3, (r2, 0x4)
     a20:	68c5      	andn      	r3, r1
     a22:	3ba6      	bseti      	r3, r3, 6
		{
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x07000000;										//EPWM0_Y(PA0.14->AF4)
		}
		else if(EPWM_IO_G==3)
		{
			GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x50000000;										//EPWM0_Y(PA0.15->AF2)
     a24:	b261      	st.w      	r3, (r2, 0x4)
     a26:	043c      	br      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
		else if(EPWM_IO_G==1)
     a28:	3941      	cmpnei      	r1, 1
     a2a:	080b      	bt      	0xa40	// a40 <EPWM_IO_Init+0x30>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XF0FFFFFF)|0x06000000;										//EPWM0_X(PA0.06->AF3)
     a2c:	1362      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     a2e:	32f0      	movi      	r2, 240
     a30:	9320      	ld.w      	r1, (r3, 0)
     a32:	9160      	ld.w      	r3, (r1, 0)
     a34:	4254      	lsli      	r2, r2, 20
     a36:	68c9      	andn      	r3, r2
     a38:	3bb9      	bseti      	r3, r3, 25
     a3a:	3bba      	bseti      	r3, r3, 26
	}
	else if(EPWM_IO_MODE_X==PWM_EP4)
	{
		if(EPWM_IO_G==0)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00600000;										//EPWM_EP4(PA1.5->AF3)
     a3c:	b160      	st.w      	r3, (r1, 0)
		}
	}
}
     a3e:	0430      	br      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
		else if(EPWM_IO_G==2)
     a40:	3942      	cmpnei      	r1, 2
     a42:	080a      	bt      	0xa56	// a56 <EPWM_IO_Init+0x46>
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFF0FFF)|0x00005000;										//EPWM0_X(PC0.3->AF2)
     a44:	127d      	lrw      	r3, 0x20000044	// bb8 <EPWM_IO_Init+0x1a8>
     a46:	32f0      	movi      	r2, 240
     a48:	9320      	ld.w      	r1, (r3, 0)
     a4a:	9160      	ld.w      	r3, (r1, 0)
     a4c:	4248      	lsli      	r2, r2, 8
     a4e:	68c9      	andn      	r3, r2
     a50:	3bac      	bseti      	r3, r3, 12
     a52:	3bae      	bseti      	r3, r3, 14
     a54:	07f4      	br      	0xa3c	// a3c <EPWM_IO_Init+0x2c>
		else if(EPWM_IO_G==3)
     a56:	3943      	cmpnei      	r1, 3
     a58:	080b      	bt      	0xa6e	// a6e <EPWM_IO_Init+0x5e>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFF0FFFF)|0x00070000;										//EPWM0_X(PA1.4->AF4)
     a5a:	1279      	lrw      	r3, 0x2000004c	// bbc <EPWM_IO_Init+0x1ac>
     a5c:	32f0      	movi      	r2, 240
     a5e:	9320      	ld.w      	r1, (r3, 0)
     a60:	424c      	lsli      	r2, r2, 12
     a62:	9160      	ld.w      	r3, (r1, 0)
     a64:	68c9      	andn      	r3, r2
     a66:	32e0      	movi      	r2, 224
     a68:	424b      	lsli      	r2, r2, 11
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00700000;										//EPWM1_X(PA1.5->AF4)
     a6a:	6cc8      	or      	r3, r2
     a6c:	07e8      	br      	0xa3c	// a3c <EPWM_IO_Init+0x2c>
		else if(EPWM_IO_G==4)
     a6e:	3944      	cmpnei      	r1, 4
     a70:	0817      	bt      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFF0FFFFF)|0x00700000;										//EPWM0_X(PA0.13->AF4)
     a72:	1271      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     a74:	32f0      	movi      	r2, 240
     a76:	9320      	ld.w      	r1, (r3, 0)
     a78:	4250      	lsli      	r2, r2, 16
     a7a:	9161      	ld.w      	r3, (r1, 0x4)
     a7c:	68c9      	andn      	r3, r2
     a7e:	32e0      	movi      	r2, 224
     a80:	424f      	lsli      	r2, r2, 15
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x07000000;										//EPWM0_Y(PA0.14->AF4)
     a82:	6cc8      	or      	r3, r2
     a84:	040c      	br      	0xa9c	// a9c <EPWM_IO_Init+0x8c>
	else if(EPWM_IO_MODE_X==PWM_Y0)
     a86:	3841      	cmpnei      	r0, 1
     a88:	082c      	bt      	0xae0	// ae0 <EPWM_IO_Init+0xd0>
		if(EPWM_IO_G==0)
     a8a:	3940      	cmpnei      	r1, 0
     a8c:	080a      	bt      	0xaa0	// aa0 <EPWM_IO_Init+0x90>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFF0FF)|0x00000400;										//EPWM0_Y(PA0.10->AF1)
     a8e:	126a      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     a90:	32f0      	movi      	r2, 240
     a92:	9320      	ld.w      	r1, (r3, 0)
     a94:	9161      	ld.w      	r3, (r1, 0x4)
     a96:	4244      	lsli      	r2, r2, 4
     a98:	68c9      	andn      	r3, r2
     a9a:	3baa      	bseti      	r3, r3, 10
     a9c:	b161      	st.w      	r3, (r1, 0x4)
}
     a9e:	783c      	rts
		else if(EPWM_IO_G==1)
     aa0:	3941      	cmpnei      	r1, 1
     aa2:	080a      	bt      	0xab6	// ab6 <EPWM_IO_Init+0xa6>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFF0FFFFF)|0x00600000;										//EPWM0_Y(PA0.05->AF3)
     aa4:	1264      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00600000;										//EPWM_EP4(PA1.5->AF3)
     aa6:	9320      	ld.w      	r1, (r3, 0)
     aa8:	32f0      	movi      	r2, 240
     aaa:	9160      	ld.w      	r3, (r1, 0)
     aac:	4250      	lsli      	r2, r2, 16
     aae:	68c9      	andn      	r3, r2
     ab0:	3bb5      	bseti      	r3, r3, 21
     ab2:	3bb6      	bseti      	r3, r3, 22
     ab4:	07c4      	br      	0xa3c	// a3c <EPWM_IO_Init+0x2c>
		else if(EPWM_IO_G==2)
     ab6:	3942      	cmpnei      	r1, 2
     ab8:	080a      	bt      	0xacc	// acc <EPWM_IO_Init+0xbc>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x07000000;										//EPWM0_Y(PA0.14->AF4)
     aba:	117f      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     abc:	32f0      	movi      	r2, 240
     abe:	9320      	ld.w      	r1, (r3, 0)
     ac0:	4254      	lsli      	r2, r2, 20
     ac2:	9161      	ld.w      	r3, (r1, 0x4)
     ac4:	68c9      	andn      	r3, r2
     ac6:	32e0      	movi      	r2, 224
     ac8:	4253      	lsli      	r2, r2, 19
     aca:	07dc      	br      	0xa82	// a82 <EPWM_IO_Init+0x72>
		else if(EPWM_IO_G==3)
     acc:	3943      	cmpnei      	r1, 3
     ace:	0be8      	bt      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x50000000;										//EPWM0_Y(PA0.15->AF2)
     ad0:	1179      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     ad2:	9340      	ld.w      	r2, (r3, 0)
     ad4:	9261      	ld.w      	r3, (r2, 0x4)
     ad6:	4364      	lsli      	r3, r3, 4
     ad8:	4b64      	lsri      	r3, r3, 4
     ada:	3bbc      	bseti      	r3, r3, 28
     adc:	3bbe      	bseti      	r3, r3, 30
     ade:	07a3      	br      	0xa24	// a24 <EPWM_IO_Init+0x14>
	else if(EPWM_IO_MODE_X==PWM_X1)
     ae0:	3842      	cmpnei      	r0, 2
     ae2:	082c      	bt      	0xb3a	// b3a <EPWM_IO_Init+0x12a>
		if(EPWM_IO_G==0)
     ae4:	3940      	cmpnei      	r1, 0
     ae6:	0809      	bt      	0xaf8	// af8 <EPWM_IO_Init+0xe8>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0X0FFFFFFF)|0x40000000;										//EPWM1_X(PA0.7->AF1)
     ae8:	1173      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     aea:	9340      	ld.w      	r2, (r3, 0)
     aec:	9260      	ld.w      	r3, (r2, 0)
     aee:	4364      	lsli      	r3, r3, 4
     af0:	4b64      	lsri      	r3, r3, 4
     af2:	3bbe      	bseti      	r3, r3, 30
			GPIOD0->CONLR=(GPIOD0->CONLR & 0XFFFFFFF0)|0x00000006;										//EPWM_EP1(PD0.0->AF3)
     af4:	b260      	st.w      	r3, (r2, 0)
     af6:	07d4      	br      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
		else if(EPWM_IO_G==1)
     af8:	3941      	cmpnei      	r1, 1
     afa:	080a      	bt      	0xb0e	// b0e <EPWM_IO_Init+0xfe>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00007000;										//EPWM1_X(PA0.11->AF4)
     afc:	116e      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     afe:	32f0      	movi      	r2, 240
     b00:	9320      	ld.w      	r1, (r3, 0)
     b02:	4248      	lsli      	r2, r2, 8
     b04:	9161      	ld.w      	r3, (r1, 0x4)
     b06:	68c9      	andn      	r3, r2
     b08:	32e0      	movi      	r2, 224
     b0a:	4247      	lsli      	r2, r2, 7
     b0c:	07bb      	br      	0xa82	// a82 <EPWM_IO_Init+0x72>
		else if(EPWM_IO_G==2)
     b0e:	3942      	cmpnei      	r1, 2
     b10:	080a      	bt      	0xb24	// b24 <EPWM_IO_Init+0x114>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFF0FFFFF)|0x00500000;										//EPWM1_X(PA0.13->AF2)
     b12:	1169      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     b14:	32f0      	movi      	r2, 240
     b16:	9320      	ld.w      	r1, (r3, 0)
     b18:	9161      	ld.w      	r3, (r1, 0x4)
     b1a:	4250      	lsli      	r2, r2, 16
     b1c:	68c9      	andn      	r3, r2
     b1e:	3bb4      	bseti      	r3, r3, 20
     b20:	3bb6      	bseti      	r3, r3, 22
     b22:	07bd      	br      	0xa9c	// a9c <EPWM_IO_Init+0x8c>
		else if(EPWM_IO_G==3)
     b24:	3943      	cmpnei      	r1, 3
     b26:	0bbc      	bt      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00700000;										//EPWM1_X(PA1.5->AF4)
     b28:	1165      	lrw      	r3, 0x2000004c	// bbc <EPWM_IO_Init+0x1ac>
     b2a:	32f0      	movi      	r2, 240
     b2c:	9320      	ld.w      	r1, (r3, 0)
     b2e:	4250      	lsli      	r2, r2, 16
     b30:	9160      	ld.w      	r3, (r1, 0)
     b32:	68c9      	andn      	r3, r2
     b34:	32e0      	movi      	r2, 224
     b36:	424f      	lsli      	r2, r2, 15
     b38:	0799      	br      	0xa6a	// a6a <EPWM_IO_Init+0x5a>
	else if(EPWM_IO_MODE_X==PWM_Y1)
     b3a:	3843      	cmpnei      	r0, 3
     b3c:	0820      	bt      	0xb7c	// b7c <EPWM_IO_Init+0x16c>
		if(EPWM_IO_G==0)
     b3e:	3940      	cmpnei      	r1, 0
     b40:	0808      	bt      	0xb50	// b50 <EPWM_IO_Init+0x140>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFFF0)|0x00000004;										//EPWM1_Y(PA0.8->AF1)
     b42:	107d      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     b44:	310f      	movi      	r1, 15
     b46:	9340      	ld.w      	r2, (r3, 0)
     b48:	9261      	ld.w      	r3, (r2, 0x4)
     b4a:	68c5      	andn      	r3, r1
     b4c:	3ba2      	bseti      	r3, r3, 2
     b4e:	076b      	br      	0xa24	// a24 <EPWM_IO_Init+0x14>
		else if(EPWM_IO_G==1)
     b50:	3941      	cmpnei      	r1, 1
     b52:	080a      	bt      	0xb66	// b66 <EPWM_IO_Init+0x156>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x05000000;										//EPWM1_Y(PA0.14->AF2)
     b54:	1078      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     b56:	32f0      	movi      	r2, 240
     b58:	9320      	ld.w      	r1, (r3, 0)
     b5a:	9161      	ld.w      	r3, (r1, 0x4)
     b5c:	4254      	lsli      	r2, r2, 20
     b5e:	68c9      	andn      	r3, r2
     b60:	3bb8      	bseti      	r3, r3, 24
     b62:	3bba      	bseti      	r3, r3, 26
     b64:	079c      	br      	0xa9c	// a9c <EPWM_IO_Init+0x8c>
		else if(EPWM_IO_G==2)
     b66:	3942      	cmpnei      	r1, 2
     b68:	0b9b      	bt      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFF0FFFF)|0x00070000;										//EPWM1_Y(PA0.12->AF4)
     b6a:	1073      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     b6c:	32f0      	movi      	r2, 240
     b6e:	9320      	ld.w      	r1, (r3, 0)
     b70:	424c      	lsli      	r2, r2, 12
     b72:	9161      	ld.w      	r3, (r1, 0x4)
     b74:	68c9      	andn      	r3, r2
     b76:	32e0      	movi      	r2, 224
     b78:	424b      	lsli      	r2, r2, 11
     b7a:	0784      	br      	0xa82	// a82 <EPWM_IO_Init+0x72>
	else if(EPWM_IO_MODE_X==PWM_X2)
     b7c:	3844      	cmpnei      	r0, 4
     b7e:	0827      	bt      	0xbcc	// bcc <EPWM_IO_Init+0x1bc>
		if(EPWM_IO_G==0)
     b80:	3940      	cmpnei      	r1, 0
     b82:	0809      	bt      	0xb94	// b94 <EPWM_IO_Init+0x184>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFF0FFFFF)|0x00400000;										//EPWM2_X(PA0.5->AF1)
     b84:	106c      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     b86:	32f0      	movi      	r2, 240
     b88:	9320      	ld.w      	r1, (r3, 0)
     b8a:	9160      	ld.w      	r3, (r1, 0)
     b8c:	4250      	lsli      	r2, r2, 16
     b8e:	68c9      	andn      	r3, r2
     b90:	3bb6      	bseti      	r3, r3, 22
     b92:	0755      	br      	0xa3c	// a3c <EPWM_IO_Init+0x2c>
		else if(EPWM_IO_G==1)
     b94:	3941      	cmpnei      	r1, 1
     b96:	0809      	bt      	0xba8	// ba8 <EPWM_IO_Init+0x198>
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFFF0F)|0x00000070;										//EPWM2_X(PC0.1->AF4)
     b98:	1068      	lrw      	r3, 0x20000044	// bb8 <EPWM_IO_Init+0x1a8>
     b9a:	31f0      	movi      	r1, 240
     b9c:	9340      	ld.w      	r2, (r3, 0)
     b9e:	9260      	ld.w      	r3, (r2, 0)
     ba0:	68c5      	andn      	r3, r1
     ba2:	3170      	movi      	r1, 112
     ba4:	6cc4      	or      	r3, r1
     ba6:	07a7      	br      	0xaf4	// af4 <EPWM_IO_Init+0xe4>
		else if(EPWM_IO_G==2)
     ba8:	3942      	cmpnei      	r1, 2
     baa:	0b7a      	bt      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00005000;										//EPWM2_X(PA0.11->AF2)
     bac:	1062      	lrw      	r3, 0x20000050	// bb4 <EPWM_IO_Init+0x1a4>
     bae:	32f0      	movi      	r2, 240
     bb0:	9320      	ld.w      	r1, (r3, 0)
     bb2:	0407      	br      	0xbc0	// bc0 <EPWM_IO_Init+0x1b0>
     bb4:	20000050 	.long	0x20000050
     bb8:	20000044 	.long	0x20000044
     bbc:	2000004c 	.long	0x2000004c
     bc0:	9161      	ld.w      	r3, (r1, 0x4)
     bc2:	4248      	lsli      	r2, r2, 8
     bc4:	68c9      	andn      	r3, r2
     bc6:	3bac      	bseti      	r3, r3, 12
     bc8:	3bae      	bseti      	r3, r3, 14
     bca:	0769      	br      	0xa9c	// a9c <EPWM_IO_Init+0x8c>
	else if(EPWM_IO_MODE_X==PWM_Y2)
     bcc:	3845      	cmpnei      	r0, 5
     bce:	0816      	bt      	0xbfa	// bfa <EPWM_IO_Init+0x1ea>
		if(EPWM_IO_G==0)
     bd0:	3940      	cmpnei      	r1, 0
     bd2:	0809      	bt      	0xbe4	// be4 <EPWM_IO_Init+0x1d4>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XF0FFFFFF)|0x04000000;										//EPWM2_Y(PA0.6->AF1)
     bd4:	1365      	lrw      	r3, 0x20000050	// d68 <EPWM_PX_PY_Configure+0xde>
     bd6:	32f0      	movi      	r2, 240
     bd8:	9320      	ld.w      	r1, (r3, 0)
     bda:	9160      	ld.w      	r3, (r1, 0)
     bdc:	4254      	lsli      	r2, r2, 20
     bde:	68c9      	andn      	r3, r2
     be0:	3bba      	bseti      	r3, r3, 26
     be2:	072d      	br      	0xa3c	// a3c <EPWM_IO_Init+0x2c>
		else if(EPWM_IO_G==1)
     be4:	3941      	cmpnei      	r1, 1
     be6:	0b5c      	bt      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFF0FFFF)|0x00050000;										//EPWM2_Y(PA0.12->AF2)
     be8:	1360      	lrw      	r3, 0x20000050	// d68 <EPWM_PX_PY_Configure+0xde>
     bea:	32f0      	movi      	r2, 240
     bec:	9320      	ld.w      	r1, (r3, 0)
     bee:	9161      	ld.w      	r3, (r1, 0x4)
     bf0:	424c      	lsli      	r2, r2, 12
     bf2:	68c9      	andn      	r3, r2
     bf4:	3bb0      	bseti      	r3, r3, 16
     bf6:	3bb2      	bseti      	r3, r3, 18
     bf8:	0752      	br      	0xa9c	// a9c <EPWM_IO_Init+0x8c>
	else if(EPWM_IO_MODE_X==PWM_EP0)																	
     bfa:	3846      	cmpnei      	r0, 6
     bfc:	080c      	bt      	0xc14	// c14 <EPWM_IO_Init+0x204>
		if(EPWM_IO_G==0)
     bfe:	3940      	cmpnei      	r1, 0
     c00:	0b4f      	bt      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFF0FF)|0x00000500;										//EPWM2_Y(PA0.2->AF2)
     c02:	127a      	lrw      	r3, 0x20000050	// d68 <EPWM_PX_PY_Configure+0xde>
     c04:	32f0      	movi      	r2, 240
     c06:	9320      	ld.w      	r1, (r3, 0)
     c08:	9160      	ld.w      	r3, (r1, 0)
     c0a:	4244      	lsli      	r2, r2, 4
     c0c:	68c9      	andn      	r3, r2
     c0e:	3ba8      	bseti      	r3, r3, 8
     c10:	3baa      	bseti      	r3, r3, 10
     c12:	0715      	br      	0xa3c	// a3c <EPWM_IO_Init+0x2c>
	else if(EPWM_IO_MODE_X==PWM_EP1)
     c14:	3847      	cmpnei      	r0, 7
     c16:	080b      	bt      	0xc2c	// c2c <EPWM_IO_Init+0x21c>
		if(EPWM_IO_G==0)
     c18:	3940      	cmpnei      	r1, 0
     c1a:	0b42      	bt      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
			GPIOD0->CONLR=(GPIOD0->CONLR & 0XFFFFFFF0)|0x00000006;										//EPWM_EP1(PD0.0->AF3)
     c1c:	1274      	lrw      	r3, 0x20000040	// d6c <EPWM_PX_PY_Configure+0xe2>
     c1e:	310f      	movi      	r1, 15
     c20:	9340      	ld.w      	r2, (r3, 0)
     c22:	9260      	ld.w      	r3, (r2, 0)
     c24:	68c5      	andn      	r3, r1
     c26:	3ba1      	bseti      	r3, r3, 1
     c28:	3ba2      	bseti      	r3, r3, 2
     c2a:	0765      	br      	0xaf4	// af4 <EPWM_IO_Init+0xe4>
	else if(EPWM_IO_MODE_X==PWM_EP2)
     c2c:	3848      	cmpnei      	r0, 8
     c2e:	080b      	bt      	0xc44	// c44 <EPWM_IO_Init+0x234>
		if(EPWM_IO_G==0)
     c30:	3940      	cmpnei      	r1, 0
     c32:	0b36      	bt      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFF0FF)|0x00000400;										//EPWM_EP2(PC0.2->AF1)
     c34:	126f      	lrw      	r3, 0x20000044	// d70 <EPWM_PX_PY_Configure+0xe6>
     c36:	32f0      	movi      	r2, 240
     c38:	9320      	ld.w      	r1, (r3, 0)
     c3a:	9160      	ld.w      	r3, (r1, 0)
     c3c:	4244      	lsli      	r2, r2, 4
     c3e:	68c9      	andn      	r3, r2
     c40:	3baa      	bseti      	r3, r3, 10
     c42:	06fd      	br      	0xa3c	// a3c <EPWM_IO_Init+0x2c>
	else if(EPWM_IO_MODE_X==PWM_EP3)
     c44:	3849      	cmpnei      	r0, 9
     c46:	080b      	bt      	0xc5c	// c5c <EPWM_IO_Init+0x24c>
		if(EPWM_IO_G==0)
     c48:	3940      	cmpnei      	r1, 0
     c4a:	0b2a      	bt      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFF0FFF)|0x00004000;										//EPWM_EP3(PC0.3->AF1)
     c4c:	1269      	lrw      	r3, 0x20000044	// d70 <EPWM_PX_PY_Configure+0xe6>
     c4e:	32f0      	movi      	r2, 240
     c50:	9320      	ld.w      	r1, (r3, 0)
     c52:	9160      	ld.w      	r3, (r1, 0)
     c54:	4248      	lsli      	r2, r2, 8
     c56:	68c9      	andn      	r3, r2
     c58:	3bae      	bseti      	r3, r3, 14
     c5a:	06f1      	br      	0xa3c	// a3c <EPWM_IO_Init+0x2c>
	else if(EPWM_IO_MODE_X==PWM_EP4)
     c5c:	384a      	cmpnei      	r0, 10
     c5e:	0b20      	bt      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
		if(EPWM_IO_G==0)
     c60:	3940      	cmpnei      	r1, 0
     c62:	0b1e      	bt      	0xa9e	// a9e <EPWM_IO_Init+0x8e>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00600000;										//EPWM_EP4(PA1.5->AF3)
     c64:	1264      	lrw      	r3, 0x2000004c	// d74 <EPWM_PX_PY_Configure+0xea>
     c66:	0720      	br      	0xaa6	// aa6 <EPWM_IO_Init+0x96>

00000c68 <EPWM_CONTER_Configure>:
//EPWM_DINM;0~0XFFF
//ReturnValue:NONE
/*************************************************************/  
//EPWM_CLK=PCLK/(2^DIVN)/(DINM+1)
void EPWM_CONTER_Configure(EPWM_CMODE_TypeDef EPWM_ContMode_X , EPWM_Conter_NUM_TypeDef EMP_Conter_X, EPWM_Overflow_Mode_TypeDef EMP_Overflow_Mode_X , U8_T  EPWM_DIVN , U16_T  EPWM_DINM )
{
     c68:	14c3      	push      	r4-r6
     c6a:	d8ae1006 	ld.h      	r5, (sp, 0xc)
	EPWM->CR |= CKEN;
	EPWM->CR = EPWM_ContMode_X | EMP_Conter_X | EMP_Overflow_Mode_X | (EPWM_DIVN<<5) | (EPWM_DINM<<8) | CKEN ;
     c6e:	3ab6      	bseti      	r2, r2, 22
     c70:	6c84      	or      	r2, r1
	EPWM->CR |= CKEN;
     c72:	1282      	lrw      	r4, 0x2000001c	// d78 <EPWM_PX_PY_Configure+0xee>
	EPWM->CR = EPWM_ContMode_X | EMP_Conter_X | EMP_Overflow_Mode_X | (EPWM_DIVN<<5) | (EPWM_DINM<<8) | CKEN ;
     c74:	4528      	lsli      	r1, r5, 8
	EPWM->CR |= CKEN;
     c76:	9480      	ld.w      	r4, (r4, 0)
	EPWM->CR = EPWM_ContMode_X | EMP_Conter_X | EMP_Overflow_Mode_X | (EPWM_DIVN<<5) | (EPWM_DINM<<8) | CKEN ;
     c78:	6c84      	or      	r2, r1
	EPWM->CR |= CKEN;
     c7a:	94c0      	ld.w      	r6, (r4, 0)
	EPWM->CR = EPWM_ContMode_X | EMP_Conter_X | EMP_Overflow_Mode_X | (EPWM_DIVN<<5) | (EPWM_DINM<<8) | CKEN ;
     c7c:	6c08      	or      	r0, r2
     c7e:	4365      	lsli      	r3, r3, 5
	EPWM->CR |= CKEN;
     c80:	3eb6      	bseti      	r6, r6, 22
	EPWM->CR = EPWM_ContMode_X | EMP_Conter_X | EMP_Overflow_Mode_X | (EPWM_DIVN<<5) | (EPWM_DINM<<8) | CKEN ;
     c82:	6cc0      	or      	r3, r0
	EPWM->CR |= CKEN;
     c84:	b4c0      	st.w      	r6, (r4, 0)
	EPWM->CR = EPWM_ContMode_X | EMP_Conter_X | EMP_Overflow_Mode_X | (EPWM_DIVN<<5) | (EPWM_DINM<<8) | CKEN ;
     c86:	b460      	st.w      	r3, (r4, 0)
}
     c88:	1483      	pop      	r4-r6

00000c8a <EPWM_PX_PY_Configure>:
//ReturnValue:NONE
/*************************************************************/  
void EPWM_PX_PY_Configure(EPWM_PXxOrPYx_TypeDef EPWM_PXxOrPYx , EPWM_StartStopEvent_PxOUT_TypeDef EPWM_StartStopEvent_X , EPWM_PendEvent_PxOUT_TypeDef EPWM_PendEvent_X , 
						EPWM_CentralEvent_PxOUT_TypeDef EPWM_CentralEvent_X , EPWM_EqCMPAEvent_PxOUT_TypeDef EPWM_EqCMPAEvent_X , EPWM_EqCMPBEvent_PxOUT_TypeDef EPWM_EqCMPBEvent_X  ,
						U16_T EPWM_CNTRX , U16_T EPWM_CMPARX , U16_T EPWM_CMPBRX)
{
     c8a:	14c4      	push      	r4-r7
     c8c:	1425      	subi      	sp, sp, 20
     c8e:	b860      	st.w      	r3, (sp, 0)
     c90:	9869      	ld.w      	r3, (sp, 0x24)
     c92:	b861      	st.w      	r3, (sp, 0x4)
     c94:	986a      	ld.w      	r3, (sp, 0x28)
     c96:	b862      	st.w      	r3, (sp, 0x8)
     c98:	d86e1018 	ld.h      	r3, (sp, 0x30)
     c9c:	b863      	st.w      	r3, (sp, 0xc)
	if(EPWM_PXxOrPYx==EPWM_P0X)
     c9e:	3840      	cmpnei      	r0, 0
{
     ca0:	d86e101a 	ld.h      	r3, (sp, 0x34)
     ca4:	d88e1016 	ld.h      	r4, (sp, 0x2c)
     ca8:	b864      	st.w      	r3, (sp, 0x10)
	if(EPWM_PXxOrPYx==EPWM_P0X)
     caa:	0823      	bt      	0xcf0	// cf0 <EPWM_PX_PY_Configure+0x66>
	{
		EPWM->WGCR0&=0XFFFFFC00;
     cac:	1113      	lrw      	r0, 0x2000001c	// d78 <EPWM_PX_PY_Configure+0xee>
     cae:	3780      	movi      	r7, 128
     cb0:	90c0      	ld.w      	r6, (r0, 0)
     cb2:	61d8      	addu      	r7, r6
     cb4:	9701      	ld.w      	r0, (r7, 0x4)
     cb6:	11b2      	lrw      	r5, 0x3ff	// d7c <EPWM_PX_PY_Configure+0xf2>
     cb8:	6815      	andn      	r0, r5
     cba:	b701      	st.w      	r0, (r7, 0x4)
		EPWM->WGCR0|=(EPWM_StartStopEvent_X<<8)|(EPWM_PendEvent_X<<6)|(EPWM_CentralEvent_X<<4)|(EPWM_EqCMPBEvent_X<<2)|EPWM_EqCMPAEvent_X;
     cbc:	9862      	ld.w      	r3, (sp, 0x8)
     cbe:	4302      	lsli      	r0, r3, 2
     cc0:	97a1      	ld.w      	r5, (r7, 0x4)
     cc2:	9861      	ld.w      	r3, (sp, 0x4)
     cc4:	6d4c      	or      	r5, r3
     cc6:	9860      	ld.w      	r3, (sp, 0)
     cc8:	6d40      	or      	r5, r0
     cca:	4364      	lsli      	r3, r3, 4
     ccc:	6cd4      	or      	r3, r5
     cce:	4246      	lsli      	r2, r2, 6
     cd0:	6cc8      	or      	r3, r2
     cd2:	4128      	lsli      	r1, r1, 8
		EPWM->CMPBR0=(0xA5<<24)|EPWM_CMPBRX;
	}
	else if(EPWM_PXxOrPYx==EPWM_P0Y)
	{
		EPWM->WGCR0&=0XFFF003FF;
		EPWM->WGCR0|=(EPWM_StartStopEvent_X<<18)|(EPWM_PendEvent_X<<16)|(EPWM_CentralEvent_X<<14)|(EPWM_EqCMPBEvent_X<<12)|(EPWM_EqCMPAEvent_X<<10);
     cd4:	6c4c      	or      	r1, r3
		EPWM->CNTR0=(0xA5<<24)|EPWM_CNTRX;
     cd6:	33a5      	movi      	r3, 165
     cd8:	4378      	lsli      	r3, r3, 24
		EPWM->CMPAR0=(0xA5<<24)|EPWM_CMPARX;
     cda:	9843      	ld.w      	r2, (sp, 0xc)
     cdc:	6c8c      	or      	r2, r3
		EPWM->CNTR0=(0xA5<<24)|EPWM_CNTRX;
     cde:	6d0c      	or      	r4, r3
		EPWM->WGCR0|=(EPWM_StartStopEvent_X<<18)|(EPWM_PendEvent_X<<16)|(EPWM_CentralEvent_X<<14)|(EPWM_EqCMPBEvent_X<<12)|(EPWM_EqCMPAEvent_X<<10);
     ce0:	b721      	st.w      	r1, (r7, 0x4)
		EPWM->CNTR0=(0xA5<<24)|EPWM_CNTRX;
     ce2:	b683      	st.w      	r4, (r6, 0xc)
		EPWM->CMPAR0=(0xA5<<24)|EPWM_CMPARX;
     ce4:	b64f      	st.w      	r2, (r6, 0x3c)
		EPWM->CMPBR0=(0xA5<<24)|EPWM_CMPBRX;
     ce6:	9844      	ld.w      	r2, (sp, 0x10)
     ce8:	6c8c      	or      	r2, r3
     cea:	b652      	st.w      	r2, (r6, 0x48)
		EPWM->WGCR2|=(EPWM_StartStopEvent_X<<18)|(EPWM_PendEvent_X<<16)|(EPWM_CentralEvent_X<<14)|(EPWM_EqCMPBEvent_X<<12)|(EPWM_EqCMPAEvent_X<<10);
		EPWM->CNTR2=(0xA5<<24)|EPWM_CNTRX;
		EPWM->CMPAR2=(0xA5<<24)|EPWM_CMPARX;
		EPWM->CMPBR2=(0xA5<<24)|EPWM_CMPBRX;
	}
}
     cec:	1405      	addi      	sp, sp, 20
     cee:	1484      	pop      	r4-r7
	else if(EPWM_PXxOrPYx==EPWM_P0Y)
     cf0:	3841      	cmpnei      	r0, 1
     cf2:	0817      	bt      	0xd20	// d20 <EPWM_PX_PY_Configure+0x96>
		EPWM->WGCR0&=0XFFF003FF;
     cf4:	1101      	lrw      	r0, 0x2000001c	// d78 <EPWM_PX_PY_Configure+0xee>
     cf6:	3780      	movi      	r7, 128
     cf8:	90c0      	ld.w      	r6, (r0, 0)
     cfa:	61d8      	addu      	r7, r6
     cfc:	9701      	ld.w      	r0, (r7, 0x4)
     cfe:	11a1      	lrw      	r5, 0xffc00	// d80 <EPWM_PX_PY_Configure+0xf6>
     d00:	6815      	andn      	r0, r5
		EPWM->WGCR0|=(EPWM_StartStopEvent_X<<18)|(EPWM_PendEvent_X<<16)|(EPWM_CentralEvent_X<<14)|(EPWM_EqCMPBEvent_X<<12)|(EPWM_EqCMPAEvent_X<<10);
     d02:	9861      	ld.w      	r3, (sp, 0x4)
		EPWM->WGCR0&=0XFFF003FF;
     d04:	b701      	st.w      	r0, (r7, 0x4)
		EPWM->WGCR0|=(EPWM_StartStopEvent_X<<18)|(EPWM_PendEvent_X<<16)|(EPWM_CentralEvent_X<<14)|(EPWM_EqCMPBEvent_X<<12)|(EPWM_EqCMPAEvent_X<<10);
     d06:	9701      	ld.w      	r0, (r7, 0x4)
     d08:	43aa      	lsli      	r5, r3, 10
     d0a:	9862      	ld.w      	r3, (sp, 0x8)
     d0c:	6d40      	or      	r5, r0
     d0e:	430c      	lsli      	r0, r3, 12
     d10:	9860      	ld.w      	r3, (sp, 0)
     d12:	6c14      	or      	r0, r5
     d14:	436e      	lsli      	r3, r3, 14
     d16:	6cc0      	or      	r3, r0
     d18:	4250      	lsli      	r2, r2, 16
     d1a:	6cc8      	or      	r3, r2
     d1c:	4132      	lsli      	r1, r1, 18
     d1e:	07db      	br      	0xcd4	// cd4 <EPWM_PX_PY_Configure+0x4a>
	else if(EPWM_PXxOrPYx==EPWM_P1X)
     d20:	3842      	cmpnei      	r0, 2
     d22:	0831      	bt      	0xd84	// d84 <EPWM_PX_PY_Configure+0xfa>
		EPWM->WGCR1&=0XFFFFFC00;
     d24:	1015      	lrw      	r0, 0x2000001c	// d78 <EPWM_PX_PY_Configure+0xee>
     d26:	3780      	movi      	r7, 128
     d28:	90c0      	ld.w      	r6, (r0, 0)
     d2a:	61d8      	addu      	r7, r6
     d2c:	9702      	ld.w      	r0, (r7, 0x8)
     d2e:	10b4      	lrw      	r5, 0x3ff	// d7c <EPWM_PX_PY_Configure+0xf2>
     d30:	6815      	andn      	r0, r5
     d32:	b702      	st.w      	r0, (r7, 0x8)
		EPWM->WGCR1|=(EPWM_StartStopEvent_X<<8)|(EPWM_PendEvent_X<<6)|(EPWM_CentralEvent_X<<4)|(EPWM_EqCMPBEvent_X<<2)|EPWM_EqCMPAEvent_X;
     d34:	9862      	ld.w      	r3, (sp, 0x8)
     d36:	97a2      	ld.w      	r5, (r7, 0x8)
     d38:	4302      	lsli      	r0, r3, 2
     d3a:	9861      	ld.w      	r3, (sp, 0x4)
     d3c:	6cd4      	or      	r3, r5
     d3e:	6d4f      	mov      	r5, r3
     d40:	9860      	ld.w      	r3, (sp, 0)
     d42:	6d40      	or      	r5, r0
     d44:	4364      	lsli      	r3, r3, 4
     d46:	6cd4      	or      	r3, r5
     d48:	4246      	lsli      	r2, r2, 6
     d4a:	6cc8      	or      	r3, r2
     d4c:	4128      	lsli      	r1, r1, 8
		EPWM->WGCR1|=(EPWM_StartStopEvent_X<<18)|(EPWM_PendEvent_X<<16)|(EPWM_CentralEvent_X<<14)|(EPWM_EqCMPBEvent_X<<12)|(EPWM_EqCMPAEvent_X<<10);
     d4e:	6c4c      	or      	r1, r3
		EPWM->CNTR1=(0xA5<<24)|EPWM_CNTRX;
     d50:	33a5      	movi      	r3, 165
     d52:	4378      	lsli      	r3, r3, 24
		EPWM->CMPAR1=(0xA5<<24)|EPWM_CMPARX;
     d54:	9843      	ld.w      	r2, (sp, 0xc)
     d56:	6c8c      	or      	r2, r3
		EPWM->CNTR1=(0xA5<<24)|EPWM_CNTRX;
     d58:	6d0c      	or      	r4, r3
		EPWM->WGCR1|=(EPWM_StartStopEvent_X<<18)|(EPWM_PendEvent_X<<16)|(EPWM_CentralEvent_X<<14)|(EPWM_EqCMPBEvent_X<<12)|(EPWM_EqCMPAEvent_X<<10);
     d5a:	b722      	st.w      	r1, (r7, 0x8)
		EPWM->CNTR1=(0xA5<<24)|EPWM_CNTRX;
     d5c:	b687      	st.w      	r4, (r6, 0x1c)
		EPWM->CMPAR1=(0xA5<<24)|EPWM_CMPARX;
     d5e:	b655      	st.w      	r2, (r6, 0x54)
		EPWM->CMPBR1=(0xA5<<24)|EPWM_CMPBRX;
     d60:	9844      	ld.w      	r2, (sp, 0x10)
     d62:	6c8c      	or      	r2, r3
     d64:	b658      	st.w      	r2, (r6, 0x60)
     d66:	07c3      	br      	0xcec	// cec <EPWM_PX_PY_Configure+0x62>
     d68:	20000050 	.long	0x20000050
     d6c:	20000040 	.long	0x20000040
     d70:	20000044 	.long	0x20000044
     d74:	2000004c 	.long	0x2000004c
     d78:	2000001c 	.long	0x2000001c
     d7c:	000003ff 	.long	0x000003ff
     d80:	000ffc00 	.long	0x000ffc00
	else if(EPWM_PXxOrPYx==EPWM_P1Y)
     d84:	3843      	cmpnei      	r0, 3
     d86:	0817      	bt      	0xdb4	// db4 <EPWM_PX_PY_Configure+0x12a>
		EPWM->WGCR1&=0XFFF003FF;
     d88:	1303      	lrw      	r0, 0x2000001c	// f14 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x36>
     d8a:	3780      	movi      	r7, 128
     d8c:	90c0      	ld.w      	r6, (r0, 0)
     d8e:	61d8      	addu      	r7, r6
     d90:	9702      	ld.w      	r0, (r7, 0x8)
     d92:	13a2      	lrw      	r5, 0xffc00	// f18 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x3a>
     d94:	6815      	andn      	r0, r5
		EPWM->WGCR1|=(EPWM_StartStopEvent_X<<18)|(EPWM_PendEvent_X<<16)|(EPWM_CentralEvent_X<<14)|(EPWM_EqCMPBEvent_X<<12)|(EPWM_EqCMPAEvent_X<<10);
     d96:	9861      	ld.w      	r3, (sp, 0x4)
		EPWM->WGCR1&=0XFFF003FF;
     d98:	b702      	st.w      	r0, (r7, 0x8)
		EPWM->WGCR1|=(EPWM_StartStopEvent_X<<18)|(EPWM_PendEvent_X<<16)|(EPWM_CentralEvent_X<<14)|(EPWM_EqCMPBEvent_X<<12)|(EPWM_EqCMPAEvent_X<<10);
     d9a:	9702      	ld.w      	r0, (r7, 0x8)
     d9c:	43aa      	lsli      	r5, r3, 10
     d9e:	9862      	ld.w      	r3, (sp, 0x8)
     da0:	6d40      	or      	r5, r0
     da2:	430c      	lsli      	r0, r3, 12
     da4:	9860      	ld.w      	r3, (sp, 0)
     da6:	6c14      	or      	r0, r5
     da8:	436e      	lsli      	r3, r3, 14
     daa:	6cc0      	or      	r3, r0
     dac:	4250      	lsli      	r2, r2, 16
     dae:	6cc8      	or      	r3, r2
     db0:	4132      	lsli      	r1, r1, 18
     db2:	07ce      	br      	0xd4e	// d4e <EPWM_PX_PY_Configure+0xc4>
	else if(EPWM_PXxOrPYx==EPWM_P2X)
     db4:	3844      	cmpnei      	r0, 4
     db6:	0823      	bt      	0xdfc	// dfc <EPWM_PX_PY_Configure+0x172>
		EPWM->WGCR2&=0XFFFFFC00;
     db8:	1217      	lrw      	r0, 0x2000001c	// f14 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x36>
     dba:	3780      	movi      	r7, 128
     dbc:	90c0      	ld.w      	r6, (r0, 0)
     dbe:	61d8      	addu      	r7, r6
     dc0:	9703      	ld.w      	r0, (r7, 0xc)
     dc2:	12b7      	lrw      	r5, 0x3ff	// f1c <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x3e>
     dc4:	6815      	andn      	r0, r5
     dc6:	b703      	st.w      	r0, (r7, 0xc)
		EPWM->WGCR2|=(EPWM_StartStopEvent_X<<8)|(EPWM_PendEvent_X<<6)|(EPWM_CentralEvent_X<<4)|(EPWM_EqCMPBEvent_X<<2)|EPWM_EqCMPAEvent_X;
     dc8:	9862      	ld.w      	r3, (sp, 0x8)
     dca:	97a3      	ld.w      	r5, (r7, 0xc)
     dcc:	4302      	lsli      	r0, r3, 2
     dce:	9861      	ld.w      	r3, (sp, 0x4)
     dd0:	6cd4      	or      	r3, r5
     dd2:	6d4f      	mov      	r5, r3
     dd4:	9860      	ld.w      	r3, (sp, 0)
     dd6:	6d40      	or      	r5, r0
     dd8:	4364      	lsli      	r3, r3, 4
     dda:	6cd4      	or      	r3, r5
     ddc:	4246      	lsli      	r2, r2, 6
     dde:	6cc8      	or      	r3, r2
     de0:	4128      	lsli      	r1, r1, 8
     de2:	6c4c      	or      	r1, r3
		EPWM->CNTR2=(0xA5<<24)|EPWM_CNTRX;
     de4:	33a5      	movi      	r3, 165
     de6:	4378      	lsli      	r3, r3, 24
		EPWM->CMPAR2=(0xA5<<24)|EPWM_CMPARX;
     de8:	9843      	ld.w      	r2, (sp, 0xc)
     dea:	6c8c      	or      	r2, r3
		EPWM->CNTR2=(0xA5<<24)|EPWM_CNTRX;
     dec:	6d0c      	or      	r4, r3
		EPWM->WGCR2|=(EPWM_StartStopEvent_X<<18)|(EPWM_PendEvent_X<<16)|(EPWM_CentralEvent_X<<14)|(EPWM_EqCMPBEvent_X<<12)|(EPWM_EqCMPAEvent_X<<10);
     dee:	b723      	st.w      	r1, (r7, 0xc)
		EPWM->CNTR2=(0xA5<<24)|EPWM_CNTRX;
     df0:	b68b      	st.w      	r4, (r6, 0x2c)
		EPWM->CMPAR2=(0xA5<<24)|EPWM_CMPARX;
     df2:	b65b      	st.w      	r2, (r6, 0x6c)
		EPWM->CMPBR2=(0xA5<<24)|EPWM_CMPBRX;
     df4:	9844      	ld.w      	r2, (sp, 0x10)
     df6:	6c8c      	or      	r2, r3
     df8:	b65e      	st.w      	r2, (r6, 0x78)
}
     dfa:	0779      	br      	0xcec	// cec <EPWM_PX_PY_Configure+0x62>
	else if(EPWM_PXxOrPYx==EPWM_P2Y)
     dfc:	3845      	cmpnei      	r0, 5
     dfe:	0b77      	bt      	0xcec	// cec <EPWM_PX_PY_Configure+0x62>
		EPWM->WGCR2&=0XFFF003FF;
     e00:	1205      	lrw      	r0, 0x2000001c	// f14 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x36>
     e02:	3780      	movi      	r7, 128
     e04:	90c0      	ld.w      	r6, (r0, 0)
     e06:	61d8      	addu      	r7, r6
     e08:	9703      	ld.w      	r0, (r7, 0xc)
     e0a:	12a4      	lrw      	r5, 0xffc00	// f18 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x3a>
     e0c:	6815      	andn      	r0, r5
		EPWM->WGCR2|=(EPWM_StartStopEvent_X<<18)|(EPWM_PendEvent_X<<16)|(EPWM_CentralEvent_X<<14)|(EPWM_EqCMPBEvent_X<<12)|(EPWM_EqCMPAEvent_X<<10);
     e0e:	9861      	ld.w      	r3, (sp, 0x4)
		EPWM->WGCR2&=0XFFF003FF;
     e10:	b703      	st.w      	r0, (r7, 0xc)
		EPWM->WGCR2|=(EPWM_StartStopEvent_X<<18)|(EPWM_PendEvent_X<<16)|(EPWM_CentralEvent_X<<14)|(EPWM_EqCMPBEvent_X<<12)|(EPWM_EqCMPAEvent_X<<10);
     e12:	9703      	ld.w      	r0, (r7, 0xc)
     e14:	43aa      	lsli      	r5, r3, 10
     e16:	9862      	ld.w      	r3, (sp, 0x8)
     e18:	6d40      	or      	r5, r0
     e1a:	430c      	lsli      	r0, r3, 12
     e1c:	9860      	ld.w      	r3, (sp, 0)
     e1e:	6c14      	or      	r0, r5
     e20:	436e      	lsli      	r3, r3, 14
     e22:	6c0c      	or      	r0, r3
     e24:	4250      	lsli      	r2, r2, 16
     e26:	6c08      	or      	r0, r2
     e28:	4132      	lsli      	r1, r1, 18
     e2a:	6c40      	or      	r1, r0
     e2c:	07dc      	br      	0xde4	// de4 <EPWM_PX_PY_Configure+0x15a>

00000e2e <EPWM_OUTPUT_Configure>:
/*************************************************************/
//RED = DTR x (DIVM + 1) x 2DIVN x PCLK
//FED = DTF x (DIVM + 1) x 2DIVN x PCLK
void EPWM_OUTPUT_Configure(EPWM_PWM_XxOrPWM_Yx_TypeDef EPWM_PWM_XxOrPWM_Yx , EPWM_OUTSEL_TypeDef EPWM_OUTSEL_X , EPWM_X_POLARITY_TypeDef EPWM_X_POLARITY_X 
					, EPWM_Y_POLARITY_TypeDef EPWM_Y_POLARITY_X , EPWM_SRCSEL_TypeDef EPWM_SRCSEL_X , U16_T DTR , U16_T DTF)
{
     e2e:	14c3      	push      	r4-r6
	if(EPWM_PWM_XxOrPWM_Yx==EPWM_PWM_X0OrPWM_Y0)
     e30:	3840      	cmpnei      	r0, 0
{
     e32:	98c3      	ld.w      	r6, (sp, 0xc)
     e34:	d8ae1008 	ld.h      	r5, (sp, 0x10)
     e38:	d88e100a 	ld.h      	r4, (sp, 0x14)
	if(EPWM_PWM_XxOrPWM_Yx==EPWM_PWM_X0OrPWM_Y0)
     e3c:	080d      	bt      	0xe56	// e56 <EPWM_OUTPUT_Configure+0x28>
	{
		EPWM->OUTCR0=EPWM_OUTSEL_X|EPWM_X_POLARITY_X|EPWM_Y_POLARITY_X|EPWM_SRCSEL_X|(DTR<<6)|(DTF<<15);
     e3e:	448f      	lsli      	r4, r4, 15
     e40:	6d0c      	or      	r4, r3
     e42:	6d18      	or      	r4, r6
     e44:	1114      	lrw      	r0, 0x2000001c	// f14 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x36>
     e46:	6c90      	or      	r2, r4
     e48:	45a6      	lsli      	r5, r5, 6
     e4a:	9000      	ld.w      	r0, (r0, 0)
     e4c:	6c94      	or      	r2, r5
     e4e:	6c48      	or      	r1, r2
     e50:	207f      	addi      	r0, 128
     e52:	b024      	st.w      	r1, (r0, 0x10)
	}
	else if(EPWM_PWM_XxOrPWM_Yx==EPWM_PWM_X2OrPWM_Y2)
	{
		EPWM->OUTCR2=EPWM_OUTSEL_X|EPWM_X_POLARITY_X|EPWM_Y_POLARITY_X|EPWM_SRCSEL_X|(DTR<<6)|(DTF<<15);
	}
}
     e54:	1483      	pop      	r4-r6
	else if(EPWM_PWM_XxOrPWM_Yx==EPWM_PWM_X1OrPWM_Y1)
     e56:	3841      	cmpnei      	r0, 1
     e58:	080d      	bt      	0xe72	// e72 <EPWM_OUTPUT_Configure+0x44>
		EPWM->OUTCR1=EPWM_OUTSEL_X|EPWM_X_POLARITY_X|EPWM_Y_POLARITY_X|EPWM_SRCSEL_X|(DTR<<6)|(DTF<<15);
     e5a:	448f      	lsli      	r4, r4, 15
     e5c:	6d0c      	or      	r4, r3
     e5e:	6d18      	or      	r4, r6
     e60:	110d      	lrw      	r0, 0x2000001c	// f14 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x36>
     e62:	6c90      	or      	r2, r4
     e64:	45a6      	lsli      	r5, r5, 6
     e66:	9000      	ld.w      	r0, (r0, 0)
     e68:	6c94      	or      	r2, r5
     e6a:	6c48      	or      	r1, r2
     e6c:	207f      	addi      	r0, 128
     e6e:	b025      	st.w      	r1, (r0, 0x14)
     e70:	07f2      	br      	0xe54	// e54 <EPWM_OUTPUT_Configure+0x26>
	else if(EPWM_PWM_XxOrPWM_Yx==EPWM_PWM_X2OrPWM_Y2)
     e72:	3842      	cmpnei      	r0, 2
     e74:	0bf0      	bt      	0xe54	// e54 <EPWM_OUTPUT_Configure+0x26>
		EPWM->OUTCR2=EPWM_OUTSEL_X|EPWM_X_POLARITY_X|EPWM_Y_POLARITY_X|EPWM_SRCSEL_X|(DTR<<6)|(DTF<<15);
     e76:	448f      	lsli      	r4, r4, 15
     e78:	6d0c      	or      	r4, r3
     e7a:	6d18      	or      	r4, r6
     e7c:	1106      	lrw      	r0, 0x2000001c	// f14 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x36>
     e7e:	6c90      	or      	r2, r4
     e80:	45a6      	lsli      	r5, r5, 6
     e82:	9000      	ld.w      	r0, (r0, 0)
     e84:	6c94      	or      	r2, r5
     e86:	6c48      	or      	r1, r2
     e88:	207f      	addi      	r0, 128
     e8a:	b026      	st.w      	r1, (r0, 0x18)
}
     e8c:	07e4      	br      	0xe54	// e54 <EPWM_OUTPUT_Configure+0x26>

00000e8e <EPWM_Set_CNTRX_CMPARX_CMPBRX>:
//Load_PCMPARX:0~0xffff
//Load_PCMPBRX:0~0xffff
//ReturnValue:NONE
/*************************************************************/ 
void EPWM_Set_CNTRX_CMPARX_CMPBRX(EPWM_CNTRX_Selected_TypeDef EPWM_CNTRX_Selected , U16_T Load_PCNTRX , U16_T Load_PCMPARX , U16_T Load_PCMPBRX )
{
     e8e:	14c1      	push      	r4
	if(EPWM_CNTRX_Selected==EPWM_CNTR0)
     e90:	3840      	cmpnei      	r0, 0
     e92:	080c      	bt      	0xeaa	// eaa <EPWM_Set_CNTRX_CMPARX_CMPBRX+0x1c>
	{
		EPWM->CNTR0=(0xA5<<24)|Load_PCNTRX;
     e94:	34a5      	movi      	r4, 165
     e96:	4498      	lsli      	r4, r4, 24
     e98:	101f      	lrw      	r0, 0x2000001c	// f14 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x36>
     e9a:	6c50      	or      	r1, r4
     e9c:	9000      	ld.w      	r0, (r0, 0)
		EPWM->CMPAR0=(0xA5<<24)|Load_PCMPARX;
     e9e:	6c90      	or      	r2, r4
		EPWM->CMPBR0=(0xA5<<24)|Load_PCMPBRX;
     ea0:	6d0c      	or      	r4, r3
		EPWM->CNTR0=(0xA5<<24)|Load_PCNTRX;
     ea2:	b023      	st.w      	r1, (r0, 0xc)
		EPWM->CMPAR0=(0xA5<<24)|Load_PCMPARX;
     ea4:	b04f      	st.w      	r2, (r0, 0x3c)
		EPWM->CMPBR0=(0xA5<<24)|Load_PCMPBRX;
     ea6:	b092      	st.w      	r4, (r0, 0x48)
	{
		EPWM->CNTR2=(0xA5<<24)|Load_PCNTRX;
		EPWM->CMPAR2=(0xA5<<24)|Load_PCMPARX;
		EPWM->CMPBR2=(0xA5<<24)|Load_PCMPBRX;
	}
}
     ea8:	1481      	pop      	r4
	else if(EPWM_CNTRX_Selected==EPWM_CNTR1)
     eaa:	3841      	cmpnei      	r0, 1
     eac:	080c      	bt      	0xec4	// ec4 <EPWM_Set_CNTRX_CMPARX_CMPBRX+0x36>
		EPWM->CNTR1=(0xA5<<24)|Load_PCNTRX;
     eae:	101a      	lrw      	r0, 0x2000001c	// f14 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x36>
     eb0:	9080      	ld.w      	r4, (r0, 0)
     eb2:	30a5      	movi      	r0, 165
     eb4:	4018      	lsli      	r0, r0, 24
     eb6:	6c40      	or      	r1, r0
		EPWM->CMPAR1=(0xA5<<24)|Load_PCMPARX;
     eb8:	6c80      	or      	r2, r0
		EPWM->CMPBR1=(0xA5<<24)|Load_PCMPBRX;
     eba:	6c0c      	or      	r0, r3
		EPWM->CNTR1=(0xA5<<24)|Load_PCNTRX;
     ebc:	b427      	st.w      	r1, (r4, 0x1c)
		EPWM->CMPAR1=(0xA5<<24)|Load_PCMPARX;
     ebe:	b455      	st.w      	r2, (r4, 0x54)
		EPWM->CMPBR1=(0xA5<<24)|Load_PCMPBRX;
     ec0:	b418      	st.w      	r0, (r4, 0x60)
     ec2:	07f3      	br      	0xea8	// ea8 <EPWM_Set_CNTRX_CMPARX_CMPBRX+0x1a>
	else if(EPWM_CNTRX_Selected==EPWM_CNTR2)
     ec4:	3842      	cmpnei      	r0, 2
     ec6:	0bf1      	bt      	0xea8	// ea8 <EPWM_Set_CNTRX_CMPARX_CMPBRX+0x1a>
		EPWM->CNTR2=(0xA5<<24)|Load_PCNTRX;
     ec8:	1013      	lrw      	r0, 0x2000001c	// f14 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x36>
     eca:	9080      	ld.w      	r4, (r0, 0)
     ecc:	30a5      	movi      	r0, 165
     ece:	4018      	lsli      	r0, r0, 24
     ed0:	6c40      	or      	r1, r0
		EPWM->CMPAR2=(0xA5<<24)|Load_PCMPARX;
     ed2:	6c80      	or      	r2, r0
		EPWM->CMPBR2=(0xA5<<24)|Load_PCMPBRX;
     ed4:	6c0c      	or      	r0, r3
		EPWM->CNTR2=(0xA5<<24)|Load_PCNTRX;
     ed6:	b42b      	st.w      	r1, (r4, 0x2c)
		EPWM->CMPAR2=(0xA5<<24)|Load_PCMPARX;
     ed8:	b45b      	st.w      	r2, (r4, 0x6c)
		EPWM->CMPBR2=(0xA5<<24)|Load_PCMPBRX;
     eda:	b41e      	st.w      	r0, (r4, 0x78)
}
     edc:	07e6      	br      	0xea8	// ea8 <EPWM_Set_CNTRX_CMPARX_CMPBRX+0x1a>

00000ede <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX>:
//Load_SLPCMPARX:0~0xffff
//Load_SLPCMPBRX:0~0xffff
//ReturnValue:NOE
/*************************************************************/ 
void EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX(EPWM_CNTRX_Selected_TypeDef EPWM_SLPCNTRX_Selected , U16_T Load_SLPCNTRX , U16_T Load_SLPCMPARX , U16_T Load_SLPCMPBRX )
{
     ede:	14c2      	push      	r4-r5
	if(EPWM_SLPCNTRX_Selected==EPWM_SLPCNTR0)
     ee0:	3843      	cmpnei      	r0, 3
     ee2:	080c      	bt      	0xefa	// efa <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x1c>
	{
		EPWM->SLPCNTR0=(0xA5<<24)|Load_SLPCNTRX;
     ee4:	100c      	lrw      	r0, 0x2000001c	// f14 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x36>
     ee6:	9080      	ld.w      	r4, (r0, 0)
     ee8:	30a5      	movi      	r0, 165
     eea:	4018      	lsli      	r0, r0, 24
     eec:	6c40      	or      	r1, r0
		EPWM->SLPCMPAR0=(0xA5<<24)|Load_SLPCMPARX;
     eee:	6c80      	or      	r2, r0
		EPWM->SLPCMPBR0=(0xA5<<24)|Load_SLPCMPBRX;
     ef0:	6c0c      	or      	r0, r3
		EPWM->SLPCNTR0=(0xA5<<24)|Load_SLPCNTRX;
     ef2:	b426      	st.w      	r1, (r4, 0x18)
		EPWM->SLPCMPAR0=(0xA5<<24)|Load_SLPCMPARX;
     ef4:	b451      	st.w      	r2, (r4, 0x44)
		EPWM->SLPCMPBR0=(0xA5<<24)|Load_SLPCMPBRX;
     ef6:	b414      	st.w      	r0, (r4, 0x50)
	{
		EPWM->SLPCNTR1=(0xA5<<24)|Load_SLPCNTRX;
		EPWM->SLPCMPAR1=(0xA5<<24)|Load_SLPCMPARX;
		EPWM->SLPCMPBR1=(0xA5<<24)|Load_SLPCMPBRX;
	}
}
     ef8:	1482      	pop      	r4-r5
	else if(EPWM_SLPCNTRX_Selected==EPWM_SLPCNTR1)
     efa:	3844      	cmpnei      	r0, 4
     efc:	0bfe      	bt      	0xef8	// ef8 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x1a>
		EPWM->SLPCNTR1=(0xA5<<24)|Load_SLPCNTRX;
     efe:	34a5      	movi      	r4, 165
     f00:	4498      	lsli      	r4, r4, 24
     f02:	1005      	lrw      	r0, 0x2000001c	// f14 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x36>
     f04:	6c50      	or      	r1, r4
     f06:	90a0      	ld.w      	r5, (r0, 0)
		EPWM->SLPCMPAR1=(0xA5<<24)|Load_SLPCMPARX;
     f08:	6c90      	or      	r2, r4
		EPWM->SLPCMPBR1=(0xA5<<24)|Load_SLPCMPBRX;
     f0a:	6cd0      	or      	r3, r4
		EPWM->SLPCNTR1=(0xA5<<24)|Load_SLPCNTRX;
     f0c:	b52a      	st.w      	r1, (r5, 0x28)
		EPWM->SLPCMPAR1=(0xA5<<24)|Load_SLPCMPARX;
     f0e:	b557      	st.w      	r2, (r5, 0x5c)
		EPWM->SLPCMPBR1=(0xA5<<24)|Load_SLPCMPBRX;
     f10:	b57a      	st.w      	r3, (r5, 0x68)
     f12:	0407      	br      	0xf20	// f20 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x42>
     f14:	2000001c 	.long	0x2000001c
     f18:	000ffc00 	.long	0x000ffc00
     f1c:	000003ff 	.long	0x000003ff
}
     f20:	07ec      	br      	0xef8	// ef8 <EPWM_Set_SLPCNTRX_SLPCMPARX_SLPCMPBRX+0x1a>

00000f22 <EPWM_software_reset>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void EPWM_software_reset(void)
{
	EPWM->CR = EPWM->CR | S_RST;									// Reset PWM
     f22:	127e      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
     f24:	9340      	ld.w      	r2, (r3, 0)
     f26:	9260      	ld.w      	r3, (r2, 0)
     f28:	3ba2      	bseti      	r3, r3, 2
     f2a:	b260      	st.w      	r3, (r2, 0)
}
     f2c:	783c      	rts

00000f2e <EPWM_AllConter_START>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void EPWM_AllConter_START(void)
{
	EPWM->CR = EPWM->CR | PWMSTART;									// Start PWM
     f2e:	127b      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
     f30:	9340      	ld.w      	r2, (r3, 0)
     f32:	9260      	ld.w      	r3, (r2, 0)
     f34:	3ba0      	bseti      	r3, r3, 0
     f36:	b260      	st.w      	r3, (r2, 0)
}
     f38:	783c      	rts

00000f3a <EPWM_Conter0_START>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void EPWM_Conter0_START(void)
{
	EPWM->CR = EPWM->CR | PWM0START;									// Start PWM0
     f3a:	1278      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
     f3c:	9340      	ld.w      	r2, (r3, 0)
     f3e:	9260      	ld.w      	r3, (r2, 0)
     f40:	3bb8      	bseti      	r3, r3, 24
     f42:	b260      	st.w      	r3, (r2, 0)
}
     f44:	783c      	rts

00000f46 <EPWM_Conter1_START>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void EPWM_Conter1_START(void)
{
	EPWM->CR = EPWM->CR | PWM1START;									// Start PWM1
     f46:	1275      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
     f48:	9340      	ld.w      	r2, (r3, 0)
     f4a:	9260      	ld.w      	r3, (r2, 0)
     f4c:	3bb9      	bseti      	r3, r3, 25
     f4e:	b260      	st.w      	r3, (r2, 0)
}
     f50:	783c      	rts

00000f52 <EPWM_Conter2_START>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void EPWM_Conter2_START(void)
{
	EPWM->CR = EPWM->CR | PWM2START;									// Start PWM2
     f52:	1272      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
     f54:	9340      	ld.w      	r2, (r3, 0)
     f56:	9260      	ld.w      	r3, (r2, 0)
     f58:	3bba      	bseti      	r3, r3, 26
     f5a:	b260      	st.w      	r3, (r2, 0)
}
     f5c:	783c      	rts

00000f5e <EPWM_AllConter_stop>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void EPWM_AllConter_stop(void)
{
	EPWM->CR = EPWM->CR | PWMSTOP;									// stop PWM
     f5e:	126f      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
	while( (EPWM->CR & BUSY) == BUSY );					// Check if the PWM is busy
     f60:	3280      	movi      	r2, 128
	EPWM->CR = EPWM->CR | PWMSTOP;									// stop PWM
     f62:	9320      	ld.w      	r1, (r3, 0)
     f64:	9160      	ld.w      	r3, (r1, 0)
     f66:	3ba1      	bseti      	r3, r3, 1
     f68:	b160      	st.w      	r3, (r1, 0)
	while( (EPWM->CR & BUSY) == BUSY );					// Check if the PWM is busy
     f6a:	424d      	lsli      	r2, r2, 13
     f6c:	9160      	ld.w      	r3, (r1, 0)
     f6e:	68c8      	and      	r3, r2
     f70:	3b40      	cmpnei      	r3, 0
     f72:	0bfd      	bt      	0xf6c	// f6c <EPWM_AllConter_stop+0xe>
}
     f74:	783c      	rts

00000f76 <EPWM_Conter0_STOP>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void EPWM_Conter0_STOP(void)
{
	EPWM->CR = EPWM->CR | PWM0STOP;									// Stop PWM0
     f76:	1269      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
	while( (EPWM->RISR & EPWM_STOP0)!=EPWM_STOP0 );					// Check if the PWM0 stop complete
     f78:	3102      	movi      	r1, 2
	EPWM->CR = EPWM->CR | PWM0STOP;									// Stop PWM0
     f7a:	9360      	ld.w      	r3, (r3, 0)
     f7c:	9340      	ld.w      	r2, (r3, 0)
     f7e:	3abb      	bseti      	r2, r2, 27
     f80:	b340      	st.w      	r2, (r3, 0)
	while( (EPWM->RISR & EPWM_STOP0)!=EPWM_STOP0 );					// Check if the PWM0 stop complete
     f82:	237f      	addi      	r3, 128
     f84:	9350      	ld.w      	r2, (r3, 0x40)
     f86:	6884      	and      	r2, r1
     f88:	3a40      	cmpnei      	r2, 0
     f8a:	0ffd      	bf      	0xf84	// f84 <EPWM_Conter0_STOP+0xe>
}
     f8c:	783c      	rts

00000f8e <EPWM_Conter1_STOP>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void EPWM_Conter1_STOP(void)
{
	EPWM->CR = EPWM->CR | PWM1STOP;									// Stop PWM1
     f8e:	1263      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
	while( (EPWM->RISR & EPWM_STOP1)!=EPWM_STOP1 );					// Check if the PWM1 stop complete
     f90:	3120      	movi      	r1, 32
	EPWM->CR = EPWM->CR | PWM1STOP;									// Stop PWM1
     f92:	9360      	ld.w      	r3, (r3, 0)
     f94:	9340      	ld.w      	r2, (r3, 0)
     f96:	3abc      	bseti      	r2, r2, 28
     f98:	b340      	st.w      	r2, (r3, 0)
	while( (EPWM->RISR & EPWM_STOP1)!=EPWM_STOP1 );					// Check if the PWM1 stop complete
     f9a:	237f      	addi      	r3, 128
     f9c:	9350      	ld.w      	r2, (r3, 0x40)
     f9e:	6884      	and      	r2, r1
     fa0:	3a40      	cmpnei      	r2, 0
     fa2:	0ffd      	bf      	0xf9c	// f9c <EPWM_Conter1_STOP+0xe>
}
     fa4:	783c      	rts

00000fa6 <EPWM_Conter2_STOP>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void EPWM_Conter2_STOP(void)
{
	EPWM->CR = EPWM->CR | PWM2STOP;									// Stop PWM2
     fa6:	117d      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
	while( (EPWM->RISR & EPWM_STOP2)!=EPWM_STOP2 );					// Check if the PWM2 stop complete
     fa8:	3180      	movi      	r1, 128
	EPWM->CR = EPWM->CR | PWM2STOP;									// Stop PWM2
     faa:	9360      	ld.w      	r3, (r3, 0)
     fac:	9340      	ld.w      	r2, (r3, 0)
     fae:	3abd      	bseti      	r2, r2, 29
     fb0:	b340      	st.w      	r2, (r3, 0)
	while( (EPWM->RISR & EPWM_STOP2)!=EPWM_STOP2 );					// Check if the PWM2 stop complete
     fb2:	4122      	lsli      	r1, r1, 2
     fb4:	237f      	addi      	r3, 128
     fb6:	9350      	ld.w      	r2, (r3, 0x40)
     fb8:	6884      	and      	r2, r1
     fba:	3a40      	cmpnei      	r2, 0
     fbc:	0ffd      	bf      	0xfb6	// fb6 <EPWM_Conter2_STOP+0x10>
}
     fbe:	783c      	rts

00000fc0 <EPWM_ConfigInterrupt_CMD>:
//EPWM0_SLPA_OVF,EPWM0_SLPB_OVF,EPWM1_SLPA_OVF,EPWM1_SLPB_OVF
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void EPWM_ConfigInterrupt_CMD(EPWM_INT_TypeDef EPWM_INT_X , FunctionalStatus NewState)
{
     fc0:	1176      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
	if (NewState != DISABLE)
     fc2:	3940      	cmpnei      	r1, 0
	{
		EPWM->IER  |= EPWM_INT_X;						//SET
     fc4:	9360      	ld.w      	r3, (r3, 0)
     fc6:	237f      	addi      	r3, 128
     fc8:	934e      	ld.w      	r2, (r3, 0x38)
	if (NewState != DISABLE)
     fca:	0c04      	bf      	0xfd2	// fd2 <EPWM_ConfigInterrupt_CMD+0x12>
		EPWM->IER  |= EPWM_INT_X;						//SET
     fcc:	6c08      	or      	r0, r2
	}
	else
	{
		EPWM->IER  &= ~EPWM_INT_X;						//CLR
     fce:	b30e      	st.w      	r0, (r3, 0x38)
	}
}
     fd0:	783c      	rts
		EPWM->IER  &= ~EPWM_INT_X;						//CLR
     fd2:	6c02      	nor      	r0, r0
     fd4:	6808      	and      	r0, r2
     fd6:	07fc      	br      	0xfce	// fce <EPWM_ConfigInterrupt_CMD+0xe>

00000fd8 <EPWM_Carrier_Wave_CMD>:
//ReturnValue:NONE
/*************************************************************/ 
//CarrierWave_Duty_time=OSW_time*(PCLK/CDIV)*8
void EPWM_Carrier_Wave_CMD(EPWM_PWM_XxOrPWM_Yx_TypeDef EPWM_PWM_XxOrPWM_Yx , EPWM_Carrier_Wave_Duty_TypeDef EPWM_Carrier_Wave_Duty_X ,
					EPWM_CDIV_TypeDef EPWM_CDIV_X , U8_T OSW_time , FunctionalStatus NewState)
{
     fd8:	14c2      	push      	r4-r5
	if(EPWM_PWM_XxOrPWM_Yx==EPWM_PWM_X0OrPWM_Y0)
     fda:	3840      	cmpnei      	r0, 0
{
     fdc:	9882      	ld.w      	r4, (sp, 0x8)
	if(EPWM_PWM_XxOrPWM_Yx==EPWM_PWM_X0OrPWM_Y0)
     fde:	0810      	bt      	0xffe	// ffe <EPWM_Carrier_Wave_CMD+0x26>
	{
		EPWM->CFCR0=EPWM_Carrier_Wave_Duty_X|EPWM_CDIV_X|(OSW_time<<4);
     fe0:	110e      	lrw      	r0, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
     fe2:	4364      	lsli      	r3, r3, 4
     fe4:	9000      	ld.w      	r0, (r0, 0)
     fe6:	6c84      	or      	r2, r1
     fe8:	6c8c      	or      	r2, r3
     fea:	207f      	addi      	r0, 128
     fec:	b047      	st.w      	r2, (r0, 0x1c)
		if (NewState != DISABLE)
     fee:	3c40      	cmpnei      	r4, 0
		{
			EPWM->CFCR0  |= 0x01;						//SET
     ff0:	9067      	ld.w      	r3, (r0, 0x1c)
		if (NewState != DISABLE)
     ff2:	0c04      	bf      	0xffa	// ffa <EPWM_Carrier_Wave_CMD+0x22>
			EPWM->CFCR0  |= 0x01;						//SET
     ff4:	3ba0      	bseti      	r3, r3, 0
		}
		else
		{
			EPWM->CFCR0  &= 0xfffffffe;					//CLR
     ff6:	b067      	st.w      	r3, (r0, 0x1c)
		else
		{
			EPWM->CFCR2  &= 0xfffffffe;					//CLR
		}
	}
}
     ff8:	1482      	pop      	r4-r5
			EPWM->CFCR0  &= 0xfffffffe;					//CLR
     ffa:	3b80      	bclri      	r3, r3, 0
     ffc:	07fd      	br      	0xff6	// ff6 <EPWM_Carrier_Wave_CMD+0x1e>
	else if(EPWM_PWM_XxOrPWM_Yx==EPWM_PWM_X1OrPWM_Y1)
     ffe:	3841      	cmpnei      	r0, 1
    1000:	0811      	bt      	0x1022	// 1022 <EPWM_Carrier_Wave_CMD+0x4a>
		EPWM->CFCR1=EPWM_Carrier_Wave_Duty_X|EPWM_CDIV_X|(OSW_time<<4);
    1002:	11a6      	lrw      	r5, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
    1004:	4364      	lsli      	r3, r3, 4
    1006:	95a0      	ld.w      	r5, (r5, 0)
    1008:	6c84      	or      	r2, r1
    100a:	6c8c      	or      	r2, r3
    100c:	257f      	addi      	r5, 128
    100e:	b548      	st.w      	r2, (r5, 0x20)
		if (NewState != DISABLE)
    1010:	3c40      	cmpnei      	r4, 0
			EPWM->CFCR1  |= 0x01;						//SET
    1012:	9568      	ld.w      	r3, (r5, 0x20)
		if (NewState != DISABLE)
    1014:	0c04      	bf      	0x101c	// 101c <EPWM_Carrier_Wave_CMD+0x44>
			EPWM->CFCR1  |= 0x01;						//SET
    1016:	6c0c      	or      	r0, r3
    1018:	b508      	st.w      	r0, (r5, 0x20)
    101a:	07ef      	br      	0xff8	// ff8 <EPWM_Carrier_Wave_CMD+0x20>
			EPWM->CFCR1  &= 0xfffffffe;					//CLR
    101c:	3b80      	bclri      	r3, r3, 0
    101e:	b568      	st.w      	r3, (r5, 0x20)
    1020:	07ec      	br      	0xff8	// ff8 <EPWM_Carrier_Wave_CMD+0x20>
	else if(EPWM_PWM_XxOrPWM_Yx==EPWM_PWM_X2OrPWM_Y2)
    1022:	3842      	cmpnei      	r0, 2
    1024:	0bea      	bt      	0xff8	// ff8 <EPWM_Carrier_Wave_CMD+0x20>
		EPWM->CFCR2|=EPWM_Carrier_Wave_Duty_X|EPWM_CDIV_X|(OSW_time<<4);
    1026:	101d      	lrw      	r0, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
    1028:	4364      	lsli      	r3, r3, 4
    102a:	9000      	ld.w      	r0, (r0, 0)
    102c:	207f      	addi      	r0, 128
    102e:	90a9      	ld.w      	r5, (r0, 0x24)
    1030:	6c94      	or      	r2, r5
    1032:	6c84      	or      	r2, r1
    1034:	6c8c      	or      	r2, r3
    1036:	b049      	st.w      	r2, (r0, 0x24)
		if (NewState != DISABLE)
    1038:	3c40      	cmpnei      	r4, 0
			EPWM->CFCR2  |= 0x01;						//SET
    103a:	9069      	ld.w      	r3, (r0, 0x24)
		if (NewState != DISABLE)
    103c:	0c04      	bf      	0x1044	// 1044 <EPWM_Carrier_Wave_CMD+0x6c>
			EPWM->CFCR2  |= 0x01;						//SET
    103e:	3ba0      	bseti      	r3, r3, 0
			EPWM->CFCR2  &= 0xfffffffe;					//CLR
    1040:	b069      	st.w      	r3, (r0, 0x24)
}
    1042:	07db      	br      	0xff8	// ff8 <EPWM_Carrier_Wave_CMD+0x20>
			EPWM->CFCR2  &= 0xfffffffe;					//CLR
    1044:	3b80      	bclri      	r3, r3, 0
    1046:	07fd      	br      	0x1040	// 1040 <EPWM_Carrier_Wave_CMD+0x68>

00001048 <EPWM_LKCR_TRG_Configure>:
//10：选择为软锁止的触发源
//11：选择为硬锁止的触发源
//IVT = TRGIVT x 4 x Tpwmclk  ; TDL = (TRGTDL+1) x 4 x Tpwmclk 
void EPWM_LKCR_TRG_Configure(EPWM_Triggle_Source_TypeDef EPWM_Triggle_Source_X , U8_T EPWM_LK_mode_selected)
{
	if(EPWM_Triggle_Source_X==CMP0LKM)
    1048:	3841      	cmpnei      	r0, 1
    104a:	080b      	bt      	0x1060	// 1060 <EPWM_LKCR_TRG_Configure+0x18>
	{
		EPWM->LKCR&=0XFFFFFFF8;
    104c:	1073      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
    104e:	3007      	movi      	r0, 7
    1050:	9360      	ld.w      	r3, (r3, 0)
    1052:	9341      	ld.w      	r2, (r3, 0x4)
    1054:	6881      	andn      	r2, r0
    1056:	b341      	st.w      	r2, (r3, 0x4)
		EPWM->LKCR|=EPWM_LK_mode_selected;
    1058:	9341      	ld.w      	r2, (r3, 0x4)
		EPWM->LKCR|=EPWM_LK_mode_selected<<18;
	}
	else if(EPWM_Triggle_Source_X==EXI3LKM)
	{
		EPWM->LKCR&=0XFF1FFFFF;
		EPWM->LKCR|=EPWM_LK_mode_selected<<21;
    105a:	6c48      	or      	r1, r2
    105c:	b321      	st.w      	r1, (r3, 0x4)
	else if(EPWM_Triggle_Source_X==EXI7LKM)
	{
		EPWM->LKCR&=0X3FFFFFFF;
		EPWM->LKCR|=EPWM_LK_mode_selected<<30;
	}*/
}
    105e:	783c      	rts
	else if(EPWM_Triggle_Source_X==CMP1LKM)
    1060:	3842      	cmpnei      	r0, 2
    1062:	080a      	bt      	0x1076	// 1076 <EPWM_LKCR_TRG_Configure+0x2e>
		EPWM->LKCR&=0XFFFFFFC7;
    1064:	106d      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
    1066:	3038      	movi      	r0, 56
    1068:	9360      	ld.w      	r3, (r3, 0)
    106a:	9341      	ld.w      	r2, (r3, 0x4)
    106c:	6881      	andn      	r2, r0
    106e:	b341      	st.w      	r2, (r3, 0x4)
		EPWM->LKCR|=EPWM_LK_mode_selected<<3;
    1070:	9341      	ld.w      	r2, (r3, 0x4)
    1072:	4123      	lsli      	r1, r1, 3
    1074:	07f3      	br      	0x105a	// 105a <EPWM_LKCR_TRG_Configure+0x12>
	else if(EPWM_Triggle_Source_X==CMP2LKM)
    1076:	3843      	cmpnei      	r0, 3
    1078:	080a      	bt      	0x108c	// 108c <EPWM_LKCR_TRG_Configure+0x44>
		EPWM->LKCR&=0XFFFFFF3F;
    107a:	1068      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
		EPWM->LKCR|=EPWM_LK_mode_selected<<6;
    107c:	4126      	lsli      	r1, r1, 6
		EPWM->LKCR&=0XFFFFFF3F;
    107e:	9360      	ld.w      	r3, (r3, 0)
    1080:	9341      	ld.w      	r2, (r3, 0x4)
    1082:	3a86      	bclri      	r2, r2, 6
    1084:	3a87      	bclri      	r2, r2, 7
    1086:	b341      	st.w      	r2, (r3, 0x4)
		EPWM->LKCR|=EPWM_LK_mode_selected<<6;
    1088:	9341      	ld.w      	r2, (r3, 0x4)
    108a:	07e8      	br      	0x105a	// 105a <EPWM_LKCR_TRG_Configure+0x12>
	else if(EPWM_Triggle_Source_X==CMP3LKM)
    108c:	3844      	cmpnei      	r0, 4
    108e:	080e      	bt      	0x10aa	// 10aa <EPWM_LKCR_TRG_Configure+0x62>
		EPWM->LKCR&=0XFFFFFCFF;
    1090:	1062      	lrw      	r3, 0x2000001c	// 1098 <EPWM_LKCR_TRG_Configure+0x50>
		EPWM->LKCR|=EPWM_LK_mode_selected<<8;
    1092:	4128      	lsli      	r1, r1, 8
    1094:	0404      	br      	0x109c	// 109c <EPWM_LKCR_TRG_Configure+0x54>
    1096:	0000      	bkpt
    1098:	2000001c 	.long	0x2000001c
		EPWM->LKCR&=0XFFFFFCFF;
    109c:	9360      	ld.w      	r3, (r3, 0)
    109e:	9341      	ld.w      	r2, (r3, 0x4)
    10a0:	3a88      	bclri      	r2, r2, 8
    10a2:	3a89      	bclri      	r2, r2, 9
    10a4:	b341      	st.w      	r2, (r3, 0x4)
		EPWM->LKCR|=EPWM_LK_mode_selected<<8;
    10a6:	9341      	ld.w      	r2, (r3, 0x4)
    10a8:	07d9      	br      	0x105a	// 105a <EPWM_LKCR_TRG_Configure+0x12>
	else if(EPWM_Triggle_Source_X==CMP4LKM)
    10aa:	3845      	cmpnei      	r0, 5
    10ac:	080a      	bt      	0x10c0	// 10c0 <EPWM_LKCR_TRG_Configure+0x78>
		EPWM->LKCR&=0XFFFFF3FF;
    10ae:	1366      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
		EPWM->LKCR|=EPWM_LK_mode_selected<<10;
    10b0:	412a      	lsli      	r1, r1, 10
		EPWM->LKCR&=0XFFFFF3FF;
    10b2:	9360      	ld.w      	r3, (r3, 0)
    10b4:	9341      	ld.w      	r2, (r3, 0x4)
    10b6:	3a8a      	bclri      	r2, r2, 10
    10b8:	3a8b      	bclri      	r2, r2, 11
    10ba:	b341      	st.w      	r2, (r3, 0x4)
		EPWM->LKCR|=EPWM_LK_mode_selected<<10;
    10bc:	9341      	ld.w      	r2, (r3, 0x4)
    10be:	07ce      	br      	0x105a	// 105a <EPWM_LKCR_TRG_Configure+0x12>
	else if(EPWM_Triggle_Source_X==EXI0LKM)
    10c0:	3846      	cmpnei      	r0, 6
    10c2:	080b      	bt      	0x10d8	// 10d8 <EPWM_LKCR_TRG_Configure+0x90>
		EPWM->LKCR&=0XFFFF8FFF;
    10c4:	1360      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
    10c6:	30e0      	movi      	r0, 224
    10c8:	9360      	ld.w      	r3, (r3, 0)
    10ca:	9341      	ld.w      	r2, (r3, 0x4)
    10cc:	4007      	lsli      	r0, r0, 7
    10ce:	6881      	andn      	r2, r0
    10d0:	b341      	st.w      	r2, (r3, 0x4)
		EPWM->LKCR|=EPWM_LK_mode_selected<<12;
    10d2:	9341      	ld.w      	r2, (r3, 0x4)
    10d4:	412c      	lsli      	r1, r1, 12
    10d6:	07c2      	br      	0x105a	// 105a <EPWM_LKCR_TRG_Configure+0x12>
	else if(EPWM_Triggle_Source_X==EXI1LKM)
    10d8:	3847      	cmpnei      	r0, 7
    10da:	080b      	bt      	0x10f0	// 10f0 <EPWM_LKCR_TRG_Configure+0xa8>
		EPWM->LKCR&=0XFFFC7FFF;
    10dc:	127a      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
    10de:	30e0      	movi      	r0, 224
    10e0:	9360      	ld.w      	r3, (r3, 0)
    10e2:	9341      	ld.w      	r2, (r3, 0x4)
    10e4:	400a      	lsli      	r0, r0, 10
    10e6:	6881      	andn      	r2, r0
    10e8:	b341      	st.w      	r2, (r3, 0x4)
		EPWM->LKCR|=EPWM_LK_mode_selected<<15;
    10ea:	9341      	ld.w      	r2, (r3, 0x4)
    10ec:	412f      	lsli      	r1, r1, 15
    10ee:	07b6      	br      	0x105a	// 105a <EPWM_LKCR_TRG_Configure+0x12>
	else if(EPWM_Triggle_Source_X==EXI2LKM)
    10f0:	3848      	cmpnei      	r0, 8
    10f2:	080b      	bt      	0x1108	// 1108 <EPWM_LKCR_TRG_Configure+0xc0>
		EPWM->LKCR&=0XFFE3FFFF;
    10f4:	1274      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
    10f6:	30e0      	movi      	r0, 224
    10f8:	9360      	ld.w      	r3, (r3, 0)
    10fa:	9341      	ld.w      	r2, (r3, 0x4)
    10fc:	400d      	lsli      	r0, r0, 13
    10fe:	6881      	andn      	r2, r0
    1100:	b341      	st.w      	r2, (r3, 0x4)
		EPWM->LKCR|=EPWM_LK_mode_selected<<18;
    1102:	9341      	ld.w      	r2, (r3, 0x4)
    1104:	4132      	lsli      	r1, r1, 18
    1106:	07aa      	br      	0x105a	// 105a <EPWM_LKCR_TRG_Configure+0x12>
	else if(EPWM_Triggle_Source_X==EXI3LKM)
    1108:	3849      	cmpnei      	r0, 9
    110a:	0baa      	bt      	0x105e	// 105e <EPWM_LKCR_TRG_Configure+0x16>
		EPWM->LKCR&=0XFF1FFFFF;
    110c:	126e      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
    110e:	30e0      	movi      	r0, 224
    1110:	9360      	ld.w      	r3, (r3, 0)
    1112:	9341      	ld.w      	r2, (r3, 0x4)
    1114:	4010      	lsli      	r0, r0, 16
    1116:	6881      	andn      	r2, r0
    1118:	b341      	st.w      	r2, (r3, 0x4)
		EPWM->LKCR|=EPWM_LK_mode_selected<<21;
    111a:	9341      	ld.w      	r2, (r3, 0x4)
    111c:	4135      	lsli      	r1, r1, 21
    111e:	079e      	br      	0x105a	// 105a <EPWM_LKCR_TRG_Configure+0x12>

00001120 <EPWM_TrgivtAndTrgtdl_Set_Configure>:
//EPWM_TRGIVT:0~255
//ReturnValue:NONE
/*************************************************************/
void EPWM_TrgivtAndTrgtdl_Set_Configure(U8_T EPWM_TRGTDL , U8_T EPWM_TRGIVT)
{
	EPWM->LKTRG = (0XA5<<24) | (EPWM_TRGTDL<<8) | EPWM_TRGIVT;
    1120:	1269      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
    1122:	4008      	lsli      	r0, r0, 8
    1124:	9340      	ld.w      	r2, (r3, 0)
    1126:	33a5      	movi      	r3, 165
    1128:	4378      	lsli      	r3, r3, 24
    112a:	6c4c      	or      	r1, r3
    112c:	6c04      	or      	r0, r1
    112e:	b202      	st.w      	r0, (r2, 0x8)
}
    1130:	783c      	rts

00001132 <EPWM_Software_Clr>:
//EPWM Software clr
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPWM_Software_Clr(void)
{
    1132:	14c1      	push      	r4
	R_EPWM_EMR_ST=EPWM->EMR&0XFFFFFFFC;
    1134:	1264      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
	if(EPWM->EMR&0x02)
    1136:	3402      	movi      	r4, 2
	R_EPWM_EMR_ST=EPWM->EMR&0XFFFFFFFC;
    1138:	9340      	ld.w      	r2, (r3, 0)
    113a:	227f      	addi      	r2, 128
    113c:	922a      	ld.w      	r1, (r2, 0x28)
    113e:	3980      	bclri      	r1, r1, 0
    1140:	3981      	bclri      	r1, r1, 1
    1142:	1262      	lrw      	r3, 0x2000007c	// 1248 <EPWM_SoftHardWare_OUTPUT_Configure+0xc0>
    1144:	b320      	st.w      	r1, (r3, 0)
	if(EPWM->EMR&0x02)
    1146:	920a      	ld.w      	r0, (r2, 0x28)
    1148:	6810      	and      	r0, r4
    114a:	3840      	cmpnei      	r0, 0
    114c:	0c04      	bf      	0x1154	// 1154 <EPWM_Software_Clr+0x22>
	{
		R_EPWM_EMR_ST|=0x02;
    114e:	9320      	ld.w      	r1, (r3, 0)
    1150:	6c50      	or      	r1, r4
    1152:	b320      	st.w      	r1, (r3, 0)
	}
	EPWM->EMR=R_EPWM_EMR_ST;
    1154:	9360      	ld.w      	r3, (r3, 0)
    1156:	b26a      	st.w      	r3, (r2, 0x28)
}
    1158:	1481      	pop      	r4

0000115a <EPWM_Hardware_Clr>:
//EPWM Hardware clr
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPWM_Hardware_Clr(void)
{
    115a:	14c1      	push      	r4
	R_EPWM_EMR_ST=EPWM->EMR&0XFFFFFFFC;
    115c:	117a      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
    115e:	115b      	lrw      	r2, 0x2000007c	// 1248 <EPWM_SoftHardWare_OUTPUT_Configure+0xc0>
	if(EPWM->EMR&0x01)
    1160:	3401      	movi      	r4, 1
	R_EPWM_EMR_ST=EPWM->EMR&0XFFFFFFFC;
    1162:	9360      	ld.w      	r3, (r3, 0)
    1164:	237f      	addi      	r3, 128
    1166:	932a      	ld.w      	r1, (r3, 0x28)
    1168:	3980      	bclri      	r1, r1, 0
    116a:	3981      	bclri      	r1, r1, 1
    116c:	b220      	st.w      	r1, (r2, 0)
	if(EPWM->EMR&0x01)
    116e:	930a      	ld.w      	r0, (r3, 0x28)
    1170:	6810      	and      	r0, r4
    1172:	3840      	cmpnei      	r0, 0
    1174:	0c04      	bf      	0x117c	// 117c <EPWM_Hardware_Clr+0x22>
	{
		R_EPWM_EMR_ST|=0x01;
    1176:	9220      	ld.w      	r1, (r2, 0)
    1178:	6c50      	or      	r1, r4
    117a:	b220      	st.w      	r1, (r2, 0)
	}
	EPWM->EMR=R_EPWM_EMR_ST;
    117c:	9240      	ld.w      	r2, (r2, 0)
    117e:	b34a      	st.w      	r2, (r3, 0x28)
	
	EPWM->EMR|=0x01;
    1180:	934a      	ld.w      	r2, (r3, 0x28)
    1182:	3aa0      	bseti      	r2, r2, 0
    1184:	b34a      	st.w      	r2, (r3, 0x28)
}
    1186:	1481      	pop      	r4

00001188 <EPWM_SoftHardWare_OUTPUT_Configure>:
//EPWM_LK_output_X:EPWM_LK_output_LOW,EPWM_LK_output_High,EPWM_LK_output_OP,EPWM_LK_output_keep
//ReturnValue:NONE
/*************************************************************/
void EPWM_SoftHardWare_OUTPUT_Configure(EPWM_LK_output_Select_TypeDef EPWM_LK_output_Select_X , EPWM_LK_output_TypeDef EPWM_LK_output_X)
{
	if(EPWM_LK_output_Select_X==EPWM_LK_output_HLP0XS)
    1188:	3841      	cmpnei      	r0, 1
    118a:	080d      	bt      	0x11a4	// 11a4 <EPWM_SoftHardWare_OUTPUT_Configure+0x1c>
	{
		EPWM->EMR&=0XFFFFFFF3;
    118c:	116e      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
		EPWM->EMR|=EPWM_LK_output_X<<2;
    118e:	4122      	lsli      	r1, r1, 2
		EPWM->EMR&=0XFFFFFFF3;
    1190:	9360      	ld.w      	r3, (r3, 0)
    1192:	237f      	addi      	r3, 128
    1194:	934a      	ld.w      	r2, (r3, 0x28)
    1196:	3a82      	bclri      	r2, r2, 2
    1198:	3a83      	bclri      	r2, r2, 3
    119a:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<2;
    119c:	934a      	ld.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<22;
	}
	else if(EPWM_LK_output_Select_X==EPWM_LK_output_SLP2YS)
	{
		EPWM->EMR&=0XFCFFFFFF;
		EPWM->EMR|=EPWM_LK_output_X<<24;
    119e:	6c48      	or      	r1, r2
    11a0:	b32a      	st.w      	r1, (r3, 0x28)
	}
}
    11a2:	783c      	rts
	else if(EPWM_LK_output_Select_X==EPWM_LK_output_HLP0YS)
    11a4:	3842      	cmpnei      	r0, 2
    11a6:	080b      	bt      	0x11bc	// 11bc <EPWM_SoftHardWare_OUTPUT_Configure+0x34>
		EPWM->EMR&=0XFFFFFFCF;
    11a8:	1167      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
		EPWM->EMR|=EPWM_LK_output_X<<4;
    11aa:	4124      	lsli      	r1, r1, 4
		EPWM->EMR&=0XFFFFFFCF;
    11ac:	9360      	ld.w      	r3, (r3, 0)
    11ae:	237f      	addi      	r3, 128
    11b0:	934a      	ld.w      	r2, (r3, 0x28)
    11b2:	3a84      	bclri      	r2, r2, 4
    11b4:	3a85      	bclri      	r2, r2, 5
    11b6:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<4;
    11b8:	934a      	ld.w      	r2, (r3, 0x28)
    11ba:	07f2      	br      	0x119e	// 119e <EPWM_SoftHardWare_OUTPUT_Configure+0x16>
	else if(EPWM_LK_output_Select_X==EPWM_LK_output_SLP0XS)
    11bc:	3843      	cmpnei      	r0, 3
    11be:	080b      	bt      	0x11d4	// 11d4 <EPWM_SoftHardWare_OUTPUT_Configure+0x4c>
		EPWM->EMR&=0XFFFFFF3F;
    11c0:	1161      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
		EPWM->EMR|=EPWM_LK_output_X<<6;
    11c2:	4126      	lsli      	r1, r1, 6
		EPWM->EMR&=0XFFFFFF3F;
    11c4:	9360      	ld.w      	r3, (r3, 0)
    11c6:	237f      	addi      	r3, 128
    11c8:	934a      	ld.w      	r2, (r3, 0x28)
    11ca:	3a86      	bclri      	r2, r2, 6
    11cc:	3a87      	bclri      	r2, r2, 7
    11ce:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<6;
    11d0:	934a      	ld.w      	r2, (r3, 0x28)
    11d2:	07e6      	br      	0x119e	// 119e <EPWM_SoftHardWare_OUTPUT_Configure+0x16>
	else if(EPWM_LK_output_Select_X==EPWM_LK_output_SLP0YS)
    11d4:	3844      	cmpnei      	r0, 4
    11d6:	080b      	bt      	0x11ec	// 11ec <EPWM_SoftHardWare_OUTPUT_Configure+0x64>
		EPWM->EMR&=0XFFFFFCFF;
    11d8:	107b      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
		EPWM->EMR|=EPWM_LK_output_X<<8;
    11da:	4128      	lsli      	r1, r1, 8
		EPWM->EMR&=0XFFFFFCFF;
    11dc:	9360      	ld.w      	r3, (r3, 0)
    11de:	237f      	addi      	r3, 128
    11e0:	934a      	ld.w      	r2, (r3, 0x28)
    11e2:	3a88      	bclri      	r2, r2, 8
    11e4:	3a89      	bclri      	r2, r2, 9
    11e6:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<8;
    11e8:	934a      	ld.w      	r2, (r3, 0x28)
    11ea:	07da      	br      	0x119e	// 119e <EPWM_SoftHardWare_OUTPUT_Configure+0x16>
	else if(EPWM_LK_output_Select_X==EPWM_LK_output_HLP1XS)
    11ec:	3845      	cmpnei      	r0, 5
    11ee:	080b      	bt      	0x1204	// 1204 <EPWM_SoftHardWare_OUTPUT_Configure+0x7c>
		EPWM->EMR&=0XFFFFF3FF;
    11f0:	1075      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
		EPWM->EMR|=EPWM_LK_output_X<<10;
    11f2:	412a      	lsli      	r1, r1, 10
		EPWM->EMR&=0XFFFFF3FF;
    11f4:	9360      	ld.w      	r3, (r3, 0)
    11f6:	237f      	addi      	r3, 128
    11f8:	934a      	ld.w      	r2, (r3, 0x28)
    11fa:	3a8a      	bclri      	r2, r2, 10
    11fc:	3a8b      	bclri      	r2, r2, 11
    11fe:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<10;
    1200:	934a      	ld.w      	r2, (r3, 0x28)
    1202:	07ce      	br      	0x119e	// 119e <EPWM_SoftHardWare_OUTPUT_Configure+0x16>
	else if(EPWM_LK_output_Select_X==EPWM_LK_output_HLP1YS)
    1204:	3846      	cmpnei      	r0, 6
    1206:	080b      	bt      	0x121c	// 121c <EPWM_SoftHardWare_OUTPUT_Configure+0x94>
		EPWM->EMR&=0XFFFFCFFF;
    1208:	106f      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
		EPWM->EMR|=EPWM_LK_output_X<<12;
    120a:	412c      	lsli      	r1, r1, 12
		EPWM->EMR&=0XFFFFCFFF;
    120c:	9360      	ld.w      	r3, (r3, 0)
    120e:	237f      	addi      	r3, 128
    1210:	934a      	ld.w      	r2, (r3, 0x28)
    1212:	3a8c      	bclri      	r2, r2, 12
    1214:	3a8d      	bclri      	r2, r2, 13
    1216:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<12;
    1218:	934a      	ld.w      	r2, (r3, 0x28)
    121a:	07c2      	br      	0x119e	// 119e <EPWM_SoftHardWare_OUTPUT_Configure+0x16>
	else if(EPWM_LK_output_Select_X==EPWM_LK_output_SLP1XS)
    121c:	3847      	cmpnei      	r0, 7
    121e:	080b      	bt      	0x1234	// 1234 <EPWM_SoftHardWare_OUTPUT_Configure+0xac>
		EPWM->EMR&=0XFFFF3FFF;
    1220:	1069      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
		EPWM->EMR|=EPWM_LK_output_X<<14;
    1222:	412e      	lsli      	r1, r1, 14
		EPWM->EMR&=0XFFFF3FFF;
    1224:	9360      	ld.w      	r3, (r3, 0)
    1226:	237f      	addi      	r3, 128
    1228:	934a      	ld.w      	r2, (r3, 0x28)
    122a:	3a8e      	bclri      	r2, r2, 14
    122c:	3a8f      	bclri      	r2, r2, 15
    122e:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<14;
    1230:	934a      	ld.w      	r2, (r3, 0x28)
    1232:	07b6      	br      	0x119e	// 119e <EPWM_SoftHardWare_OUTPUT_Configure+0x16>
	else if(EPWM_LK_output_Select_X==EPWM_LK_output_SLP1YS)
    1234:	3848      	cmpnei      	r0, 8
    1236:	0811      	bt      	0x1258	// 1258 <EPWM_SoftHardWare_OUTPUT_Configure+0xd0>
		EPWM->EMR&=0XFFFCFFFF;
    1238:	1063      	lrw      	r3, 0x2000001c	// 1244 <EPWM_SoftHardWare_OUTPUT_Configure+0xbc>
		EPWM->EMR|=EPWM_LK_output_X<<16;
    123a:	4130      	lsli      	r1, r1, 16
		EPWM->EMR&=0XFFFCFFFF;
    123c:	9360      	ld.w      	r3, (r3, 0)
    123e:	237f      	addi      	r3, 128
    1240:	0406      	br      	0x124c	// 124c <EPWM_SoftHardWare_OUTPUT_Configure+0xc4>
    1242:	0000      	bkpt
    1244:	2000001c 	.long	0x2000001c
    1248:	2000007c 	.long	0x2000007c
    124c:	934a      	ld.w      	r2, (r3, 0x28)
    124e:	3a90      	bclri      	r2, r2, 16
    1250:	3a91      	bclri      	r2, r2, 17
    1252:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<16;
    1254:	934a      	ld.w      	r2, (r3, 0x28)
    1256:	07a4      	br      	0x119e	// 119e <EPWM_SoftHardWare_OUTPUT_Configure+0x16>
	else if(EPWM_LK_output_Select_X==EPWM_LK_output_HLP2XS)
    1258:	3849      	cmpnei      	r0, 9
    125a:	080b      	bt      	0x1270	// 1270 <EPWM_SoftHardWare_OUTPUT_Configure+0xe8>
		EPWM->EMR&=0XFFF3FFFF;
    125c:	127b      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
		EPWM->EMR|=EPWM_LK_output_X<<18;
    125e:	4132      	lsli      	r1, r1, 18
		EPWM->EMR&=0XFFF3FFFF;
    1260:	9360      	ld.w      	r3, (r3, 0)
    1262:	237f      	addi      	r3, 128
    1264:	934a      	ld.w      	r2, (r3, 0x28)
    1266:	3a92      	bclri      	r2, r2, 18
    1268:	3a93      	bclri      	r2, r2, 19
    126a:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<18;
    126c:	934a      	ld.w      	r2, (r3, 0x28)
    126e:	0798      	br      	0x119e	// 119e <EPWM_SoftHardWare_OUTPUT_Configure+0x16>
	else if(EPWM_LK_output_Select_X==EPWM_LK_output_HLP2YS)
    1270:	384a      	cmpnei      	r0, 10
    1272:	080b      	bt      	0x1288	// 1288 <EPWM_SoftHardWare_OUTPUT_Configure+0x100>
		EPWM->EMR&=0XFFCFFFFF;
    1274:	1275      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
		EPWM->EMR|=EPWM_LK_output_X<<20;
    1276:	4134      	lsli      	r1, r1, 20
		EPWM->EMR&=0XFFCFFFFF;
    1278:	9360      	ld.w      	r3, (r3, 0)
    127a:	237f      	addi      	r3, 128
    127c:	934a      	ld.w      	r2, (r3, 0x28)
    127e:	3a94      	bclri      	r2, r2, 20
    1280:	3a95      	bclri      	r2, r2, 21
    1282:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<20;
    1284:	934a      	ld.w      	r2, (r3, 0x28)
    1286:	078c      	br      	0x119e	// 119e <EPWM_SoftHardWare_OUTPUT_Configure+0x16>
	else if(EPWM_LK_output_Select_X==EPWM_LK_output_SLP2XS)
    1288:	384b      	cmpnei      	r0, 11
    128a:	080b      	bt      	0x12a0	// 12a0 <EPWM_SoftHardWare_OUTPUT_Configure+0x118>
		EPWM->EMR&=0XFF3FFFFF;
    128c:	126f      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
		EPWM->EMR|=EPWM_LK_output_X<<22;
    128e:	4136      	lsli      	r1, r1, 22
		EPWM->EMR&=0XFF3FFFFF;
    1290:	9360      	ld.w      	r3, (r3, 0)
    1292:	237f      	addi      	r3, 128
    1294:	934a      	ld.w      	r2, (r3, 0x28)
    1296:	3a96      	bclri      	r2, r2, 22
    1298:	3a97      	bclri      	r2, r2, 23
    129a:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<22;
    129c:	934a      	ld.w      	r2, (r3, 0x28)
    129e:	0780      	br      	0x119e	// 119e <EPWM_SoftHardWare_OUTPUT_Configure+0x16>
	else if(EPWM_LK_output_Select_X==EPWM_LK_output_SLP2YS)
    12a0:	384c      	cmpnei      	r0, 12
    12a2:	0b80      	bt      	0x11a2	// 11a2 <EPWM_SoftHardWare_OUTPUT_Configure+0x1a>
		EPWM->EMR&=0XFCFFFFFF;
    12a4:	1269      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
		EPWM->EMR|=EPWM_LK_output_X<<24;
    12a6:	4138      	lsli      	r1, r1, 24
		EPWM->EMR&=0XFCFFFFFF;
    12a8:	9360      	ld.w      	r3, (r3, 0)
    12aa:	237f      	addi      	r3, 128
    12ac:	934a      	ld.w      	r2, (r3, 0x28)
    12ae:	3a98      	bclri      	r2, r2, 24
    12b0:	3a99      	bclri      	r2, r2, 25
    12b2:	b34a      	st.w      	r2, (r3, 0x28)
		EPWM->EMR|=EPWM_LK_output_X<<24;
    12b4:	934a      	ld.w      	r2, (r3, 0x28)
    12b6:	0774      	br      	0x119e	// 119e <EPWM_SoftHardWare_OUTPUT_Configure+0x16>

000012b8 <EPMW_Soft_Lock_Auto_adjust_Configure>:
//ReturnValue:NONE
/*************************************************************/
//每组CMPAX和CMPBX不能同时设置为增或者减
void EPMW_Soft_Lock_Auto_adjust_Configure(EPWM_SLCON_TypeDef EPWM_SLCON__X , FunctionalStatus NewState , U16_T INC_DEC_STEPX)
{
	if(EPWM_SLCON__X==EPWM_SL_DECA_EN0)
    12b8:	3841      	cmpnei      	r0, 1
    12ba:	0811      	bt      	0x12dc	// 12dc <EPMW_Soft_Lock_Auto_adjust_Configure+0x24>
    12bc:	1263      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
	{
		if (NewState != DISABLE)
    12be:	3940      	cmpnei      	r1, 0
		{
			EPWM->SLCON|=0X00000001;
    12c0:	9360      	ld.w      	r3, (r3, 0)
    12c2:	237f      	addi      	r3, 128
		if (NewState != DISABLE)
    12c4:	0c08      	bf      	0x12d4	// 12d4 <EPMW_Soft_Lock_Auto_adjust_Configure+0x1c>
			EPWM->SLCON|=0X00000001;
    12c6:	932b      	ld.w      	r1, (r3, 0x2c)
    12c8:	6c04      	or      	r0, r1
    12ca:	b30b      	st.w      	r0, (r3, 0x2c)
	else if(EPWM_SLCON__X==EPWM_SL_DECB_EN0)
	{
		if (NewState != DISABLE)
		{
			EPWM->SLCON|=0X00000004;
			EPWM->SLSTEP0=(EPWM->SLSTEP0&0XFFFFF000)|INC_DEC_STEPX;
    12cc:	932c      	ld.w      	r1, (r3, 0x30)
    12ce:	1200      	lrw      	r0, 0xfff	// 13cc <EPMW_Soft_Lock_Auto_adjust_Configure+0x114>
    12d0:	6841      	andn      	r1, r0
    12d2:	0413      	br      	0x12f8	// 12f8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x40>
			EPWM->SLCON&=0XFFFFFFFE;
    12d4:	934b      	ld.w      	r2, (r3, 0x2c)
    12d6:	3a80      	bclri      	r2, r2, 0
		{
			EPWM->SLCON|=0X00000200;
		}
		else
		{
			EPWM->SLCON&=0XFFFFFDFF;
    12d8:	b34b      	st.w      	r2, (r3, 0x2c)
		}
	}
}
    12da:	0411      	br      	0x12fc	// 12fc <EPMW_Soft_Lock_Auto_adjust_Configure+0x44>
	else if(EPWM_SLCON__X==EPWM_SL_INCA_EN0)
    12dc:	3842      	cmpnei      	r0, 2
    12de:	0813      	bt      	0x1304	// 1304 <EPMW_Soft_Lock_Auto_adjust_Configure+0x4c>
    12e0:	117a      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
		if (NewState != DISABLE)
    12e2:	3940      	cmpnei      	r1, 0
			EPWM->SLCON|=0X00000002;
    12e4:	9360      	ld.w      	r3, (r3, 0)
    12e6:	237f      	addi      	r3, 128
		if (NewState != DISABLE)
    12e8:	0c0b      	bf      	0x12fe	// 12fe <EPMW_Soft_Lock_Auto_adjust_Configure+0x46>
			EPWM->SLCON|=0X00000002;
    12ea:	932b      	ld.w      	r1, (r3, 0x2c)
    12ec:	6c04      	or      	r0, r1
    12ee:	b30b      	st.w      	r0, (r3, 0x2c)
			EPWM->SLSTEP0=(EPWM->SLSTEP0&0XFF000FFF)|(INC_DEC_STEPX<<12);
    12f0:	932c      	ld.w      	r1, (r3, 0x30)
    12f2:	1118      	lrw      	r0, 0xfff000	// 13d0 <EPMW_Soft_Lock_Auto_adjust_Configure+0x118>
    12f4:	6841      	andn      	r1, r0
    12f6:	424c      	lsli      	r2, r2, 12
    12f8:	6c84      	or      	r2, r1
    12fa:	b34c      	st.w      	r2, (r3, 0x30)
}
    12fc:	783c      	rts
			EPWM->SLCON&=0XFFFFFFFD;
    12fe:	934b      	ld.w      	r2, (r3, 0x2c)
    1300:	3a81      	bclri      	r2, r2, 1
    1302:	07eb      	br      	0x12d8	// 12d8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x20>
	else if(EPWM_SLCON__X==EPWM_SL_DECB_EN0)
    1304:	3843      	cmpnei      	r0, 3
    1306:	080d      	bt      	0x1320	// 1320 <EPMW_Soft_Lock_Auto_adjust_Configure+0x68>
    1308:	1170      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
		if (NewState != DISABLE)
    130a:	3940      	cmpnei      	r1, 0
			EPWM->SLCON|=0X00000004;
    130c:	9360      	ld.w      	r3, (r3, 0)
    130e:	237f      	addi      	r3, 128
		if (NewState != DISABLE)
    1310:	0c05      	bf      	0x131a	// 131a <EPMW_Soft_Lock_Auto_adjust_Configure+0x62>
			EPWM->SLCON|=0X00000004;
    1312:	932b      	ld.w      	r1, (r3, 0x2c)
    1314:	39a2      	bseti      	r1, r1, 2
    1316:	b32b      	st.w      	r1, (r3, 0x2c)
    1318:	07da      	br      	0x12cc	// 12cc <EPMW_Soft_Lock_Auto_adjust_Configure+0x14>
			EPWM->SLCON&=0XFFFFFFFB;
    131a:	934b      	ld.w      	r2, (r3, 0x2c)
    131c:	3a82      	bclri      	r2, r2, 2
    131e:	07dd      	br      	0x12d8	// 12d8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x20>
	else if(EPWM_SLCON__X==EPWM_SL_INCB_EN0)
    1320:	3844      	cmpnei      	r0, 4
    1322:	080d      	bt      	0x133c	// 133c <EPMW_Soft_Lock_Auto_adjust_Configure+0x84>
    1324:	1169      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
		if (NewState != DISABLE)
    1326:	3940      	cmpnei      	r1, 0
			EPWM->SLCON|=0X00000008;
    1328:	9360      	ld.w      	r3, (r3, 0)
    132a:	237f      	addi      	r3, 128
		if (NewState != DISABLE)
    132c:	0c05      	bf      	0x1336	// 1336 <EPMW_Soft_Lock_Auto_adjust_Configure+0x7e>
			EPWM->SLCON|=0X00000008;
    132e:	932b      	ld.w      	r1, (r3, 0x2c)
    1330:	39a3      	bseti      	r1, r1, 3
    1332:	b32b      	st.w      	r1, (r3, 0x2c)
    1334:	07de      	br      	0x12f0	// 12f0 <EPMW_Soft_Lock_Auto_adjust_Configure+0x38>
			EPWM->SLCON&=0XFFFFFFF7;
    1336:	934b      	ld.w      	r2, (r3, 0x2c)
    1338:	3a83      	bclri      	r2, r2, 3
    133a:	07cf      	br      	0x12d8	// 12d8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x20>
	else if(EPWM_SLCON__X==EPWM_SL_DECA_EN1)
    133c:	3845      	cmpnei      	r0, 5
    133e:	0812      	bt      	0x1362	// 1362 <EPMW_Soft_Lock_Auto_adjust_Configure+0xaa>
    1340:	1162      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
		if (NewState != DISABLE)
    1342:	3940      	cmpnei      	r1, 0
			EPWM->SLCON|=0X00000010;
    1344:	9360      	ld.w      	r3, (r3, 0)
    1346:	237f      	addi      	r3, 128
		if (NewState != DISABLE)
    1348:	0c0a      	bf      	0x135c	// 135c <EPMW_Soft_Lock_Auto_adjust_Configure+0xa4>
			EPWM->SLCON|=0X00000010;
    134a:	932b      	ld.w      	r1, (r3, 0x2c)
    134c:	39a4      	bseti      	r1, r1, 4
			EPWM->SLCON|=0X00000040;
    134e:	b32b      	st.w      	r1, (r3, 0x2c)
			EPWM->SLSTEP1=(EPWM->SLSTEP1&0XFFFFF000)|INC_DEC_STEPX;
    1350:	932d      	ld.w      	r1, (r3, 0x34)
    1352:	101f      	lrw      	r0, 0xfff	// 13cc <EPMW_Soft_Lock_Auto_adjust_Configure+0x114>
    1354:	6841      	andn      	r1, r0
			EPWM->SLSTEP1=(EPWM->SLSTEP1&0XFF000FFF)|(INC_DEC_STEPX<<12);
    1356:	6c84      	or      	r2, r1
    1358:	b34d      	st.w      	r2, (r3, 0x34)
    135a:	07d1      	br      	0x12fc	// 12fc <EPMW_Soft_Lock_Auto_adjust_Configure+0x44>
			EPWM->SLCON&=0XFFFFFFEF;
    135c:	934b      	ld.w      	r2, (r3, 0x2c)
    135e:	3a84      	bclri      	r2, r2, 4
    1360:	07bc      	br      	0x12d8	// 12d8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x20>
	else if(EPWM_SLCON__X==EPWM_SL_INCA_EN1)
    1362:	3846      	cmpnei      	r0, 6
    1364:	0811      	bt      	0x1386	// 1386 <EPMW_Soft_Lock_Auto_adjust_Configure+0xce>
    1366:	1079      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
		if (NewState != DISABLE)
    1368:	3940      	cmpnei      	r1, 0
			EPWM->SLCON|=0X00000020;
    136a:	9360      	ld.w      	r3, (r3, 0)
    136c:	237f      	addi      	r3, 128
		if (NewState != DISABLE)
    136e:	0c09      	bf      	0x1380	// 1380 <EPMW_Soft_Lock_Auto_adjust_Configure+0xc8>
			EPWM->SLCON|=0X00000020;
    1370:	932b      	ld.w      	r1, (r3, 0x2c)
    1372:	39a5      	bseti      	r1, r1, 5
			EPWM->SLCON|=0X00000080;
    1374:	b32b      	st.w      	r1, (r3, 0x2c)
			EPWM->SLSTEP1=(EPWM->SLSTEP1&0XFF000FFF)|(INC_DEC_STEPX<<12);
    1376:	932d      	ld.w      	r1, (r3, 0x34)
    1378:	1016      	lrw      	r0, 0xfff000	// 13d0 <EPMW_Soft_Lock_Auto_adjust_Configure+0x118>
    137a:	6841      	andn      	r1, r0
    137c:	424c      	lsli      	r2, r2, 12
    137e:	07ec      	br      	0x1356	// 1356 <EPMW_Soft_Lock_Auto_adjust_Configure+0x9e>
			EPWM->SLCON&=0XFFFFFFDF;
    1380:	934b      	ld.w      	r2, (r3, 0x2c)
    1382:	3a85      	bclri      	r2, r2, 5
    1384:	07aa      	br      	0x12d8	// 12d8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x20>
	else if(EPWM_SLCON__X==EPWM_SL_DECB_EN1)
    1386:	3847      	cmpnei      	r0, 7
    1388:	080c      	bt      	0x13a0	// 13a0 <EPMW_Soft_Lock_Auto_adjust_Configure+0xe8>
    138a:	1070      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
		if (NewState != DISABLE)
    138c:	3940      	cmpnei      	r1, 0
			EPWM->SLCON|=0X00000040;
    138e:	9360      	ld.w      	r3, (r3, 0)
    1390:	237f      	addi      	r3, 128
		if (NewState != DISABLE)
    1392:	0c04      	bf      	0x139a	// 139a <EPMW_Soft_Lock_Auto_adjust_Configure+0xe2>
			EPWM->SLCON|=0X00000040;
    1394:	932b      	ld.w      	r1, (r3, 0x2c)
    1396:	39a6      	bseti      	r1, r1, 6
    1398:	07db      	br      	0x134e	// 134e <EPMW_Soft_Lock_Auto_adjust_Configure+0x96>
			EPWM->SLCON&=0XFFFFFFBF;
    139a:	934b      	ld.w      	r2, (r3, 0x2c)
    139c:	3a86      	bclri      	r2, r2, 6
    139e:	079d      	br      	0x12d8	// 12d8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x20>
	else if(EPWM_SLCON__X==EPWM_SL_INCB_EN1)
    13a0:	3848      	cmpnei      	r0, 8
    13a2:	080e      	bt      	0x13be	// 13be <EPMW_Soft_Lock_Auto_adjust_Configure+0x106>
    13a4:	1069      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
		if (NewState != DISABLE)
    13a6:	3940      	cmpnei      	r1, 0
			EPWM->SLCON|=0X00000080;
    13a8:	9360      	ld.w      	r3, (r3, 0)
		if (NewState != DISABLE)
    13aa:	0c06      	bf      	0x13b6	// 13b6 <EPMW_Soft_Lock_Auto_adjust_Configure+0xfe>
			EPWM->SLCON|=0X00000080;
    13ac:	3080      	movi      	r0, 128
    13ae:	60c0      	addu      	r3, r0
    13b0:	932b      	ld.w      	r1, (r3, 0x2c)
    13b2:	6c40      	or      	r1, r0
    13b4:	07e0      	br      	0x1374	// 1374 <EPMW_Soft_Lock_Auto_adjust_Configure+0xbc>
			EPWM->SLCON&=0XFFFFFF7F;
    13b6:	237f      	addi      	r3, 128
    13b8:	934b      	ld.w      	r2, (r3, 0x2c)
    13ba:	3a87      	bclri      	r2, r2, 7
    13bc:	078e      	br      	0x12d8	// 12d8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x20>
	else if(EPWM_SLCON__X==EPWM_SL_CNTR_DEC_EN)
    13be:	3849      	cmpnei      	r0, 9
    13c0:	0812      	bt      	0x13e4	// 13e4 <EPMW_Soft_Lock_Auto_adjust_Configure+0x12c>
    13c2:	1062      	lrw      	r3, 0x2000001c	// 13c8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x110>
		if (NewState != DISABLE)
    13c4:	3940      	cmpnei      	r1, 0
    13c6:	0407      	br      	0x13d4	// 13d4 <EPMW_Soft_Lock_Auto_adjust_Configure+0x11c>
    13c8:	2000001c 	.long	0x2000001c
    13cc:	00000fff 	.long	0x00000fff
    13d0:	00fff000 	.long	0x00fff000
			EPWM->SLCON|=0X00000100;
    13d4:	9360      	ld.w      	r3, (r3, 0)
    13d6:	237f      	addi      	r3, 128
    13d8:	934b      	ld.w      	r2, (r3, 0x2c)
		if (NewState != DISABLE)
    13da:	0c03      	bf      	0x13e0	// 13e0 <EPMW_Soft_Lock_Auto_adjust_Configure+0x128>
			EPWM->SLCON|=0X00000100;
    13dc:	3aa8      	bseti      	r2, r2, 8
    13de:	077d      	br      	0x12d8	// 12d8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x20>
			EPWM->SLCON&=0XFFFFFEFF;
    13e0:	3a88      	bclri      	r2, r2, 8
    13e2:	077b      	br      	0x12d8	// 12d8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x20>
	else if(EPWM_SLCON__X==EPWM_SL_CNTR_INC_EN)
    13e4:	384a      	cmpnei      	r0, 10
    13e6:	0b8b      	bt      	0x12fc	// 12fc <EPMW_Soft_Lock_Auto_adjust_Configure+0x44>
    13e8:	1360      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		if (NewState != DISABLE)
    13ea:	3940      	cmpnei      	r1, 0
			EPWM->SLCON|=0X00000200;
    13ec:	9360      	ld.w      	r3, (r3, 0)
    13ee:	237f      	addi      	r3, 128
    13f0:	934b      	ld.w      	r2, (r3, 0x2c)
		if (NewState != DISABLE)
    13f2:	0c03      	bf      	0x13f8	// 13f8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x140>
			EPWM->SLCON|=0X00000200;
    13f4:	3aa9      	bseti      	r2, r2, 9
    13f6:	0771      	br      	0x12d8	// 12d8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x20>
			EPWM->SLCON&=0XFFFFFDFF;
    13f8:	3a89      	bclri      	r2, r2, 9
    13fa:	076f      	br      	0x12d8	// 12d8 <EPMW_Soft_Lock_Auto_adjust_Configure+0x20>

000013fc <EPMW_Soft_Lock_output_SLPXS_CMD>:
//EntryParameter:NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void EPMW_Soft_Lock_output_SLPXS_CMD(FunctionalStatus NewState)		
{
    13fc:	127b      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
	if (NewState != DISABLE)
    13fe:	3840      	cmpnei      	r0, 0
	{
		EPWM->SLCON|=0X01000000;								//一直output SL_PXS设置状态  
    1400:	9360      	ld.w      	r3, (r3, 0)
    1402:	237f      	addi      	r3, 128
    1404:	934b      	ld.w      	r2, (r3, 0x2c)
	if (NewState != DISABLE)
    1406:	0c04      	bf      	0x140e	// 140e <EPMW_Soft_Lock_output_SLPXS_CMD+0x12>
		EPWM->SLCON|=0X01000000;								//一直output SL_PXS设置状态  
    1408:	3ab8      	bseti      	r2, r2, 24
	}
	else
	{
		EPWM->SLCON&=0XFEFFFFFF;								//只output一个周期 SL_PXS设置状态后输出PWM
    140a:	b34b      	st.w      	r2, (r3, 0x2c)
	}
}
    140c:	783c      	rts
		EPWM->SLCON&=0XFEFFFFFF;								//只output一个周期 SL_PXS设置状态后输出PWM
    140e:	3a98      	bclri      	r2, r2, 24
    1410:	07fd      	br      	0x140a	// 140a <EPMW_Soft_Lock_output_SLPXS_CMD+0xe>

00001412 <EPWM_EXTRG_Configure>:
//EPWM_EXTRG_Mode_X:EPWM_EXTRG_Mode_NONE,EPWM_EXTRG_Mode_ADC,EPWM_EXTRG_Mode_STC16,EPWM_EXTRG_Mode_AdcStc16
//ReturnValue:NONE
/*************************************************************/
void EPWM_EXTRG_Configure(EPWM_EXTRG_EVET_TypeDef EPWM_EXTRG_EVET_X , EPWM_EXTRG_Mode_TypeDef EPWM_EXTRG_Mode_X)	
{
	if(EPWM_EXTRG_EVET_X==EPWM0_EXTRG_START)
    1412:	3840      	cmpnei      	r0, 0
    1414:	080c      	bt      	0x142c	// 142c <EPWM_EXTRG_Configure+0x1a>
	{
		EPWM->EXTRG0&=0XFFFFFFFC;
    1416:	1275      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
    1418:	9360      	ld.w      	r3, (r3, 0)
    141a:	237f      	addi      	r3, 128
    141c:	9352      	ld.w      	r2, (r3, 0x48)
    141e:	3a80      	bclri      	r2, r2, 0
    1420:	3a81      	bclri      	r2, r2, 1
    1422:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X;
    1424:	9352      	ld.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<20;
	}
	if(EPWM_EXTRG_EVET_X==EPWM2_EXTRG_CENTER)
	{
		EPWM->EXTRG0&=0XFF3FFFFF;
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<22;
    1426:	6c48      	or      	r1, r2
    1428:	b332      	st.w      	r1, (r3, 0x48)
	if(EPWM_EXTRG_EVET_X==EPWM2_EXTRG_CMPBDM)
	{
		EPWM->EXTRG1&=0XFF3FFFFF;
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<22;
	}
}	
    142a:	783c      	rts
	if(EPWM_EXTRG_EVET_X==EPWM0_EXTRG_STOP)
    142c:	3841      	cmpnei      	r0, 1
    142e:	080b      	bt      	0x1444	// 1444 <EPWM_EXTRG_Configure+0x32>
		EPWM->EXTRG0&=0XFFFFFFF3;
    1430:	126e      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<2;
    1432:	4122      	lsli      	r1, r1, 2
		EPWM->EXTRG0&=0XFFFFFFF3;
    1434:	9360      	ld.w      	r3, (r3, 0)
    1436:	237f      	addi      	r3, 128
    1438:	9352      	ld.w      	r2, (r3, 0x48)
    143a:	3a82      	bclri      	r2, r2, 2
    143c:	3a83      	bclri      	r2, r2, 3
    143e:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<2;
    1440:	9352      	ld.w      	r2, (r3, 0x48)
    1442:	07f2      	br      	0x1426	// 1426 <EPWM_EXTRG_Configure+0x14>
	if(EPWM_EXTRG_EVET_X==EPWM0_EXTRG_PEND)
    1444:	3842      	cmpnei      	r0, 2
    1446:	080b      	bt      	0x145c	// 145c <EPWM_EXTRG_Configure+0x4a>
		EPWM->EXTRG0&=0XFFFFFFCF;
    1448:	1268      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<4;
    144a:	4124      	lsli      	r1, r1, 4
		EPWM->EXTRG0&=0XFFFFFFCF;
    144c:	9360      	ld.w      	r3, (r3, 0)
    144e:	237f      	addi      	r3, 128
    1450:	9352      	ld.w      	r2, (r3, 0x48)
    1452:	3a84      	bclri      	r2, r2, 4
    1454:	3a85      	bclri      	r2, r2, 5
    1456:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<4;
    1458:	9352      	ld.w      	r2, (r3, 0x48)
    145a:	07e6      	br      	0x1426	// 1426 <EPWM_EXTRG_Configure+0x14>
	if(EPWM_EXTRG_EVET_X==EPWM0_EXTRG_CENTER)
    145c:	3843      	cmpnei      	r0, 3
    145e:	080b      	bt      	0x1474	// 1474 <EPWM_EXTRG_Configure+0x62>
		EPWM->EXTRG0&=0XFFFFFF3F;
    1460:	1262      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<6;
    1462:	4126      	lsli      	r1, r1, 6
		EPWM->EXTRG0&=0XFFFFFF3F;
    1464:	9360      	ld.w      	r3, (r3, 0)
    1466:	237f      	addi      	r3, 128
    1468:	9352      	ld.w      	r2, (r3, 0x48)
    146a:	3a86      	bclri      	r2, r2, 6
    146c:	3a87      	bclri      	r2, r2, 7
    146e:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<6;
    1470:	9352      	ld.w      	r2, (r3, 0x48)
    1472:	07da      	br      	0x1426	// 1426 <EPWM_EXTRG_Configure+0x14>
	if(EPWM_EXTRG_EVET_X==EPWM1_EXTRG_START)
    1474:	3844      	cmpnei      	r0, 4
    1476:	080b      	bt      	0x148c	// 148c <EPWM_EXTRG_Configure+0x7a>
		EPWM->EXTRG0&=0XFFFFFCFF;
    1478:	117c      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<8;
    147a:	4128      	lsli      	r1, r1, 8
		EPWM->EXTRG0&=0XFFFFFCFF;
    147c:	9360      	ld.w      	r3, (r3, 0)
    147e:	237f      	addi      	r3, 128
    1480:	9352      	ld.w      	r2, (r3, 0x48)
    1482:	3a88      	bclri      	r2, r2, 8
    1484:	3a89      	bclri      	r2, r2, 9
    1486:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<8;
    1488:	9352      	ld.w      	r2, (r3, 0x48)
    148a:	07ce      	br      	0x1426	// 1426 <EPWM_EXTRG_Configure+0x14>
	if(EPWM_EXTRG_EVET_X==EPWM1_EXTRG_STOP)
    148c:	3845      	cmpnei      	r0, 5
    148e:	080b      	bt      	0x14a4	// 14a4 <EPWM_EXTRG_Configure+0x92>
		EPWM->EXTRG0&=0XFFFFF3FF;
    1490:	1176      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<10;
    1492:	412a      	lsli      	r1, r1, 10
		EPWM->EXTRG0&=0XFFFFF3FF;
    1494:	9360      	ld.w      	r3, (r3, 0)
    1496:	237f      	addi      	r3, 128
    1498:	9352      	ld.w      	r2, (r3, 0x48)
    149a:	3a8a      	bclri      	r2, r2, 10
    149c:	3a8b      	bclri      	r2, r2, 11
    149e:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<10;
    14a0:	9352      	ld.w      	r2, (r3, 0x48)
    14a2:	07c2      	br      	0x1426	// 1426 <EPWM_EXTRG_Configure+0x14>
	if(EPWM_EXTRG_EVET_X==EPWM1_EXTRG_PEND)
    14a4:	3846      	cmpnei      	r0, 6
    14a6:	080b      	bt      	0x14bc	// 14bc <EPWM_EXTRG_Configure+0xaa>
		EPWM->EXTRG0&=0XFFFFCFFF;
    14a8:	1170      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<12;
    14aa:	412c      	lsli      	r1, r1, 12
		EPWM->EXTRG0&=0XFFFFCFFF;
    14ac:	9360      	ld.w      	r3, (r3, 0)
    14ae:	237f      	addi      	r3, 128
    14b0:	9352      	ld.w      	r2, (r3, 0x48)
    14b2:	3a8c      	bclri      	r2, r2, 12
    14b4:	3a8d      	bclri      	r2, r2, 13
    14b6:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<12;
    14b8:	9352      	ld.w      	r2, (r3, 0x48)
    14ba:	07b6      	br      	0x1426	// 1426 <EPWM_EXTRG_Configure+0x14>
	if(EPWM_EXTRG_EVET_X==EPWM1_EXTRG_CENTER)
    14bc:	3847      	cmpnei      	r0, 7
    14be:	080b      	bt      	0x14d4	// 14d4 <EPWM_EXTRG_Configure+0xc2>
		EPWM->EXTRG0&=0XFFFF3FFF;
    14c0:	116a      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<14;
    14c2:	412e      	lsli      	r1, r1, 14
		EPWM->EXTRG0&=0XFFFF3FFF;
    14c4:	9360      	ld.w      	r3, (r3, 0)
    14c6:	237f      	addi      	r3, 128
    14c8:	9352      	ld.w      	r2, (r3, 0x48)
    14ca:	3a8e      	bclri      	r2, r2, 14
    14cc:	3a8f      	bclri      	r2, r2, 15
    14ce:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<14;
    14d0:	9352      	ld.w      	r2, (r3, 0x48)
    14d2:	07aa      	br      	0x1426	// 1426 <EPWM_EXTRG_Configure+0x14>
	if(EPWM_EXTRG_EVET_X==EPWM2_EXTRG_START)
    14d4:	3848      	cmpnei      	r0, 8
    14d6:	080b      	bt      	0x14ec	// 14ec <EPWM_EXTRG_Configure+0xda>
		EPWM->EXTRG0&=0XFFFCFFFF;
    14d8:	1164      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<16;
    14da:	4130      	lsli      	r1, r1, 16
		EPWM->EXTRG0&=0XFFFCFFFF;
    14dc:	9360      	ld.w      	r3, (r3, 0)
    14de:	237f      	addi      	r3, 128
    14e0:	9352      	ld.w      	r2, (r3, 0x48)
    14e2:	3a90      	bclri      	r2, r2, 16
    14e4:	3a91      	bclri      	r2, r2, 17
    14e6:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<16;
    14e8:	9352      	ld.w      	r2, (r3, 0x48)
    14ea:	079e      	br      	0x1426	// 1426 <EPWM_EXTRG_Configure+0x14>
	if(EPWM_EXTRG_EVET_X==EPWM2_EXTRG_STOP)
    14ec:	3849      	cmpnei      	r0, 9
    14ee:	080b      	bt      	0x1504	// 1504 <EPWM_EXTRG_Configure+0xf2>
		EPWM->EXTRG0&=0XFFF3FFFF;
    14f0:	107e      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<18;
    14f2:	4132      	lsli      	r1, r1, 18
		EPWM->EXTRG0&=0XFFF3FFFF;
    14f4:	9360      	ld.w      	r3, (r3, 0)
    14f6:	237f      	addi      	r3, 128
    14f8:	9352      	ld.w      	r2, (r3, 0x48)
    14fa:	3a92      	bclri      	r2, r2, 18
    14fc:	3a93      	bclri      	r2, r2, 19
    14fe:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<18;
    1500:	9352      	ld.w      	r2, (r3, 0x48)
    1502:	0792      	br      	0x1426	// 1426 <EPWM_EXTRG_Configure+0x14>
	if(EPWM_EXTRG_EVET_X==EPWM2_EXTRG_PEND)
    1504:	384a      	cmpnei      	r0, 10
    1506:	080b      	bt      	0x151c	// 151c <EPWM_EXTRG_Configure+0x10a>
		EPWM->EXTRG0&=0XFFCFFFFF;
    1508:	1078      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<20;
    150a:	4134      	lsli      	r1, r1, 20
		EPWM->EXTRG0&=0XFFCFFFFF;
    150c:	9360      	ld.w      	r3, (r3, 0)
    150e:	237f      	addi      	r3, 128
    1510:	9352      	ld.w      	r2, (r3, 0x48)
    1512:	3a94      	bclri      	r2, r2, 20
    1514:	3a95      	bclri      	r2, r2, 21
    1516:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<20;
    1518:	9352      	ld.w      	r2, (r3, 0x48)
    151a:	0786      	br      	0x1426	// 1426 <EPWM_EXTRG_Configure+0x14>
	if(EPWM_EXTRG_EVET_X==EPWM2_EXTRG_CENTER)
    151c:	384b      	cmpnei      	r0, 11
    151e:	080b      	bt      	0x1534	// 1534 <EPWM_EXTRG_Configure+0x122>
		EPWM->EXTRG0&=0XFF3FFFFF;
    1520:	1072      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<22;
    1522:	4136      	lsli      	r1, r1, 22
		EPWM->EXTRG0&=0XFF3FFFFF;
    1524:	9360      	ld.w      	r3, (r3, 0)
    1526:	237f      	addi      	r3, 128
    1528:	9352      	ld.w      	r2, (r3, 0x48)
    152a:	3a96      	bclri      	r2, r2, 22
    152c:	3a97      	bclri      	r2, r2, 23
    152e:	b352      	st.w      	r2, (r3, 0x48)
		EPWM->EXTRG0|=EPWM_EXTRG_Mode_X<<22;
    1530:	9352      	ld.w      	r2, (r3, 0x48)
    1532:	077a      	br      	0x1426	// 1426 <EPWM_EXTRG_Configure+0x14>
	if(EPWM_EXTRG_EVET_X==EPWM0_EXTRG_CMPAUM)
    1534:	384c      	cmpnei      	r0, 12
    1536:	080c      	bt      	0x154e	// 154e <EPWM_EXTRG_Configure+0x13c>
		EPWM->EXTRG1&=0XFFFFFFFC;
    1538:	106c      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
    153a:	9360      	ld.w      	r3, (r3, 0)
    153c:	237f      	addi      	r3, 128
    153e:	9353      	ld.w      	r2, (r3, 0x4c)
    1540:	3a80      	bclri      	r2, r2, 0
    1542:	3a81      	bclri      	r2, r2, 1
    1544:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X;
    1546:	9353      	ld.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<22;
    1548:	6c48      	or      	r1, r2
    154a:	b333      	st.w      	r1, (r3, 0x4c)
}	
    154c:	076f      	br      	0x142a	// 142a <EPWM_EXTRG_Configure+0x18>
	if(EPWM_EXTRG_EVET_X==EPWM0_EXTRG_CMPADM)
    154e:	384d      	cmpnei      	r0, 13
    1550:	080e      	bt      	0x156c	// 156c <EPWM_EXTRG_Configure+0x15a>
		EPWM->EXTRG1&=0XFFFFFFF3;
    1552:	1066      	lrw      	r3, 0x2000001c	// 1568 <EPWM_EXTRG_Configure+0x156>
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<2;
    1554:	4122      	lsli      	r1, r1, 2
		EPWM->EXTRG1&=0XFFFFFFF3;
    1556:	9360      	ld.w      	r3, (r3, 0)
    1558:	237f      	addi      	r3, 128
    155a:	9353      	ld.w      	r2, (r3, 0x4c)
    155c:	3a82      	bclri      	r2, r2, 2
    155e:	3a83      	bclri      	r2, r2, 3
    1560:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<2;
    1562:	9353      	ld.w      	r2, (r3, 0x4c)
    1564:	07f2      	br      	0x1548	// 1548 <EPWM_EXTRG_Configure+0x136>
    1566:	0000      	bkpt
    1568:	2000001c 	.long	0x2000001c
	if(EPWM_EXTRG_EVET_X==EPWM0_EXTRG_CMPBUM)
    156c:	384e      	cmpnei      	r0, 14
    156e:	080b      	bt      	0x1584	// 1584 <EPWM_EXTRG_Configure+0x172>
		EPWM->EXTRG1&=0XFFFFFFCF;
    1570:	126b      	lrw      	r3, 0x2000001c	// 169c <EPWM_Wakeup_Disable+0x12>
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<4;
    1572:	4124      	lsli      	r1, r1, 4
		EPWM->EXTRG1&=0XFFFFFFCF;
    1574:	9360      	ld.w      	r3, (r3, 0)
    1576:	237f      	addi      	r3, 128
    1578:	9353      	ld.w      	r2, (r3, 0x4c)
    157a:	3a84      	bclri      	r2, r2, 4
    157c:	3a85      	bclri      	r2, r2, 5
    157e:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<4;
    1580:	9353      	ld.w      	r2, (r3, 0x4c)
    1582:	07e3      	br      	0x1548	// 1548 <EPWM_EXTRG_Configure+0x136>
	if(EPWM_EXTRG_EVET_X==EPWM0_EXTRG_CMPBDM)
    1584:	384f      	cmpnei      	r0, 15
    1586:	080b      	bt      	0x159c	// 159c <EPWM_EXTRG_Configure+0x18a>
		EPWM->EXTRG1&=0XFFFFFF3F;
    1588:	1265      	lrw      	r3, 0x2000001c	// 169c <EPWM_Wakeup_Disable+0x12>
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<6;
    158a:	4126      	lsli      	r1, r1, 6
		EPWM->EXTRG1&=0XFFFFFF3F;
    158c:	9360      	ld.w      	r3, (r3, 0)
    158e:	237f      	addi      	r3, 128
    1590:	9353      	ld.w      	r2, (r3, 0x4c)
    1592:	3a86      	bclri      	r2, r2, 6
    1594:	3a87      	bclri      	r2, r2, 7
    1596:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<6;
    1598:	9353      	ld.w      	r2, (r3, 0x4c)
    159a:	07d7      	br      	0x1548	// 1548 <EPWM_EXTRG_Configure+0x136>
	if(EPWM_EXTRG_EVET_X==EPWM1_EXTRG_CMPAUM)
    159c:	3850      	cmpnei      	r0, 16
    159e:	080b      	bt      	0x15b4	// 15b4 <EPWM_EXTRG_Configure+0x1a2>
		EPWM->EXTRG1&=0XFFFFFCFF;
    15a0:	117f      	lrw      	r3, 0x2000001c	// 169c <EPWM_Wakeup_Disable+0x12>
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<8;
    15a2:	4128      	lsli      	r1, r1, 8
		EPWM->EXTRG1&=0XFFFFFCFF;
    15a4:	9360      	ld.w      	r3, (r3, 0)
    15a6:	237f      	addi      	r3, 128
    15a8:	9353      	ld.w      	r2, (r3, 0x4c)
    15aa:	3a88      	bclri      	r2, r2, 8
    15ac:	3a89      	bclri      	r2, r2, 9
    15ae:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<8;
    15b0:	9353      	ld.w      	r2, (r3, 0x4c)
    15b2:	07cb      	br      	0x1548	// 1548 <EPWM_EXTRG_Configure+0x136>
	if(EPWM_EXTRG_EVET_X==EPWM1_EXTRG_CMPADM)
    15b4:	3851      	cmpnei      	r0, 17
    15b6:	080b      	bt      	0x15cc	// 15cc <EPWM_EXTRG_Configure+0x1ba>
		EPWM->EXTRG1&=0XFFFFF3FF;
    15b8:	1179      	lrw      	r3, 0x2000001c	// 169c <EPWM_Wakeup_Disable+0x12>
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<10;
    15ba:	412a      	lsli      	r1, r1, 10
		EPWM->EXTRG1&=0XFFFFF3FF;
    15bc:	9360      	ld.w      	r3, (r3, 0)
    15be:	237f      	addi      	r3, 128
    15c0:	9353      	ld.w      	r2, (r3, 0x4c)
    15c2:	3a8a      	bclri      	r2, r2, 10
    15c4:	3a8b      	bclri      	r2, r2, 11
    15c6:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<10;
    15c8:	9353      	ld.w      	r2, (r3, 0x4c)
    15ca:	07bf      	br      	0x1548	// 1548 <EPWM_EXTRG_Configure+0x136>
	if(EPWM_EXTRG_EVET_X==EPWM1_EXTRG_CMPBUM)
    15cc:	3852      	cmpnei      	r0, 18
    15ce:	080b      	bt      	0x15e4	// 15e4 <EPWM_EXTRG_Configure+0x1d2>
		EPWM->EXTRG1&=0XFFFFCFFF;
    15d0:	1173      	lrw      	r3, 0x2000001c	// 169c <EPWM_Wakeup_Disable+0x12>
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<12;
    15d2:	412c      	lsli      	r1, r1, 12
		EPWM->EXTRG1&=0XFFFFCFFF;
    15d4:	9360      	ld.w      	r3, (r3, 0)
    15d6:	237f      	addi      	r3, 128
    15d8:	9353      	ld.w      	r2, (r3, 0x4c)
    15da:	3a8c      	bclri      	r2, r2, 12
    15dc:	3a8d      	bclri      	r2, r2, 13
    15de:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<12;
    15e0:	9353      	ld.w      	r2, (r3, 0x4c)
    15e2:	07b3      	br      	0x1548	// 1548 <EPWM_EXTRG_Configure+0x136>
	if(EPWM_EXTRG_EVET_X==EPWM1_EXTRG_CMPBDM)
    15e4:	3853      	cmpnei      	r0, 19
    15e6:	080b      	bt      	0x15fc	// 15fc <EPWM_EXTRG_Configure+0x1ea>
		EPWM->EXTRG1&=0XFFFF3FFF;
    15e8:	116d      	lrw      	r3, 0x2000001c	// 169c <EPWM_Wakeup_Disable+0x12>
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<14;
    15ea:	412e      	lsli      	r1, r1, 14
		EPWM->EXTRG1&=0XFFFF3FFF;
    15ec:	9360      	ld.w      	r3, (r3, 0)
    15ee:	237f      	addi      	r3, 128
    15f0:	9353      	ld.w      	r2, (r3, 0x4c)
    15f2:	3a8e      	bclri      	r2, r2, 14
    15f4:	3a8f      	bclri      	r2, r2, 15
    15f6:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<14;
    15f8:	9353      	ld.w      	r2, (r3, 0x4c)
    15fa:	07a7      	br      	0x1548	// 1548 <EPWM_EXTRG_Configure+0x136>
	if(EPWM_EXTRG_EVET_X==EPWM2_EXTRG_CMPAUM)
    15fc:	3854      	cmpnei      	r0, 20
    15fe:	080b      	bt      	0x1614	// 1614 <EPWM_EXTRG_Configure+0x202>
		EPWM->EXTRG1&=0XFFFCFFFF;
    1600:	1167      	lrw      	r3, 0x2000001c	// 169c <EPWM_Wakeup_Disable+0x12>
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<16;
    1602:	4130      	lsli      	r1, r1, 16
		EPWM->EXTRG1&=0XFFFCFFFF;
    1604:	9360      	ld.w      	r3, (r3, 0)
    1606:	237f      	addi      	r3, 128
    1608:	9353      	ld.w      	r2, (r3, 0x4c)
    160a:	3a90      	bclri      	r2, r2, 16
    160c:	3a91      	bclri      	r2, r2, 17
    160e:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<16;
    1610:	9353      	ld.w      	r2, (r3, 0x4c)
    1612:	079b      	br      	0x1548	// 1548 <EPWM_EXTRG_Configure+0x136>
	if(EPWM_EXTRG_EVET_X==EPWM2_EXTRG_CMPADM)
    1614:	3855      	cmpnei      	r0, 21
    1616:	080b      	bt      	0x162c	// 162c <EPWM_EXTRG_Configure+0x21a>
		EPWM->EXTRG1&=0XFFF3FFFF;
    1618:	1161      	lrw      	r3, 0x2000001c	// 169c <EPWM_Wakeup_Disable+0x12>
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<18;
    161a:	4132      	lsli      	r1, r1, 18
		EPWM->EXTRG1&=0XFFF3FFFF;
    161c:	9360      	ld.w      	r3, (r3, 0)
    161e:	237f      	addi      	r3, 128
    1620:	9353      	ld.w      	r2, (r3, 0x4c)
    1622:	3a92      	bclri      	r2, r2, 18
    1624:	3a93      	bclri      	r2, r2, 19
    1626:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<18;
    1628:	9353      	ld.w      	r2, (r3, 0x4c)
    162a:	078f      	br      	0x1548	// 1548 <EPWM_EXTRG_Configure+0x136>
	if(EPWM_EXTRG_EVET_X==EPWM2_EXTRG_CMPBUM)
    162c:	3856      	cmpnei      	r0, 22
    162e:	080b      	bt      	0x1644	// 1644 <EPWM_EXTRG_Configure+0x232>
		EPWM->EXTRG1&=0XFFCFFFFF;
    1630:	107b      	lrw      	r3, 0x2000001c	// 169c <EPWM_Wakeup_Disable+0x12>
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<20;
    1632:	4134      	lsli      	r1, r1, 20
		EPWM->EXTRG1&=0XFFCFFFFF;
    1634:	9360      	ld.w      	r3, (r3, 0)
    1636:	237f      	addi      	r3, 128
    1638:	9353      	ld.w      	r2, (r3, 0x4c)
    163a:	3a94      	bclri      	r2, r2, 20
    163c:	3a95      	bclri      	r2, r2, 21
    163e:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<20;
    1640:	9353      	ld.w      	r2, (r3, 0x4c)
    1642:	0783      	br      	0x1548	// 1548 <EPWM_EXTRG_Configure+0x136>
	if(EPWM_EXTRG_EVET_X==EPWM2_EXTRG_CMPBDM)
    1644:	3857      	cmpnei      	r0, 23
    1646:	0af2      	bt      	0x142a	// 142a <EPWM_EXTRG_Configure+0x18>
		EPWM->EXTRG1&=0XFF3FFFFF;
    1648:	1075      	lrw      	r3, 0x2000001c	// 169c <EPWM_Wakeup_Disable+0x12>
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<22;
    164a:	4136      	lsli      	r1, r1, 22
		EPWM->EXTRG1&=0XFF3FFFFF;
    164c:	9360      	ld.w      	r3, (r3, 0)
    164e:	237f      	addi      	r3, 128
    1650:	9353      	ld.w      	r2, (r3, 0x4c)
    1652:	3a96      	bclri      	r2, r2, 22
    1654:	3a97      	bclri      	r2, r2, 23
    1656:	b353      	st.w      	r2, (r3, 0x4c)
		EPWM->EXTRG1|=EPWM_EXTRG_Mode_X<<22;
    1658:	9353      	ld.w      	r2, (r3, 0x4c)
    165a:	0777      	br      	0x1548	// 1548 <EPWM_EXTRG_Configure+0x136>

0000165c <EPWM_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPWM_Int_Enable(void)
{
    INTC_ISER_WRITE(EPWM_INT);    
    165c:	1071      	lrw      	r3, 0x20000064	// 16a0 <EPWM_Wakeup_Disable+0x16>
    165e:	3280      	movi      	r2, 128
    1660:	9360      	ld.w      	r3, (r3, 0)
    1662:	23ff      	addi      	r3, 256
    1664:	4242      	lsli      	r2, r2, 2
    1666:	b340      	st.w      	r2, (r3, 0)
}
    1668:	783c      	rts

0000166a <EPWM_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPWM_Int_Disable(void)
{
    INTC_ICER_WRITE(EPWM_INT);    
    166a:	106e      	lrw      	r3, 0x20000064	// 16a0 <EPWM_Wakeup_Disable+0x16>
    166c:	32c0      	movi      	r2, 192
    166e:	9360      	ld.w      	r3, (r3, 0)
    1670:	4241      	lsli      	r2, r2, 1
    1672:	60c8      	addu      	r3, r2
    1674:	3280      	movi      	r2, 128
    1676:	4242      	lsli      	r2, r2, 2
    1678:	b340      	st.w      	r2, (r3, 0)
}
    167a:	783c      	rts

0000167c <EPWM_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPWM_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(EPWM_INT);    
    167c:	1069      	lrw      	r3, 0x20000064	// 16a0 <EPWM_Wakeup_Disable+0x16>
    167e:	3280      	movi      	r2, 128
    1680:	9360      	ld.w      	r3, (r3, 0)
    1682:	23ff      	addi      	r3, 256
    1684:	4242      	lsli      	r2, r2, 2
    1686:	b350      	st.w      	r2, (r3, 0x40)
}
    1688:	783c      	rts

0000168a <EPWM_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPWM_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(EPWM_INT);    
    168a:	1066      	lrw      	r3, 0x20000064	// 16a0 <EPWM_Wakeup_Disable+0x16>
    168c:	32e0      	movi      	r2, 224
    168e:	9360      	ld.w      	r3, (r3, 0)
    1690:	4241      	lsli      	r2, r2, 1
    1692:	60c8      	addu      	r3, r2
    1694:	3280      	movi      	r2, 128
    1696:	4242      	lsli      	r2, r2, 2
    1698:	b340      	st.w      	r2, (r3, 0)
}
    169a:	783c      	rts
    169c:	2000001c 	.long	0x2000001c
    16a0:	20000064 	.long	0x20000064

000016a4 <LED_RESET_VALUE>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void LED_RESET_VALUE(void)
{
	 LED0->CR			=	LED0_CR_RST;     					/**< CR  reset value  	*/
    16a4:	106b      	lrw      	r3, 0x20000018	// 16d0 <LED_RESET_VALUE+0x2c>
    16a6:	3200      	movi      	r2, 0
    16a8:	9360      	ld.w      	r3, (r3, 0)
    16aa:	b340      	st.w      	r2, (r3, 0)
	 LED0->BRIGHT		=	LED0_BRIGHT_RST;                  	/**< BRIGHT reset value */
    16ac:	b341      	st.w      	r2, (r3, 0x4)
	 LED0->RISR			= 	LED0_RISR_RST;       		  		/**< RISR reset value  	*/
    16ae:	b342      	st.w      	r2, (r3, 0x8)
	 LED0->IMCR			=	LED0_IMCR_RST;             			/**< IMCR reset value  	*/
    16b0:	b343      	st.w      	r2, (r3, 0xc)
	 LED0->MISR			=   LED0_MISR_RST;                  	/**< MISR reset value  	*/
    16b2:	b344      	st.w      	r2, (r3, 0x10)
	 LED0->ICR 			=	LED0_ICR_RST;                   	/**< ICR reset value  	*/
    16b4:	b345      	st.w      	r2, (r3, 0x14)
	 LED0->TIMCR		=	LED0_TIMCR_RST;						/**< TIMCR reset value  */	
    16b6:	b347      	st.w      	r2, (r3, 0x1c)
	 LED0->BLKER		=	LED0_BLKER_RST;						/**< BLKER reset value  */	
    16b8:	b348      	st.w      	r2, (r3, 0x20)
	 LED0->BLKDR		=	LED0_BLKDR_RST;						/**< BLKDR reset value  */	
    16ba:	b349      	st.w      	r2, (r3, 0x24)
	 LED0->BLKST		=	LED0_BLKST_RST;						/**< BLKST reset value  */	
    16bc:	b34a      	st.w      	r2, (r3, 0x28)
	 LED0->SEGDATA0 	=	LED0_SEGDAT0_RST;                	/**< SEGDAT0  reset value */
    16be:	b34b      	st.w      	r2, (r3, 0x2c)
	 LED0->SEGDATA1 	=	LED0_SEGDAT1_RST;              		/**< SEGDAT1  reset value */
    16c0:	b34c      	st.w      	r2, (r3, 0x30)
	 LED0->SEGDATA2  	=	LED0_SEGDAT2_RST;               	/**< SEGDAT2  reset value */
    16c2:	b34d      	st.w      	r2, (r3, 0x34)
	 LED0->SEGDATA3 	=	LED0_SEGDAT3_RST;             		/**< SEGDAT3  reset value */
    16c4:	b34e      	st.w      	r2, (r3, 0x38)
	 LED0->SEGDATA4 	=	LED0_SEGDAT0_RST;                	/**< SEGDAT0  reset value */
    16c6:	b34f      	st.w      	r2, (r3, 0x3c)
	 LED0->SEGDATA5 	=	LED0_SEGDAT1_RST;              		/**< SEGDAT1  reset value */
    16c8:	b350      	st.w      	r2, (r3, 0x40)
	 LED0->SEGDATA6  	=	LED0_SEGDAT2_RST;               	/**< SEGDAT2  reset value */
    16ca:	b351      	st.w      	r2, (r3, 0x44)
	 LED0->SEGDATA7 	=	LED0_SEGDAT3_RST;             		/**< SEGDAT3  reset value */
    16cc:	b352      	st.w      	r2, (r3, 0x48)
}
    16ce:	783c      	rts
    16d0:	20000018 	.long	0x20000018

000016d4 <LED_SCAN_ENABLE>:
//EntryParameter:NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/  
void LED_SCAN_ENABLE(FunctionalStatus NewState)
{
    16d4:	1362      	lrw      	r3, 0x20000018	// 185c <LED_seg_io_initial+0x4c>
	if (NewState != DISABLE)
    16d6:	3840      	cmpnei      	r0, 0
	{
		LED0->CR|=LIGHTON;
    16d8:	9340      	ld.w      	r2, (r3, 0)
    16da:	9260      	ld.w      	r3, (r2, 0)
	if (NewState != DISABLE)
    16dc:	0c04      	bf      	0x16e4	// 16e4 <LED_SCAN_ENABLE+0x10>
		LED0->CR|=LIGHTON;
    16de:	3ba0      	bseti      	r3, r3, 0
	}
	else
	{
		LED0->CR&=~LIGHTON;
    16e0:	b260      	st.w      	r3, (r2, 0)
	}
}
    16e2:	783c      	rts
		LED0->CR&=~LIGHTON;
    16e4:	3b80      	bclri      	r3, r3, 0
    16e6:	07fd      	br      	0x16e0	// 16e0 <LED_SCAN_ENABLE+0xc>

000016e8 <LED_COM_ENABLE>:
//NewState:ENABLE,DISABLE
//LED_COMx_ENABLE:0~0xff
//ReturnValue:NONE
/*************************************************************/  
void LED_COM_ENABLE(U8_T LED_COMx_ENABLE)
{
    16e8:	14d2      	push      	r4-r5, r15
	uint8_t i;
	LED0->BLKER=0Xff;
    16ea:	127d      	lrw      	r3, 0x20000018	// 185c <LED_seg_io_initial+0x4c>
    16ec:	32ff      	movi      	r2, 255
    16ee:	9360      	ld.w      	r3, (r3, 0)
    16f0:	b348      	st.w      	r2, (r3, 0x20)
{
    16f2:	6d03      	mov      	r4, r0
	LED0->BLKER=0Xff;
    16f4:	3200      	movi      	r2, 0
	for (i=0;i<8;i++)
	{
		if ((LED_COMx_ENABLE & (1<<i))!=0)
    16f6:	3501      	movi      	r5, 1
    16f8:	6c53      	mov      	r1, r4
    16fa:	704a      	asr      	r1, r2
    16fc:	6854      	and      	r1, r5
    16fe:	3940      	cmpnei      	r1, 0
    1700:	7408      	zextb      	r0, r2
    1702:	0c0c      	bf      	0x171a	// 171a <LED_COM_ENABLE+0x32>
		{
			switch (i)
    1704:	2800      	subi      	r0, 1
    1706:	3806      	cmphsi      	r0, 7
    1708:	0807      	bt      	0x1716	// 1716 <LED_COM_ENABLE+0x2e>
    170a:	e0001dcb 	bsr      	0x52a0	// 52a0 <___gnu_csky_case_uqi>
    170e:	0c0a      	.short	0x0c0a
    1710:	1412100e 	.long	0x1412100e
    1714:	0016      	.short	0x0016
			{
				case 0:
				{
					LED0->BLKDR=0x01;													//COM1使能
    1716:	3101      	movi      	r1, 1
					LED0->BLKDR=0x40;													//COM7使能
					break;
				}
				case 7:
				{
					LED0->BLKDR=0x80;													//COM8使能
    1718:	b329      	st.w      	r1, (r3, 0x24)
    171a:	2200      	addi      	r2, 1
	for (i=0;i<8;i++)
    171c:	3a48      	cmpnei      	r2, 8
    171e:	0bed      	bt      	0x16f8	// 16f8 <LED_COM_ENABLE+0x10>
					break;
				}
			}
		}
	}
}
    1720:	1492      	pop      	r4-r5, r15
					LED0->BLKDR=0x02;													//COM2使能
    1722:	3102      	movi      	r1, 2
    1724:	07fa      	br      	0x1718	// 1718 <LED_COM_ENABLE+0x30>
					LED0->BLKDR=0x04;													//COM3使能
    1726:	3104      	movi      	r1, 4
    1728:	07f8      	br      	0x1718	// 1718 <LED_COM_ENABLE+0x30>
					LED0->BLKDR=0x08;													//COM4使能
    172a:	3108      	movi      	r1, 8
    172c:	07f6      	br      	0x1718	// 1718 <LED_COM_ENABLE+0x30>
					LED0->BLKDR=0x10;													//COM5使能
    172e:	3110      	movi      	r1, 16
    1730:	07f4      	br      	0x1718	// 1718 <LED_COM_ENABLE+0x30>
					LED0->BLKDR=0x20;													//COM6使能
    1732:	3120      	movi      	r1, 32
    1734:	07f2      	br      	0x1718	// 1718 <LED_COM_ENABLE+0x30>
					LED0->BLKDR=0x40;													//COM7使能
    1736:	3140      	movi      	r1, 64
    1738:	07f0      	br      	0x1718	// 1718 <LED_COM_ENABLE+0x30>
					LED0->BLKDR=0x80;													//COM8使能
    173a:	3180      	movi      	r1, 128
    173c:	07ee      	br      	0x1718	// 1718 <LED_COM_ENABLE+0x30>

0000173e <LED_Control_Config>:
  //LEDCLK=PLCK/LEDCLK_DIVx
  //LED_Bright_X:LED_Bright_100/LED_Bright_87/LED_Bright_75/LED_Bright_62/LED_Bright_50/LED_Bright_37LED_Bright_25/LED_Bright_12
  //DCOMCNT:COM显示周期长度
  //NOVCNT:相邻COM时间
void LED_Control_Config(LED_LEDCLK_TypeDef LED_LEDCLK , U8_T LED_COM_EN , LED_Bright_TypeDef LED_Bright_X , U8_T DCOMCNT , U8_T NOVCNT  )
{
    173e:	14d4      	push      	r4-r7, r15
    1740:	1427      	subi      	sp, sp, 28
    1742:	b864      	st.w      	r3, (sp, 0x10)
    1744:	1b0c      	addi      	r3, sp, 48
    1746:	8360      	ld.b      	r3, (r3, 0)
    1748:	b843      	st.w      	r2, (sp, 0xc)
    174a:	b865      	st.w      	r3, (sp, 0x14)
					GPIOA1->CONLR=(GPIOA1->CONLR&0XFFF0FFFF) | 0x00080000;				//COM1
					break;
				}
				case 2:
				{
					GPIOA1->CONLR=(GPIOA1->CONLR&0XFF0FFFFF) | 0x00800000;				//COM2
    174c:	36f0      	movi      	r6, 240
					GPIOB0->CONLR=(GPIOB0->CONLR&0XFFFFFF0F) | 0x00000080;				//COM6
					break;
				}
				case 7:
				{
					GPIOA0->CONLR=(GPIOA0->CONLR&0XFFFFFFF0) | 0x00000008;				//COM7
    174e:	1245      	lrw      	r2, 0x20000050	// 1860 <LED_seg_io_initial+0x50>
					GPIOB0->CONLR=(GPIOB0->CONLR&0XFFFFFF0F) | 0x00000080;				//COM6
    1750:	1265      	lrw      	r3, 0x20000048	// 1864 <LED_seg_io_initial+0x54>
					GPIOA1->CONLR=(GPIOA1->CONLR&0XFFF0FFFF) | 0x00080000;				//COM1
    1752:	37f0      	movi      	r7, 240
					GPIOA0->CONLR=(GPIOA0->CONLR&0XFFFFFFF0) | 0x00000008;				//COM7
    1754:	9240      	ld.w      	r2, (r2, 0)
					GPIOB0->CONLR=(GPIOB0->CONLR&0XFFFFFF0F) | 0x00000080;				//COM6
    1756:	93a0      	ld.w      	r5, (r3, 0)
					GPIOA0->CONLR=(GPIOA0->CONLR&0XFFFFFFF0) | 0x00000008;				//COM7
    1758:	b840      	st.w      	r2, (sp, 0)
					GPIOA1->CONLR=(GPIOA1->CONLR&0XFFFF0FFF) | 0x00008000;				//COM0
    175a:	32f0      	movi      	r2, 240
					GPIOC0->CONLR=(GPIOC0->CONLR&0XFFFFFF0F) | 0x00000080;				//COM4
    175c:	1263      	lrw      	r3, 0x20000044	// 1868 <LED_seg_io_initial+0x58>
					GPIOA1->CONLR=(GPIOA1->CONLR&0XFFFF0FFF) | 0x00008000;				//COM0
    175e:	4248      	lsli      	r2, r2, 8
					GPIOC0->CONLR=(GPIOC0->CONLR&0XFFFFFF0F) | 0x00000080;				//COM4
    1760:	9380      	ld.w      	r4, (r3, 0)
{
    1762:	b821      	st.w      	r1, (sp, 0x4)
    1764:	b802      	st.w      	r0, (sp, 0x8)
	for (i=0;i<8;i++)
    1766:	3100      	movi      	r1, 0
					GPIOA1->CONLR=(GPIOA1->CONLR&0XFF0FFFFF) | 0x00800000;				//COM2
    1768:	1261      	lrw      	r3, 0x2000004c	// 186c <LED_seg_io_initial+0x5c>
    176a:	46d0      	lsli      	r6, r6, 16
    176c:	9360      	ld.w      	r3, (r3, 0)
					GPIOA1->CONLR=(GPIOA1->CONLR&0XFFFF0FFF) | 0x00008000;				//COM0
    176e:	b846      	st.w      	r2, (sp, 0x18)
					GPIOA1->CONLR=(GPIOA1->CONLR&0XFFF0FFFF) | 0x00080000;				//COM1
    1770:	47ec      	lsli      	r7, r7, 12
		if ((LED_COM_EN & (1<<i))!=0)
    1772:	9841      	ld.w      	r2, (sp, 0x4)
    1774:	7086      	asr      	r2, r1
    1776:	3001      	movi      	r0, 1
    1778:	6880      	and      	r2, r0
    177a:	3a40      	cmpnei      	r2, 0
    177c:	0c0f      	bf      	0x179a	// 179a <LED_Control_Config+0x5c>
			switch (i)
    177e:	5903      	subi      	r0, r1, 1
    1780:	3806      	cmphsi      	r0, 7
    1782:	0807      	bt      	0x1790	// 1790 <LED_Control_Config+0x52>
    1784:	e0001d8e 	bsr      	0x52a0	// 52a0 <___gnu_csky_case_uqi>
    1788:	2c26221e 	.long	0x2c26221e
    178c:	003c3731 	.long	0x003c3731
					GPIOA1->CONLR=(GPIOA1->CONLR&0XFFFF0FFF) | 0x00008000;				//COM0
    1790:	9340      	ld.w      	r2, (r3, 0)
    1792:	9806      	ld.w      	r0, (sp, 0x18)
    1794:	6881      	andn      	r2, r0
    1796:	3aaf      	bseti      	r2, r2, 15
					GPIOA1->CONLR=(GPIOA1->CONLR&0XFFF0FFFF) | 0x00080000;				//COM1
    1798:	b340      	st.w      	r2, (r3, 0)
	for (i=0;i<8;i++)
    179a:	2100      	addi      	r1, 1
    179c:	3948      	cmpnei      	r1, 8
    179e:	0bea      	bt      	0x1772	// 1772 <LED_Control_Config+0x34>
					break;
				}
			}
		}
	}
	LED0->CR|=LED_LEDCLK|(0X00<<4)|(0X00<<7)|(LED_COM_EN<<16);
    17a0:	116f      	lrw      	r3, 0x20000018	// 185c <LED_seg_io_initial+0x4c>
    17a2:	9340      	ld.w      	r2, (r3, 0)
    17a4:	9220      	ld.w      	r1, (r2, 0)
    17a6:	9862      	ld.w      	r3, (sp, 0x8)
    17a8:	6c4c      	or      	r1, r3
    17aa:	9861      	ld.w      	r3, (sp, 0x4)
    17ac:	4370      	lsli      	r3, r3, 16
    17ae:	6c4c      	or      	r1, r3
	LED0->BRIGHT=LED_Bright_X;
    17b0:	9863      	ld.w      	r3, (sp, 0xc)
	LED0->CR|=LED_LEDCLK|(0X00<<4)|(0X00<<7)|(LED_COM_EN<<16);
    17b2:	b220      	st.w      	r1, (r2, 0)
	LED0->BRIGHT=LED_Bright_X;
    17b4:	b261      	st.w      	r3, (r2, 0x4)
	LED0->TIMCR=DCOMCNT|(NOVCNT<<8);
    17b6:	9865      	ld.w      	r3, (sp, 0x14)
    17b8:	9824      	ld.w      	r1, (sp, 0x10)
    17ba:	4368      	lsli      	r3, r3, 8
    17bc:	6cc4      	or      	r3, r1
    17be:	b267      	st.w      	r3, (r2, 0x1c)
}
    17c0:	1407      	addi      	sp, sp, 28
    17c2:	1494      	pop      	r4-r7, r15
					GPIOA1->CONLR=(GPIOA1->CONLR&0XFFF0FFFF) | 0x00080000;				//COM1
    17c4:	9340      	ld.w      	r2, (r3, 0)
    17c6:	689d      	andn      	r2, r7
    17c8:	3ab3      	bseti      	r2, r2, 19
    17ca:	07e7      	br      	0x1798	// 1798 <LED_Control_Config+0x5a>
					GPIOA1->CONLR=(GPIOA1->CONLR&0XFF0FFFFF) | 0x00800000;				//COM2
    17cc:	9340      	ld.w      	r2, (r3, 0)
    17ce:	6899      	andn      	r2, r6
    17d0:	3ab7      	bseti      	r2, r2, 23
    17d2:	07e3      	br      	0x1798	// 1798 <LED_Control_Config+0x5a>
					GPIOC0->CONLR=(GPIOC0->CONLR&0XFFFFFFF0) | 0x00000008;				//COM3
    17d4:	9440      	ld.w      	r2, (r4, 0)
    17d6:	300f      	movi      	r0, 15
    17d8:	6881      	andn      	r2, r0
    17da:	3aa3      	bseti      	r2, r2, 3
					GPIOC0->CONLR=(GPIOC0->CONLR&0XFFFFFF0F) | 0x00000080;				//COM4
    17dc:	b440      	st.w      	r2, (r4, 0)
					break;
    17de:	07de      	br      	0x179a	// 179a <LED_Control_Config+0x5c>
					GPIOC0->CONLR=(GPIOC0->CONLR&0XFFFFFF0F) | 0x00000080;				//COM4
    17e0:	9440      	ld.w      	r2, (r4, 0)
    17e2:	30f0      	movi      	r0, 240
    17e4:	6881      	andn      	r2, r0
    17e6:	3aa7      	bseti      	r2, r2, 7
    17e8:	07fa      	br      	0x17dc	// 17dc <LED_Control_Config+0x9e>
					GPIOB0->CONLR=(GPIOB0->CONLR&0XFFFFFFF0) | 0x00000008;				//COM5
    17ea:	9540      	ld.w      	r2, (r5, 0)
    17ec:	300f      	movi      	r0, 15
    17ee:	6881      	andn      	r2, r0
    17f0:	3aa3      	bseti      	r2, r2, 3
					GPIOB0->CONLR=(GPIOB0->CONLR&0XFFFFFF0F) | 0x00000080;				//COM6
    17f2:	b540      	st.w      	r2, (r5, 0)
					break;
    17f4:	07d3      	br      	0x179a	// 179a <LED_Control_Config+0x5c>
					GPIOB0->CONLR=(GPIOB0->CONLR&0XFFFFFF0F) | 0x00000080;				//COM6
    17f6:	9540      	ld.w      	r2, (r5, 0)
    17f8:	30f0      	movi      	r0, 240
    17fa:	6881      	andn      	r2, r0
    17fc:	3aa7      	bseti      	r2, r2, 7
    17fe:	07fa      	br      	0x17f2	// 17f2 <LED_Control_Config+0xb4>
					GPIOA0->CONLR=(GPIOA0->CONLR&0XFFFFFFF0) | 0x00000008;				//COM7
    1800:	9840      	ld.w      	r2, (sp, 0)
    1802:	9240      	ld.w      	r2, (r2, 0)
    1804:	300f      	movi      	r0, 15
    1806:	6881      	andn      	r2, r0
    1808:	3aa3      	bseti      	r2, r2, 3
    180a:	9800      	ld.w      	r0, (sp, 0)
    180c:	b040      	st.w      	r2, (r0, 0)
					break;
    180e:	07c6      	br      	0x179a	// 179a <LED_Control_Config+0x5c>

00001810 <LED_seg_io_initial>:
//LED_IO_G:0,1
//ReturnValue:NONE
/*************************************************************/
void LED_seg_io_initial(LED_SEG_X_TypeDef LED_SEG_X , U8_T LED_IO_G)
{
	if(LED_SEG_X==LED_SEG_0)
    1810:	3841      	cmpnei      	r0, 1
    1812:	0808      	bt      	0x1822	// 1822 <LED_seg_io_initial+0x12>
	{
		GPIOA0->CONLR=(GPIOA0->CONLR&0XFFFFFF0F) | 0x00000080;				//seg0 PA0.1
    1814:	1073      	lrw      	r3, 0x20000050	// 1860 <LED_seg_io_initial+0x50>
		{
			GPIOA0->CONHR=(GPIOA0->CONHR&0XFFFFFF0F) | 0x00000070;			//seg5 PA0.9
		}
		else if(LED_IO_G==1)
		{
			GPIOD0->CONLR=(GPIOD0->CONLR&0XFFFFFF0F) | 0x00000080;			//seg5 PD0.1
    1816:	9340      	ld.w      	r2, (r3, 0)
    1818:	9260      	ld.w      	r3, (r2, 0)
    181a:	31f0      	movi      	r1, 240
    181c:	68c5      	andn      	r3, r1
    181e:	3ba7      	bseti      	r3, r3, 7
    1820:	0441      	br      	0x18a2	// 18a2 <LED_seg_io_initial+0x92>
	else if(LED_SEG_X==LED_SEG_1)
    1822:	3842      	cmpnei      	r0, 2
    1824:	0809      	bt      	0x1836	// 1836 <LED_seg_io_initial+0x26>
		GPIOA0->CONLR=(GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;				//seg1 PA0.2  
    1826:	106f      	lrw      	r3, 0x20000050	// 1860 <LED_seg_io_initial+0x50>
		{
			GPIOA0->CONHR=(GPIOA0->CONHR&0XFFFFF0FF) | 0x00000700;			//seg6 PA0.10
		}
		else if(LED_IO_G==1)
		{
			GPIOC0->CONLR=(GPIOC0->CONLR&0XFFFFF0FF) | 0x00000800;			//seg6 PC0.2
    1828:	9320      	ld.w      	r1, (r3, 0)
    182a:	32f0      	movi      	r2, 240
    182c:	9160      	ld.w      	r3, (r1, 0)
    182e:	4244      	lsli      	r2, r2, 4
    1830:	68c9      	andn      	r3, r2
    1832:	3bab      	bseti      	r3, r3, 11
    1834:	040a      	br      	0x1848	// 1848 <LED_seg_io_initial+0x38>
	else if(LED_SEG_X==LED_SEG_2)
    1836:	3843      	cmpnei      	r0, 3
    1838:	080a      	bt      	0x184c	// 184c <LED_seg_io_initial+0x3c>
		GPIOA0->CONLR=(GPIOA0->CONLR&0XFFFF0FFF) | 0x00008000;				//seg2 PA0.3 SWCLK
    183a:	106a      	lrw      	r3, 0x20000050	// 1860 <LED_seg_io_initial+0x50>
    183c:	32f0      	movi      	r2, 240
    183e:	9320      	ld.w      	r1, (r3, 0)
    1840:	9160      	ld.w      	r3, (r1, 0)
    1842:	4248      	lsli      	r2, r2, 8
    1844:	68c9      	andn      	r3, r2
    1846:	3baf      	bseti      	r3, r3, 15
			GPIOC0->CONLR=(GPIOC0->CONLR&0XFFFFF0FF) | 0x00000800;			//seg6 PC0.2
    1848:	b160      	st.w      	r3, (r1, 0)
    184a:	042d      	br      	0x18a4	// 18a4 <LED_seg_io_initial+0x94>
	else if(LED_SEG_X==LED_SEG_3)
    184c:	3844      	cmpnei      	r0, 4
    184e:	0815      	bt      	0x1878	// 1878 <LED_seg_io_initial+0x68>
		GPIOA0->CONLR=(GPIOA0->CONLR&0XFFF0FFFF) | 0x00080000;				//seg3 PA0.4 SWDIO
    1850:	1064      	lrw      	r3, 0x20000050	// 1860 <LED_seg_io_initial+0x50>
    1852:	32f0      	movi      	r2, 240
    1854:	9320      	ld.w      	r1, (r3, 0)
    1856:	9160      	ld.w      	r3, (r1, 0)
    1858:	040c      	br      	0x1870	// 1870 <LED_seg_io_initial+0x60>
    185a:	0000      	bkpt
    185c:	20000018 	.long	0x20000018
    1860:	20000050 	.long	0x20000050
    1864:	20000048 	.long	0x20000048
    1868:	20000044 	.long	0x20000044
    186c:	2000004c 	.long	0x2000004c
    1870:	424c      	lsli      	r2, r2, 12
    1872:	68c9      	andn      	r3, r2
    1874:	3bb3      	bseti      	r3, r3, 19
    1876:	07e9      	br      	0x1848	// 1848 <LED_seg_io_initial+0x38>
	else if(LED_SEG_X==LED_SEG_4)
    1878:	3845      	cmpnei      	r0, 5
    187a:	0816      	bt      	0x18a6	// 18a6 <LED_seg_io_initial+0x96>
		if(LED_IO_G==0)
    187c:	3940      	cmpnei      	r1, 0
    187e:	080a      	bt      	0x1892	// 1892 <LED_seg_io_initial+0x82>
			GPIOA0->CONHR=(GPIOA0->CONHR&0XFFFFFFF0) | 0x00000007;			//seg4 PA0.8
    1880:	117c      	lrw      	r3, 0x20000050	// 1970 <LED_Int_Disable+0x14>
    1882:	310f      	movi      	r1, 15
    1884:	9340      	ld.w      	r2, (r3, 0)
    1886:	9261      	ld.w      	r3, (r2, 0x4)
    1888:	68c5      	andn      	r3, r1
    188a:	3107      	movi      	r1, 7
			GPIOA0->CONHR=(GPIOA0->CONHR&0XFFFFFF0F) | 0x00000070;			//seg5 PA0.9
    188c:	6cc4      	or      	r3, r1
		}
	}
	else if(LED_SEG_X==LED_SEG_7)
	{
		GPIOA0->CONHR=(GPIOA0->CONHR&0X0FFFFFFF) | 0x80000000;				//seg7 PA0.15
    188e:	b261      	st.w      	r3, (r2, 0x4)
	}
}
    1890:	040a      	br      	0x18a4	// 18a4 <LED_seg_io_initial+0x94>
		else if(LED_IO_G==1)
    1892:	3941      	cmpnei      	r1, 1
    1894:	0808      	bt      	0x18a4	// 18a4 <LED_seg_io_initial+0x94>
			GPIOD0->CONLR=(GPIOD0->CONLR&0XFFFFFFF0) | 0x00000008;			//seg4 PD0.0
    1896:	1178      	lrw      	r3, 0x20000040	// 1974 <LED_Int_Disable+0x18>
    1898:	310f      	movi      	r1, 15
    189a:	9340      	ld.w      	r2, (r3, 0)
    189c:	9260      	ld.w      	r3, (r2, 0)
    189e:	68c5      	andn      	r3, r1
    18a0:	3ba3      	bseti      	r3, r3, 3
    18a2:	b260      	st.w      	r3, (r2, 0)
}
    18a4:	783c      	rts
	else if(LED_SEG_X==LED_SEG_5)
    18a6:	3846      	cmpnei      	r0, 6
    18a8:	080e      	bt      	0x18c4	// 18c4 <LED_seg_io_initial+0xb4>
		if(LED_IO_G==0)
    18aa:	3940      	cmpnei      	r1, 0
    18ac:	0808      	bt      	0x18bc	// 18bc <LED_seg_io_initial+0xac>
			GPIOA0->CONHR=(GPIOA0->CONHR&0XFFFFFF0F) | 0x00000070;			//seg5 PA0.9
    18ae:	1171      	lrw      	r3, 0x20000050	// 1970 <LED_Int_Disable+0x14>
    18b0:	31f0      	movi      	r1, 240
    18b2:	9340      	ld.w      	r2, (r3, 0)
    18b4:	9261      	ld.w      	r3, (r2, 0x4)
    18b6:	68c5      	andn      	r3, r1
    18b8:	3170      	movi      	r1, 112
    18ba:	07e9      	br      	0x188c	// 188c <LED_seg_io_initial+0x7c>
		else if(LED_IO_G==1)
    18bc:	3941      	cmpnei      	r1, 1
    18be:	0bf3      	bt      	0x18a4	// 18a4 <LED_seg_io_initial+0x94>
			GPIOD0->CONLR=(GPIOD0->CONLR&0XFFFFFF0F) | 0x00000080;			//seg5 PD0.1
    18c0:	116d      	lrw      	r3, 0x20000040	// 1974 <LED_Int_Disable+0x18>
    18c2:	07aa      	br      	0x1816	// 1816 <LED_seg_io_initial+0x6>
	else if(LED_SEG_X==LED_SEG_6)
    18c4:	3847      	cmpnei      	r0, 7
    18c6:	0812      	bt      	0x18ea	// 18ea <LED_seg_io_initial+0xda>
		if(LED_IO_G==0)
    18c8:	3940      	cmpnei      	r1, 0
    18ca:	080c      	bt      	0x18e2	// 18e2 <LED_seg_io_initial+0xd2>
			GPIOA0->CONHR=(GPIOA0->CONHR&0XFFFFF0FF) | 0x00000700;			//seg6 PA0.10
    18cc:	1169      	lrw      	r3, 0x20000050	// 1970 <LED_Int_Disable+0x14>
    18ce:	32f0      	movi      	r2, 240
    18d0:	9320      	ld.w      	r1, (r3, 0)
    18d2:	9161      	ld.w      	r3, (r1, 0x4)
    18d4:	4244      	lsli      	r2, r2, 4
    18d6:	68c9      	andn      	r3, r2
    18d8:	32e0      	movi      	r2, 224
    18da:	4243      	lsli      	r2, r2, 3
    18dc:	6cc8      	or      	r3, r2
    18de:	b161      	st.w      	r3, (r1, 0x4)
    18e0:	07e2      	br      	0x18a4	// 18a4 <LED_seg_io_initial+0x94>
		else if(LED_IO_G==1)
    18e2:	3941      	cmpnei      	r1, 1
    18e4:	0be0      	bt      	0x18a4	// 18a4 <LED_seg_io_initial+0x94>
			GPIOC0->CONLR=(GPIOC0->CONLR&0XFFFFF0FF) | 0x00000800;			//seg6 PC0.2
    18e6:	1165      	lrw      	r3, 0x20000044	// 1978 <LED_Int_Disable+0x1c>
    18e8:	07a0      	br      	0x1828	// 1828 <LED_seg_io_initial+0x18>
	else if(LED_SEG_X==LED_SEG_7)
    18ea:	3848      	cmpnei      	r0, 8
    18ec:	0bdc      	bt      	0x18a4	// 18a4 <LED_seg_io_initial+0x94>
		GPIOA0->CONHR=(GPIOA0->CONHR&0X0FFFFFFF) | 0x80000000;				//seg7 PA0.15
    18ee:	1161      	lrw      	r3, 0x20000050	// 1970 <LED_Int_Disable+0x14>
    18f0:	9340      	ld.w      	r2, (r3, 0)
    18f2:	9261      	ld.w      	r3, (r2, 0x4)
    18f4:	4364      	lsli      	r3, r3, 4
    18f6:	4b64      	lsri      	r3, r3, 4
    18f8:	3bbf      	bseti      	r3, r3, 31
    18fa:	07ca      	br      	0x188e	// 188e <LED_seg_io_initial+0x7e>

000018fc <LED_INT_CMD>:
/*************************************************************/  
  //ICEND:Interrupt Masking Enable/Disable for One COM scan cycle completing
  //IPEND:Interrupt Masking Enable/Disable for All COM scan cycle is completing
void LED_INT_CMD(LED_INT_TypeDef LED_INT_x , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
    18fc:	3940      	cmpnei      	r1, 0
    18fe:	1160      	lrw      	r3, 0x20000018	// 197c <LED_Int_Disable+0x20>
    1900:	0c06      	bf      	0x190c	// 190c <LED_INT_CMD+0x10>
	{
		LED0->IMCR  |= LED_INT_x;						//ENABLE
    1902:	9340      	ld.w      	r2, (r3, 0)
    1904:	9263      	ld.w      	r3, (r2, 0xc)
    1906:	6c0c      	or      	r0, r3
    1908:	b203      	st.w      	r0, (r2, 0xc)
	}
	else
	{
		LED0->IMCR  &= ~LED_INT_x;						//DIABLE
	}
}  
    190a:	783c      	rts
		LED0->IMCR  &= ~LED_INT_x;						//DIABLE
    190c:	9360      	ld.w      	r3, (r3, 0)
    190e:	9343      	ld.w      	r2, (r3, 0xc)
    1910:	6c02      	nor      	r0, r0
    1912:	6808      	and      	r0, r2
    1914:	b303      	st.w      	r0, (r3, 0xc)
}  
    1916:	07fa      	br      	0x190a	// 190a <LED_INT_CMD+0xe>

00001918 <LED_SEGDATX_data_write>:
//SEGDATX:SEGDAT_NUM0,SEGDAT_NUM1,SEGDAT_NUM2,SEGDAT_NUM3,SEGDAT_NUM4,SEGDAT_NUM5,SEGDAT_NUM6,SEGDAT_NUM7s
//SEGDATX_data:VALUE=1~0XFF
//ReturnValue:NONE
/*************************************************************/  
void LED_SEGDATX_data_write(LED_SEGDATX_TypeDef SEGDATX , U8_T SEGDATX_data)
{
    1918:	14d0      	push      	r15
	switch(SEGDATX)
    191a:	3807      	cmphsi      	r0, 8
    191c:	080a      	bt      	0x1930	// 1930 <LED_SEGDATX_data_write+0x18>
    191e:	1078      	lrw      	r3, 0x20000018	// 197c <LED_Int_Disable+0x20>
			break;
		case SEGDAT_NUM6:
			LED0->SEGDATA6=SEGDATX_data;
			break;
		case SEGDAT_NUM7:
			LED0->SEGDATA7=SEGDATX_data;
    1920:	9360      	ld.w      	r3, (r3, 0)
	switch(SEGDATX)
    1922:	e0001cbf 	bsr      	0x52a0	// 52a0 <___gnu_csky_case_uqi>
    1926:	0604      	.short	0x0604
    1928:	0e0c0a08 	.long	0x0e0c0a08
    192c:	1210      	.short	0x1210
			LED0->SEGDATA0=SEGDATX_data;
    192e:	b32b      	st.w      	r1, (r3, 0x2c)
			break;
	}		
} 
    1930:	1490      	pop      	r15
			LED0->SEGDATA1=SEGDATX_data;
    1932:	b32c      	st.w      	r1, (r3, 0x30)
			break;
    1934:	07fe      	br      	0x1930	// 1930 <LED_SEGDATX_data_write+0x18>
			LED0->SEGDATA2=SEGDATX_data;
    1936:	b32d      	st.w      	r1, (r3, 0x34)
			break;
    1938:	07fc      	br      	0x1930	// 1930 <LED_SEGDATX_data_write+0x18>
			LED0->SEGDATA3=SEGDATX_data;
    193a:	b32e      	st.w      	r1, (r3, 0x38)
			break;
    193c:	07fa      	br      	0x1930	// 1930 <LED_SEGDATX_data_write+0x18>
			LED0->SEGDATA4=SEGDATX_data;
    193e:	b32f      	st.w      	r1, (r3, 0x3c)
			break;
    1940:	07f8      	br      	0x1930	// 1930 <LED_SEGDATX_data_write+0x18>
			LED0->SEGDATA5=SEGDATX_data;
    1942:	b330      	st.w      	r1, (r3, 0x40)
			break;
    1944:	07f6      	br      	0x1930	// 1930 <LED_SEGDATX_data_write+0x18>
			LED0->SEGDATA6=SEGDATX_data;
    1946:	b331      	st.w      	r1, (r3, 0x44)
			break;
    1948:	07f4      	br      	0x1930	// 1930 <LED_SEGDATX_data_write+0x18>
			LED0->SEGDATA7=SEGDATX_data;
    194a:	b332      	st.w      	r1, (r3, 0x48)
} 
    194c:	07f2      	br      	0x1930	// 1930 <LED_SEGDATX_data_write+0x18>

0000194e <LED_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LED_Int_Enable(void)
{
    INTC_ISER_WRITE(LED_INT);    
    194e:	106d      	lrw      	r3, 0x20000064	// 1980 <LED_Int_Disable+0x24>
    1950:	3280      	movi      	r2, 128
    1952:	9360      	ld.w      	r3, (r3, 0)
    1954:	23ff      	addi      	r3, 256
    1956:	4254      	lsli      	r2, r2, 20
    1958:	b340      	st.w      	r2, (r3, 0)
}
    195a:	783c      	rts

0000195c <LED_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LED_Int_Disable(void)
{
    INTC_ICER_WRITE(LED_INT);    
    195c:	1069      	lrw      	r3, 0x20000064	// 1980 <LED_Int_Disable+0x24>
    195e:	32c0      	movi      	r2, 192
    1960:	9360      	ld.w      	r3, (r3, 0)
    1962:	4241      	lsli      	r2, r2, 1
    1964:	60c8      	addu      	r3, r2
    1966:	3280      	movi      	r2, 128
    1968:	4254      	lsli      	r2, r2, 20
    196a:	b340      	st.w      	r2, (r3, 0)
} 
    196c:	783c      	rts
    196e:	0000      	bkpt
    1970:	20000050 	.long	0x20000050
    1974:	20000040 	.long	0x20000040
    1978:	20000044 	.long	0x20000044
    197c:	20000018 	.long	0x20000018
    1980:	20000064 	.long	0x20000064

00001984 <OPA_RESET_VALUE>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void OPA_RESET_VALUE(void)
{
		OAMP->CR0=OPA0_CR_RST;     					/**< OPA0_CR  reset value   */
    1984:	1064      	lrw      	r3, 0x20000000	// 1994 <OPA_RESET_VALUE+0x10>
    1986:	3200      	movi      	r2, 0
    1988:	9360      	ld.w      	r3, (r3, 0)
    198a:	b340      	st.w      	r2, (r3, 0)
		OAMP->CR1=OPA1_CR_RST;     					/**< OPA1_CR  reset value  	*/
    198c:	b341      	st.w      	r2, (r3, 0x4)
		OAMP->GATR0=OPA0_GATR_RST;					/**< OPA0_GATR reset value  */
    198e:	b342      	st.w      	r2, (r3, 0x8)
		OAMP->GATR1=OPA1_GATR_RST;     				/**< OPA1_GATR reset value  */
    1990:	b343      	st.w      	r2, (r3, 0xc)
}
    1992:	783c      	rts
    1994:	20000000 	.long	0x20000000

00001998 <OPA_IO_Init>:
//OPA1P(0->PA1.0(AF7))),OPA1N(0->PA1.2(AF7))),OPA1X(0->PA1.1(AF7)))
//ReturnValue:NONE
/*************************************************************/  
void OPA_IO_Init(OPA_IO_MODE_TypeDef  OPA_IO_MODE_X , U8_T OPA_IO_G )
{
	if(OPA_IO_MODE_X==OPA0P)
    1998:	3841      	cmpnei      	r0, 1
    199a:	080d      	bt      	0x19b4	// 19b4 <OPA_IO_Init+0x1c>
	{
		if(OPA_IO_G==0)
    199c:	3940      	cmpnei      	r1, 0
    199e:	080a      	bt      	0x19b2	// 19b2 <OPA_IO_Init+0x1a>
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFF0FFFF)|0x000A0000;										//OPA0P(PA1.4->AF7)
    19a0:	126f      	lrw      	r3, 0x2000004c	// 1adc <OPA_Config_Prg+0x76>
    19a2:	32f0      	movi      	r2, 240
    19a4:	9320      	ld.w      	r1, (r3, 0)
    19a6:	9160      	ld.w      	r3, (r1, 0)
    19a8:	424c      	lsli      	r2, r2, 12
    19aa:	68c9      	andn      	r3, r2
    19ac:	3bb1      	bseti      	r3, r3, 17
    19ae:	3bb3      	bseti      	r3, r3, 19
	}
	else if(OPA_IO_MODE_X==OPA0N)
	{
		if(OPA_IO_G==0)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00A00000;										//OPA0N(PA1.5->AF7)
    19b0:	b160      	st.w      	r3, (r1, 0)
		if(OPA_IO_G==0)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFF0F)|0x000000A0;										//OPA1X(PA1.1->AF7)
		}
	}
}
    19b2:	783c      	rts
	else if(OPA_IO_MODE_X==OPA0N)
    19b4:	3842      	cmpnei      	r0, 2
    19b6:	080c      	bt      	0x19ce	// 19ce <OPA_IO_Init+0x36>
		if(OPA_IO_G==0)
    19b8:	3940      	cmpnei      	r1, 0
    19ba:	0bfc      	bt      	0x19b2	// 19b2 <OPA_IO_Init+0x1a>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00A00000;										//OPA0N(PA1.5->AF7)
    19bc:	1268      	lrw      	r3, 0x2000004c	// 1adc <OPA_Config_Prg+0x76>
    19be:	32f0      	movi      	r2, 240
    19c0:	9320      	ld.w      	r1, (r3, 0)
    19c2:	9160      	ld.w      	r3, (r1, 0)
    19c4:	4250      	lsli      	r2, r2, 16
    19c6:	68c9      	andn      	r3, r2
    19c8:	3bb5      	bseti      	r3, r3, 21
    19ca:	3bb7      	bseti      	r3, r3, 23
    19cc:	07f2      	br      	0x19b0	// 19b0 <OPA_IO_Init+0x18>
	else if(OPA_IO_MODE_X==OPA0X)
    19ce:	3843      	cmpnei      	r0, 3
    19d0:	080c      	bt      	0x19e8	// 19e8 <OPA_IO_Init+0x50>
		if(OPA_IO_G==0)
    19d2:	3940      	cmpnei      	r1, 0
    19d4:	0bef      	bt      	0x19b2	// 19b2 <OPA_IO_Init+0x1a>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFF0FFF)|0x0000A000;										//OPA0X(PA1.3->AF7)
    19d6:	1262      	lrw      	r3, 0x2000004c	// 1adc <OPA_Config_Prg+0x76>
    19d8:	32f0      	movi      	r2, 240
    19da:	9320      	ld.w      	r1, (r3, 0)
    19dc:	9160      	ld.w      	r3, (r1, 0)
    19de:	4248      	lsli      	r2, r2, 8
    19e0:	68c9      	andn      	r3, r2
    19e2:	3bad      	bseti      	r3, r3, 13
    19e4:	3baf      	bseti      	r3, r3, 15
    19e6:	07e5      	br      	0x19b0	// 19b0 <OPA_IO_Init+0x18>
	else if(OPA_IO_MODE_X==OPA1P)
    19e8:	3844      	cmpnei      	r0, 4
    19ea:	080c      	bt      	0x1a02	// 1a02 <OPA_IO_Init+0x6a>
		if(OPA_IO_G==0)
    19ec:	3940      	cmpnei      	r1, 0
    19ee:	0be2      	bt      	0x19b2	// 19b2 <OPA_IO_Init+0x1a>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFFF0)|0x0000000A;										//OPA1P(PA1.0->AF7)
    19f0:	117b      	lrw      	r3, 0x2000004c	// 1adc <OPA_Config_Prg+0x76>
    19f2:	310f      	movi      	r1, 15
    19f4:	9340      	ld.w      	r2, (r3, 0)
    19f6:	9260      	ld.w      	r3, (r2, 0)
    19f8:	68c5      	andn      	r3, r1
    19fa:	3ba1      	bseti      	r3, r3, 1
    19fc:	3ba3      	bseti      	r3, r3, 3
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFF0F)|0x000000A0;										//OPA1X(PA1.1->AF7)
    19fe:	b260      	st.w      	r3, (r2, 0)
}
    1a00:	07d9      	br      	0x19b2	// 19b2 <OPA_IO_Init+0x1a>
	else if(OPA_IO_MODE_X==OPA1N)
    1a02:	3845      	cmpnei      	r0, 5
    1a04:	080c      	bt      	0x1a1c	// 1a1c <OPA_IO_Init+0x84>
		if(OPA_IO_G==0)
    1a06:	3940      	cmpnei      	r1, 0
    1a08:	0bd5      	bt      	0x19b2	// 19b2 <OPA_IO_Init+0x1a>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFF0FF)|0x00000A00;										//OPA1N(PA1.2->AF7)
    1a0a:	1175      	lrw      	r3, 0x2000004c	// 1adc <OPA_Config_Prg+0x76>
    1a0c:	32f0      	movi      	r2, 240
    1a0e:	9320      	ld.w      	r1, (r3, 0)
    1a10:	9160      	ld.w      	r3, (r1, 0)
    1a12:	4244      	lsli      	r2, r2, 4
    1a14:	68c9      	andn      	r3, r2
    1a16:	3ba9      	bseti      	r3, r3, 9
    1a18:	3bab      	bseti      	r3, r3, 11
    1a1a:	07cb      	br      	0x19b0	// 19b0 <OPA_IO_Init+0x18>
	else if(OPA_IO_MODE_X==OPA1X)
    1a1c:	3846      	cmpnei      	r0, 6
    1a1e:	0bca      	bt      	0x19b2	// 19b2 <OPA_IO_Init+0x1a>
		if(OPA_IO_G==0)
    1a20:	3940      	cmpnei      	r1, 0
    1a22:	0bc8      	bt      	0x19b2	// 19b2 <OPA_IO_Init+0x1a>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFF0F)|0x000000A0;										//OPA1X(PA1.1->AF7)
    1a24:	116e      	lrw      	r3, 0x2000004c	// 1adc <OPA_Config_Prg+0x76>
    1a26:	31f0      	movi      	r1, 240
    1a28:	9340      	ld.w      	r2, (r3, 0)
    1a2a:	9260      	ld.w      	r3, (r2, 0)
    1a2c:	68c5      	andn      	r3, r1
    1a2e:	3ba5      	bseti      	r3, r3, 5
    1a30:	3ba7      	bseti      	r3, r3, 7
    1a32:	07e6      	br      	0x19fe	// 19fe <OPA_IO_Init+0x66>

00001a34 <OPA_EN_CMD>:
//OPAx_NUM:OPA0_NUM,OPA1_NUM,
//
/*************************************************************/  
void OPA_EN_CMD(OPAx_selecte_TypeDef OPAx_NUM , FunctionalStatus NewState)
{
	if(OPAx_NUM==OPA0_NUM)
    1a34:	3840      	cmpnei      	r0, 0
    1a36:	080b      	bt      	0x1a4c	// 1a4c <OPA_EN_CMD+0x18>
    1a38:	116a      	lrw      	r3, 0x20000000	// 1ae0 <OPA_Config_Prg+0x7a>
	{
		if (NewState != DISABLE)
    1a3a:	3940      	cmpnei      	r1, 0
		{
			OAMP->CR0|=0X01;								//Enable
    1a3c:	9340      	ld.w      	r2, (r3, 0)
    1a3e:	9260      	ld.w      	r3, (r2, 0)
		if (NewState != DISABLE)
    1a40:	0c04      	bf      	0x1a48	// 1a48 <OPA_EN_CMD+0x14>
			OAMP->CR0|=0X01;								//Enable
    1a42:	3ba0      	bseti      	r3, r3, 0
		}
		else
		{
			OAMP->CR0&=0XFFFFFFFE;						//Disable
    1a44:	b260      	st.w      	r3, (r2, 0)
		else
		{
			OAMP->CR1&=0XFFFFFFFE;						//Disablev
		}
	}
}
    1a46:	783c      	rts
			OAMP->CR0&=0XFFFFFFFE;						//Disable
    1a48:	3b80      	bclri      	r3, r3, 0
    1a4a:	07fd      	br      	0x1a44	// 1a44 <OPA_EN_CMD+0x10>
	else if(OPAx_NUM==OPA1_NUM)
    1a4c:	3841      	cmpnei      	r0, 1
    1a4e:	0bfc      	bt      	0x1a46	// 1a46 <OPA_EN_CMD+0x12>
    1a50:	1164      	lrw      	r3, 0x20000000	// 1ae0 <OPA_Config_Prg+0x7a>
		if (NewState != DISABLE)
    1a52:	3940      	cmpnei      	r1, 0
			OAMP->CR1|=0X01;								//Enable
    1a54:	9340      	ld.w      	r2, (r3, 0)
    1a56:	9261      	ld.w      	r3, (r2, 0x4)
		if (NewState != DISABLE)
    1a58:	0c04      	bf      	0x1a60	// 1a60 <OPA_EN_CMD+0x2c>
			OAMP->CR1|=0X01;								//Enable
    1a5a:	6c0c      	or      	r0, r3
    1a5c:	b201      	st.w      	r0, (r2, 0x4)
    1a5e:	07f4      	br      	0x1a46	// 1a46 <OPA_EN_CMD+0x12>
			OAMP->CR1&=0XFFFFFFFE;						//Disablev
    1a60:	3b80      	bclri      	r3, r3, 0
    1a62:	b261      	st.w      	r3, (r2, 0x4)
}
    1a64:	07f1      	br      	0x1a46	// 1a46 <OPA_EN_CMD+0x12>

00001a66 <OPA_Config_Prg>:
//PGAC_Set:0~7 OPA0(0->x1,1->x2,2->x3,3->x4,4->x5,5->x6,6->x7,7->x8); OPA1(0->x1,1->x10,2->x20,3->x40,4->x60,5->x80,6->x100,7->x120)
//GATRM_Set:0~15 (微调参参数,值越大放大倍速相应减小)
//ReturnValue:NONE
/*************************************************************/  
void OPA_Config_Prg(OPAx_selecte_TypeDef OPAx_NUM , PGAEN_CMD_TypeDef PGAEN_CMD_x , Op_ExtPinConnect_TypeDef Op_ExtPinConnect_X  , U8_T IPSEL_SET_x , U8_T PGAC_Set , U8_T GATRM_Set)
{
    1a66:	14c3      	push      	r4-r6
	if(OPAx_NUM==OPA0_NUM)
    1a68:	3840      	cmpnei      	r0, 0
{
    1a6a:	d88e000c 	ld.b      	r4, (sp, 0xc)
    1a6e:	d8ae0010 	ld.b      	r5, (sp, 0x10)
	if(OPAx_NUM==OPA0_NUM)
    1a72:	0819      	bt      	0x1aa4	// 1aa4 <OPA_Config_Prg+0x3e>
	{
		if(Op_ExtPinConnect_X==Op_ExtPinConnect_EN)
    1a74:	3a41      	cmpnei      	r2, 1
    1a76:	101b      	lrw      	r0, 0x20000000	// 1ae0 <OPA_Config_Prg+0x7a>
    1a78:	0811      	bt      	0x1a9a	// 1a9a <OPA_Config_Prg+0x34>
		{
			OAMP->GATR0=0xA77A << 16|GATRM_Set|0x08;
    1a7a:	90c0      	ld.w      	r6, (r0, 0)
    1a7c:	105a      	lrw      	r2, 0xa77a0008	// 1ae4 <OPA_Config_Prg+0x7e>
		}
		if(Op_ExtPinConnect_X==Op_ExtPinConnect_DIS)
		{
			OAMP->GATR0=0xA77A << 16|GATRM_Set;
    1a7e:	6d48      	or      	r5, r2
    1a80:	b6a2      	st.w      	r5, (r6, 0x8)
		}
		OAMP->CR0=(OAMP->CR0 & 0XFFFFFCE1)|(PGAEN_CMD_x<<1)|(IPSEL_SET_x<<8)|(PGAC_Set<<2);
    1a82:	9040      	ld.w      	r2, (r0, 0)
    1a84:	4482      	lsli      	r4, r4, 2
    1a86:	4121      	lsli      	r1, r1, 1
    1a88:	9200      	ld.w      	r0, (r2, 0)
    1a8a:	6c50      	or      	r1, r4
    1a8c:	1097      	lrw      	r4, 0x31e	// 1ae8 <OPA_Config_Prg+0x82>
    1a8e:	6811      	andn      	r0, r4
    1a90:	6c40      	or      	r1, r0
    1a92:	4368      	lsli      	r3, r3, 8
    1a94:	6cc4      	or      	r3, r1
    1a96:	b260      	st.w      	r3, (r2, 0)
		{
			OAMP->GATR1=0xA77A << 16|GATRM_Set;
		}
		OAMP->CR1=(OAMP->CR1 & 0XFFFFFCE1)|(PGAEN_CMD_x<<1)|(IPSEL_SET_x<<8)|(PGAC_Set<<2);
	}
}
    1a98:	1483      	pop      	r4-r6
		if(Op_ExtPinConnect_X==Op_ExtPinConnect_DIS)
    1a9a:	3a40      	cmpnei      	r2, 0
    1a9c:	0bf3      	bt      	0x1a82	// 1a82 <OPA_Config_Prg+0x1c>
			OAMP->GATR0=0xA77A << 16|GATRM_Set;
    1a9e:	90c0      	ld.w      	r6, (r0, 0)
    1aa0:	1053      	lrw      	r2, 0xa77a0000	// 1aec <OPA_Config_Prg+0x86>
    1aa2:	07ee      	br      	0x1a7e	// 1a7e <OPA_Config_Prg+0x18>
	else if(OPAx_NUM==OPA1_NUM)
    1aa4:	3841      	cmpnei      	r0, 1
    1aa6:	0bf9      	bt      	0x1a98	// 1a98 <OPA_Config_Prg+0x32>
		if(Op_ExtPinConnect_X==Op_ExtPinConnect_EN)
    1aa8:	3a41      	cmpnei      	r2, 1
    1aaa:	100e      	lrw      	r0, 0x20000000	// 1ae0 <OPA_Config_Prg+0x7a>
    1aac:	0811      	bt      	0x1ace	// 1ace <OPA_Config_Prg+0x68>
			OAMP->GATR1=0xA77A << 16|GATRM_Set|0x08;
    1aae:	104e      	lrw      	r2, 0xa77a0008	// 1ae4 <OPA_Config_Prg+0x7e>
    1ab0:	90c0      	ld.w      	r6, (r0, 0)
    1ab2:	6d48      	or      	r5, r2
    1ab4:	b6a3      	st.w      	r5, (r6, 0xc)
		OAMP->CR1=(OAMP->CR1 & 0XFFFFFCE1)|(PGAEN_CMD_x<<1)|(IPSEL_SET_x<<8)|(PGAC_Set<<2);
    1ab6:	9040      	ld.w      	r2, (r0, 0)
    1ab8:	4482      	lsli      	r4, r4, 2
    1aba:	4121      	lsli      	r1, r1, 1
    1abc:	9201      	ld.w      	r0, (r2, 0x4)
    1abe:	6c50      	or      	r1, r4
    1ac0:	108a      	lrw      	r4, 0x31e	// 1ae8 <OPA_Config_Prg+0x82>
    1ac2:	6811      	andn      	r0, r4
    1ac4:	6c40      	or      	r1, r0
    1ac6:	4368      	lsli      	r3, r3, 8
    1ac8:	6cc4      	or      	r3, r1
    1aca:	b261      	st.w      	r3, (r2, 0x4)
}
    1acc:	07e6      	br      	0x1a98	// 1a98 <OPA_Config_Prg+0x32>
		if(Op_ExtPinConnect_X==Op_ExtPinConnect_DIS)
    1ace:	3a40      	cmpnei      	r2, 0
    1ad0:	0bf3      	bt      	0x1ab6	// 1ab6 <OPA_Config_Prg+0x50>
			OAMP->GATR1=0xA77A << 16|GATRM_Set;
    1ad2:	10c7      	lrw      	r6, 0xa77a0000	// 1aec <OPA_Config_Prg+0x86>
    1ad4:	9040      	ld.w      	r2, (r0, 0)
    1ad6:	6d58      	or      	r5, r6
    1ad8:	b2a3      	st.w      	r5, (r2, 0xc)
    1ada:	07ee      	br      	0x1ab6	// 1ab6 <OPA_Config_Prg+0x50>
    1adc:	2000004c 	.long	0x2000004c
    1ae0:	20000000 	.long	0x20000000
    1ae4:	a77a0008 	.long	0xa77a0008
    1ae8:	0000031e 	.long	0x0000031e
    1aec:	a77a0000 	.long	0xa77a0000

00001af0 <SYSCON_General_CMD.part.0>:
/*************************************************************/  
void SYSCON_General_CMD(FunctionalStatus NewState, SYSCON_General_CMD_TypeDef ENDIS_X )
{
	if (NewState != DISABLE)
	{
		if(ENDIS_X==ENDIS_EMOSC) 
    1af0:	3848      	cmpnei      	r0, 8
    1af2:	080a      	bt      	0x1b06	// 1b06 <SYSCON_General_CMD.part.0+0x16>
		GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFF00F)|0x00000440;					//使能对应PIN
    1af4:	1076      	lrw      	r3, 0x20000050	// 1b4c <SYSCON_General_CMD.part.0+0x5c>
    1af6:	32ff      	movi      	r2, 255
    1af8:	9320      	ld.w      	r1, (r3, 0)
    1afa:	9160      	ld.w      	r3, (r1, 0)
    1afc:	4244      	lsli      	r2, r2, 4
    1afe:	68c9      	andn      	r3, r2
    1b00:	3ba6      	bseti      	r3, r3, 6
    1b02:	3baa      	bseti      	r3, r3, 10
    1b04:	b160      	st.w      	r3, (r1, 0)
		SYSCON->GCER=ENDIS_X;													//enable SYSCON General Control
    1b06:	1073      	lrw      	r3, 0x2000005c	// 1b50 <SYSCON_General_CMD.part.0+0x60>
    1b08:	9340      	ld.w      	r2, (r3, 0)
    1b0a:	b201      	st.w      	r0, (r2, 0x4)
		while(!(SYSCON->GCSR&ENDIS_X));											//check  Enable?	
    1b0c:	9263      	ld.w      	r3, (r2, 0xc)
    1b0e:	68c0      	and      	r3, r0
    1b10:	3b40      	cmpnei      	r3, 0
    1b12:	0ffd      	bf      	0x1b0c	// 1b0c <SYSCON_General_CMD.part.0+0x1c>
		switch(ENDIS_X)
    1b14:	3842      	cmpnei      	r0, 2
    1b16:	0808      	bt      	0x1b26	// 1b26 <SYSCON_General_CMD.part.0+0x36>
		{
			case ENDIS_IMOSC:
				while(!SYSCON_IMOSCSTFlag); 
    1b18:	106f      	lrw      	r3, 0x20000068	// 1b54 <SYSCON_General_CMD.part.0+0x64>
    1b1a:	8340      	ld.b      	r2, (r3, 0)
    1b1c:	3a40      	cmpnei      	r2, 0
    1b1e:	0ffe      	bf      	0x1b1a	// 1b1a <SYSCON_General_CMD.part.0+0x2a>
				SYSCON_IMOSCSTFlag=0;				// Wait IMOSC stable interrupt
    1b20:	3200      	movi      	r2, 0
    1b22:	a340      	st.b      	r2, (r3, 0)
	else
	{
		SYSCON->GCDR=ENDIS_X;													//disable SYSCON General Control
		while(SYSCON->GCSR&ENDIS_X);											//check  Disable?
	}
}
    1b24:	783c      	rts
		switch(ENDIS_X)
    1b26:	3848      	cmpnei      	r0, 8
    1b28:	0808      	bt      	0x1b38	// 1b38 <SYSCON_General_CMD.part.0+0x48>
				while(!SYSCON_EMOSCSTFlag); 
    1b2a:	106b      	lrw      	r3, 0x20000068	// 1b54 <SYSCON_General_CMD.part.0+0x64>
    1b2c:	8341      	ld.b      	r2, (r3, 0x1)
    1b2e:	3a40      	cmpnei      	r2, 0
    1b30:	0ffe      	bf      	0x1b2c	// 1b2c <SYSCON_General_CMD.part.0+0x3c>
				SYSCON_EMOSCSTFlag=0;				// Wait EMOSC stable interrupt	
    1b32:	3200      	movi      	r2, 0
    1b34:	a341      	st.b      	r2, (r3, 0x1)
    1b36:	07f7      	br      	0x1b24	// 1b24 <SYSCON_General_CMD.part.0+0x34>
		switch(ENDIS_X)
    1b38:	3841      	cmpnei      	r0, 1
    1b3a:	0bf5      	bt      	0x1b24	// 1b24 <SYSCON_General_CMD.part.0+0x34>
				while(!SYSCON_ISOSCSTFlag); 
    1b3c:	1066      	lrw      	r3, 0x20000068	// 1b54 <SYSCON_General_CMD.part.0+0x64>
    1b3e:	8342      	ld.b      	r2, (r3, 0x2)
    1b40:	3a40      	cmpnei      	r2, 0
    1b42:	0ffe      	bf      	0x1b3e	// 1b3e <SYSCON_General_CMD.part.0+0x4e>
				SYSCON_ISOSCSTFlag=0;				// Wait ISOS stable interrupt	
    1b44:	3200      	movi      	r2, 0
    1b46:	a342      	st.b      	r2, (r3, 0x2)
    1b48:	07ee      	br      	0x1b24	// 1b24 <SYSCON_General_CMD.part.0+0x34>
    1b4a:	0000      	bkpt
    1b4c:	20000050 	.long	0x20000050
    1b50:	2000005c 	.long	0x2000005c
    1b54:	20000068 	.long	0x20000068

00001b58 <SYSCON_WDT_CMD.part.2>:
/*************************************************************/
void SYSCON_WDT_CMD(FunctionalStatus NewState)
{
	if(NewState != DISABLE)
	{
		SYSCON->IWDEDR=IWDTEDR_KEY|Enable_IWDT;
    1b58:	1364      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1b5a:	1345      	lrw      	r2, 0x78870000	// 1cec <LVD_Int_Disable+0xa>
    1b5c:	9360      	ld.w      	r3, (r3, 0)
    1b5e:	237f      	addi      	r3, 128
		while(!(SYSCON->IWDCR&Check_IWDT_BUSY));
    1b60:	3180      	movi      	r1, 128
		SYSCON->IWDEDR=IWDTEDR_KEY|Enable_IWDT;
    1b62:	b34f      	st.w      	r2, (r3, 0x3c)
		while(!(SYSCON->IWDCR&Check_IWDT_BUSY));
    1b64:	4125      	lsli      	r1, r1, 5
    1b66:	934d      	ld.w      	r2, (r3, 0x34)
    1b68:	6884      	and      	r2, r1
    1b6a:	3a40      	cmpnei      	r2, 0
    1b6c:	0ffd      	bf      	0x1b66	// 1b66 <SYSCON_WDT_CMD.part.2+0xe>
	else
	{
		SYSCON->IWDEDR=IWDTEDR_KEY|Disable_IWDT;
		while(SYSCON->IWDCR&Check_IWDT_BUSY);
	}
}
    1b6e:	783c      	rts

00001b70 <SYSCON_RST_VALUE>:
	SYSCON->IDCCR=SYSCON_IDCCR_RST;
    1b70:	127e      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1b72:	3201      	movi      	r2, 1
    1b74:	9360      	ld.w      	r3, (r3, 0)
    1b76:	b340      	st.w      	r2, (r3, 0)
	SYSCON->GCER=SYSCON_GCER_RST;
    1b78:	3200      	movi      	r2, 0
    1b7a:	b341      	st.w      	r2, (r3, 0x4)
	SYSCON->GCDR=SYSCON_GCDR_RST;
    1b7c:	b342      	st.w      	r2, (r3, 0x8)
	SYSCON->SCLKCR=SYSCON_SCLKCR_RST;
    1b7e:	3280      	movi      	r2, 128
    1b80:	4243      	lsli      	r2, r2, 3
    1b82:	b347      	st.w      	r2, (r3, 0x1c)
	SYSCON->PCLKCR=SYSCON_PCLKCR_RST;
    1b84:	3280      	movi      	r2, 128
    1b86:	4241      	lsli      	r2, r2, 1
    1b88:	b348      	st.w      	r2, (r3, 0x20)
	SYSCON->PCER0=SYSCON_PCER0_RST;
    1b8a:	3200      	movi      	r2, 0
    1b8c:	b34a      	st.w      	r2, (r3, 0x28)
	SYSCON->PCDR0=SYSCON_PCDR0_RST;
    1b8e:	b34b      	st.w      	r2, (r3, 0x2c)
	SYSCON->PCSR0=SYSCON_PCSR0_RST;
    1b90:	3201      	movi      	r2, 1
    1b92:	b34c      	st.w      	r2, (r3, 0x30)
	SYSCON->PCER1=SYSCON_PCER1_RST;
    1b94:	3200      	movi      	r2, 0
    1b96:	b34d      	st.w      	r2, (r3, 0x34)
	SYSCON->PCDR1=SYSCON_PCDR1_RST;
    1b98:	b34e      	st.w      	r2, (r3, 0x38)
	SYSCON->PCSR1=SYSCON_PCSR1_RST;
    1b9a:	b34f      	st.w      	r2, (r3, 0x3c)
	SYSCON->OSTR=SYSCON_OSTR_RST;
    1b9c:	1255      	lrw      	r2, 0xff03ff	// 1cf0 <LVD_Int_Disable+0xe>
    1b9e:	b350      	st.w      	r2, (r3, 0x40)
	SYSCON->LVDCR=SYSCON_LVDCR_RST;
    1ba0:	3200      	movi      	r2, 0
    1ba2:	b353      	st.w      	r2, (r3, 0x4c)
	SYSCON->CLCR=SYSCON_CLCR_RST;
    1ba4:	1254      	lrw      	r2, 0x1ff	// 1cf4 <LVD_Int_Disable+0x12>
    1ba6:	b354      	st.w      	r2, (r3, 0x50)
	SYSCON->PWRCR=SYSCON_PWRCR_RST;			
    1ba8:	1254      	lrw      	r2, 0x1f09	// 1cf8 <LVD_Int_Disable+0x16>
    1baa:	b355      	st.w      	r2, (r3, 0x54)
	SYSCON->IECR=SYSCON_IECR_RST;
    1bac:	3200      	movi      	r2, 0
    1bae:	b35d      	st.w      	r2, (r3, 0x74)
	SYSCON->IDCR=SYSCON_IDCR_RST;
    1bb0:	b35e      	st.w      	r2, (r3, 0x78)
	SYSCON->IMSR=SYSCON_IMSR_RST;
    1bb2:	b35f      	st.w      	r2, (r3, 0x7c)
	SYSCON->IAR=SYSCON_IAR_RST;
    1bb4:	237f      	addi      	r3, 128
    1bb6:	b340      	st.w      	r2, (r3, 0)
	SYSCON->ICR=SYSCON_ICR_RST;
    1bb8:	b341      	st.w      	r2, (r3, 0x4)
	SYSCON->RISR=SYSCON_RISR_RST;	
    1bba:	b342      	st.w      	r2, (r3, 0x8)
	SYSCON->ISR=SYSCON_ISR_RST;
    1bbc:	b343      	st.w      	r2, (r3, 0xc)
	SYSCON->RSR=SYSCON_RSR_RST;
    1bbe:	b344      	st.w      	r2, (r3, 0x10)
	SYSCON->EXIRT=SYSCON_EXIRT_RST;
    1bc0:	b345      	st.w      	r2, (r3, 0x14)
	SYSCON->EXIFT=SYSCON_EXIFT_RST;
    1bc2:	b346      	st.w      	r2, (r3, 0x18)
	SYSCON->EXIER=SYSCON_EXIER_RST;
    1bc4:	b347      	st.w      	r2, (r3, 0x1c)
	SYSCON->EXIDR=SYSCON_EXIDR_RST;
    1bc6:	b348      	st.w      	r2, (r3, 0x20)
	SYSCON->EXIMR=SYSCON_EXIMR_RST;
    1bc8:	b349      	st.w      	r2, (r3, 0x24)
	SYSCON->EXIAR=SYSCON_EXIAR_RST;
    1bca:	b34a      	st.w      	r2, (r3, 0x28)
	SYSCON->EXICR=SYSCON_EXICR_RST;
    1bcc:	b34b      	st.w      	r2, (r3, 0x2c)
	SYSCON->EXIRS=SYSCON_EXIRS_RST;
    1bce:	b34c      	st.w      	r2, (r3, 0x30)
	SYSCON->IWDCR=SYSCON_IWDCR_RST;
    1bd0:	124b      	lrw      	r2, 0x70c	// 1cfc <LVD_Int_Disable+0x1a>
    1bd2:	b34d      	st.w      	r2, (r3, 0x34)
	SYSCON->IWDCNT=SYSCON_IWDCNT_RST;
    1bd4:	124b      	lrw      	r2, 0x3ffff	// 1d00 <LVD_Int_Disable+0x1e>
    1bd6:	b34e      	st.w      	r2, (r3, 0x38)
	SYSCON->IWDEDR=SYSCON_IWDEDR_RST;
    1bd8:	3200      	movi      	r2, 0
    1bda:	b34f      	st.w      	r2, (r3, 0x3c)
	SYSCON->ERRINF=SYSCON_ERRINF_RST;
    1bdc:	b35b      	st.w      	r2, (r3, 0x6c)
}
    1bde:	783c      	rts

00001be0 <SYSCON_General_CMD>:
{
    1be0:	14d0      	push      	r15
	if (NewState != DISABLE)
    1be2:	3840      	cmpnei      	r0, 0
    1be4:	0c05      	bf      	0x1bee	// 1bee <SYSCON_General_CMD+0xe>
    1be6:	6c07      	mov      	r0, r1
    1be8:	e3ffff84 	bsr      	0x1af0	// 1af0 <SYSCON_General_CMD.part.0>
}
    1bec:	1490      	pop      	r15
		SYSCON->GCDR=ENDIS_X;													//disable SYSCON General Control
    1bee:	117f      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1bf0:	9340      	ld.w      	r2, (r3, 0)
    1bf2:	b222      	st.w      	r1, (r2, 0x8)
		while(SYSCON->GCSR&ENDIS_X);											//check  Disable?
    1bf4:	9263      	ld.w      	r3, (r2, 0xc)
    1bf6:	68c4      	and      	r3, r1
    1bf8:	3b40      	cmpnei      	r3, 0
    1bfa:	0bfd      	bt      	0x1bf4	// 1bf4 <SYSCON_General_CMD+0x14>
    1bfc:	07f8      	br      	0x1bec	// 1bec <SYSCON_General_CMD+0xc>

00001bfe <SystemCLK_HCLKDIV_PCLKDIV_Config>:
{
    1bfe:	14c1      	push      	r4
	SYSCON->SCLKCR=SYSCLK_KEY | HCLK_DIV_X| SYSCLK_X;
    1c00:	117a      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1c02:	9380      	ld.w      	r4, (r3, 0)
    1c04:	1260      	lrw      	r3, 0xd22d0000	// 1d04 <LVD_Int_Disable+0x22>
    1c06:	6cc0      	or      	r3, r0
    1c08:	6c4c      	or      	r1, r3
    1c0a:	b427      	st.w      	r1, (r4, 0x1c)
	while(!SYSCON_SYSCLKSTFlag);												//Wait clock switch stable interrupt
    1c0c:	117f      	lrw      	r3, 0x20000068	// 1d08 <LVD_Int_Disable+0x26>
    1c0e:	8323      	ld.b      	r1, (r3, 0x3)
    1c10:	3940      	cmpnei      	r1, 0
    1c12:	0ffe      	bf      	0x1c0e	// 1c0e <SystemCLK_HCLKDIV_PCLKDIV_Config+0x10>
	SYSCON_SYSCLKSTFlag=0;
    1c14:	3100      	movi      	r1, 0
    1c16:	a323      	st.b      	r1, (r3, 0x3)
	SYSCON->PCLKCR=PCLK_KEY|PCLK_DIV_X;											//PCLK DIV 1 2 4 6 8 16		
    1c18:	117d      	lrw      	r3, 0xc33c0000	// 1d0c <LVD_Int_Disable+0x2a>
    1c1a:	6cc8      	or      	r3, r2
    1c1c:	b468      	st.w      	r3, (r4, 0x20)
	while(SYSCON->PCLKCR!=PCLK_DIV_X);											//Wait PCLK DIV
    1c1e:	9468      	ld.w      	r3, (r4, 0x20)
    1c20:	64ca      	cmpne      	r2, r3
    1c22:	0bfe      	bt      	0x1c1e	// 1c1e <SystemCLK_HCLKDIV_PCLKDIV_Config+0x20>
	if(SYSCLK_X==SYSCLK_EMOSC) GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFF00F)|0x00000440;					//使能对应PIN
    1c24:	3841      	cmpnei      	r0, 1
    1c26:	080a      	bt      	0x1c3a	// 1c3a <SystemCLK_HCLKDIV_PCLKDIV_Config+0x3c>
    1c28:	117a      	lrw      	r3, 0x20000050	// 1d10 <LVD_Int_Disable+0x2e>
    1c2a:	32ff      	movi      	r2, 255
    1c2c:	9320      	ld.w      	r1, (r3, 0)
    1c2e:	9160      	ld.w      	r3, (r1, 0)
    1c30:	4244      	lsli      	r2, r2, 4
    1c32:	68c9      	andn      	r3, r2
    1c34:	3ba6      	bseti      	r3, r3, 6
    1c36:	3baa      	bseti      	r3, r3, 10
    1c38:	b160      	st.w      	r3, (r1, 0)
}
    1c3a:	1481      	pop      	r4

00001c3c <SYSCON_WDT_CMD>:
{
    1c3c:	14d0      	push      	r15
	if(NewState != DISABLE)
    1c3e:	3840      	cmpnei      	r0, 0
    1c40:	0c04      	bf      	0x1c48	// 1c48 <SYSCON_WDT_CMD+0xc>
    1c42:	e3ffff8b 	bsr      	0x1b58	// 1b58 <SYSCON_WDT_CMD.part.2>
}
    1c46:	1490      	pop      	r15
		SYSCON->IWDEDR=IWDTEDR_KEY|Disable_IWDT;
    1c48:	1168      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1c4a:	1153      	lrw      	r2, 0x78875555	// 1d14 <LVD_Int_Disable+0x32>
    1c4c:	9360      	ld.w      	r3, (r3, 0)
    1c4e:	237f      	addi      	r3, 128
		while(SYSCON->IWDCR&Check_IWDT_BUSY);
    1c50:	3180      	movi      	r1, 128
		SYSCON->IWDEDR=IWDTEDR_KEY|Disable_IWDT;
    1c52:	b34f      	st.w      	r2, (r3, 0x3c)
		while(SYSCON->IWDCR&Check_IWDT_BUSY);
    1c54:	4125      	lsli      	r1, r1, 5
    1c56:	934d      	ld.w      	r2, (r3, 0x34)
    1c58:	6884      	and      	r2, r1
    1c5a:	3a40      	cmpnei      	r2, 0
    1c5c:	0bfd      	bt      	0x1c56	// 1c56 <SYSCON_WDT_CMD+0x1a>
    1c5e:	07f4      	br      	0x1c46	// 1c46 <SYSCON_WDT_CMD+0xa>

00001c60 <SYSCON_GET_IWDCNT>:
//EntryParameter:NONE
//ReturnValue:IWDCNT
/*************************************************************/
U32_T SYSCON_GET_IWDCNT(void )
{
	return (SYSCON->IWDCNT&0x3FFFFF);
    1c60:	1162      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1c62:	9360      	ld.w      	r3, (r3, 0)
    1c64:	237f      	addi      	r3, 128
    1c66:	930e      	ld.w      	r0, (r3, 0x38)
    1c68:	400a      	lsli      	r0, r0, 10
    1c6a:	480a      	lsri      	r0, r0, 10
}
    1c6c:	783c      	rts

00001c6e <SYSCON_GET_IWDT_CLRBSY>:
//EntryParameter:NONE
//ReturnValue: WDT clr flag
/*************************************************************/
B_T SYSCON_GET_IWDT_CLRBSY(void)					
{
	if(SYSCON->IWDCNT&0x80000000)
    1c6e:	107f      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1c70:	9360      	ld.w      	r3, (r3, 0)
    1c72:	237f      	addi      	r3, 128
    1c74:	930e      	ld.w      	r0, (r3, 0x38)
    1c76:	481f      	lsri      	r0, r0, 31
	{
		return 1;
	}
	else return 0;
}
    1c78:	783c      	rts

00001c7a <SYSCON_IWDCNT_Reload>:
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void SYSCON_IWDCNT_Reload(void)
{
	SYSCON->IWDCNT=CLR_IWDT;
    1c7a:	107c      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1c7c:	32b4      	movi      	r2, 180
    1c7e:	9360      	ld.w      	r3, (r3, 0)
    1c80:	237f      	addi      	r3, 128
    1c82:	4257      	lsli      	r2, r2, 23
    1c84:	b34e      	st.w      	r2, (r3, 0x38)
}
    1c86:	783c      	rts

00001c88 <SYSCON_IWDCNT_Config>:
{
	SYSCON->IWDCR=IWDT_KEY|NewStateE_IWDT_SHORT|IWDT_TIME_X|IWDT_INTW_DIV_X;
}*/
void SYSCON_IWDCNT_Config(IWDT_TIME_TypeDef IWDT_TIME_X , IWDT_TIMEDIV_TypeDef IWDT_INTW_DIV_X )
{
	SYSCON->IWDCR=IWDT_KEY|IWDT_TIME_X|IWDT_INTW_DIV_X;
    1c88:	1144      	lrw      	r2, 0x87780000	// 1d18 <LVD_Int_Disable+0x36>
    1c8a:	1078      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1c8c:	6c48      	or      	r1, r2
    1c8e:	9360      	ld.w      	r3, (r3, 0)
    1c90:	6c04      	or      	r0, r1
    1c92:	237f      	addi      	r3, 128
    1c94:	b30d      	st.w      	r0, (r3, 0x34)
}
    1c96:	783c      	rts

00001c98 <SYSCON_LVD_Config>:
//RSTDET_LVL_X:RSTDET_LVL_2_2V,RSTDET_LVL_2_7V,RSTDET_LVL_3_3V,RSTDET_LVL_3_6V
//X_LVD_INT:ENABLE_LVD_INT,DISABLE_LVD_INT
//ReturnValue: NONE
/*************************************************************/
void SYSCON_LVD_Config(X_LVDEN_TypeDef X_LVDEN , INTDET_LVL_X_TypeDef INTDET_LVL_X , RSTDET_LVL_X_TypeDef RSTDET_LVL_X , X_LVD_INT_TypeDef X_LVD_INT)
{
    1c98:	14c2      	push      	r4-r5
	SYSCON->LVDCR=LVD_KEY;
    1c9a:	11a1      	lrw      	r5, 0xb44b0000	// 1d1c <LVD_Int_Disable+0x3a>
	SYSCON->LVDCR=LVD_KEY|X_LVDEN|INTDET_LVL_X|RSTDET_LVL_X|X_LVD_INT;
    1c9c:	6cd4      	or      	r3, r5
    1c9e:	6c8c      	or      	r2, r3
    1ca0:	6c48      	or      	r1, r2
	SYSCON->LVDCR=LVD_KEY;
    1ca2:	1092      	lrw      	r4, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
	SYSCON->LVDCR=LVD_KEY|X_LVDEN|INTDET_LVL_X|RSTDET_LVL_X|X_LVD_INT;
    1ca4:	6c04      	or      	r0, r1
	SYSCON->LVDCR=LVD_KEY;
    1ca6:	9480      	ld.w      	r4, (r4, 0)
    1ca8:	b4b3      	st.w      	r5, (r4, 0x4c)
	SYSCON->LVDCR=LVD_KEY|X_LVDEN|INTDET_LVL_X|RSTDET_LVL_X|X_LVD_INT;
    1caa:	b413      	st.w      	r0, (r4, 0x4c)
}
    1cac:	1482      	pop      	r4-r5

00001cae <LVR_Disable>:
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void LVR_Disable(void)
{
	SYSCON->LVDCR = (SYSCON->LVDCR&0xfffffff0)|LVD_KEY|0x0a;
    1cae:	106f      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1cb0:	105c      	lrw      	r2, 0x4bb50000	// 1d20 <LVD_Int_Disable+0x3e>
    1cb2:	9320      	ld.w      	r1, (r3, 0)
    1cb4:	9173      	ld.w      	r3, (r1, 0x4c)
    1cb6:	2a0f      	subi      	r2, 16
    1cb8:	68c8      	and      	r3, r2
    1cba:	105b      	lrw      	r2, 0xb44b000a	// 1d24 <LVD_Int_Disable+0x42>
    1cbc:	6cc8      	or      	r3, r2
    1cbe:	b173      	st.w      	r3, (r1, 0x4c)
}
    1cc0:	783c      	rts

00001cc2 <LVR_Enable>:
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void LVR_Enable(void)
{
	SYSCON->LVDCR = (SYSCON->LVDCR&0xfffffff0)|LVD_KEY;
    1cc2:	106a      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1cc4:	1057      	lrw      	r2, 0x4bb50000	// 1d20 <LVD_Int_Disable+0x3e>
    1cc6:	9320      	ld.w      	r1, (r3, 0)
    1cc8:	9173      	ld.w      	r3, (r1, 0x4c)
    1cca:	2a0f      	subi      	r2, 16
    1ccc:	68c8      	and      	r3, r2
    1cce:	1054      	lrw      	r2, 0xb44b0000	// 1d1c <LVD_Int_Disable+0x3a>
    1cd0:	6cc8      	or      	r3, r2
    1cd2:	b173      	st.w      	r3, (r1, 0x4c)
}
    1cd4:	783c      	rts

00001cd6 <LVD_Int_Enable>:
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void LVD_Int_Enable(void)
{
	SYSCON->IECR  |= LVD_INT_ST;
    1cd6:	1065      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1cd8:	9340      	ld.w      	r2, (r3, 0)
    1cda:	927d      	ld.w      	r3, (r2, 0x74)
    1cdc:	3bab      	bseti      	r3, r3, 11
    1cde:	b27d      	st.w      	r3, (r2, 0x74)
}
    1ce0:	783c      	rts

00001ce2 <LVD_Int_Disable>:
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void LVD_Int_Disable(void)
{
	SYSCON->IDCR  |= LVD_INT_ST;
    1ce2:	1062      	lrw      	r3, 0x2000005c	// 1ce8 <LVD_Int_Disable+0x6>
    1ce4:	9340      	ld.w      	r2, (r3, 0)
    1ce6:	0421      	br      	0x1d28	// 1d28 <LVD_Int_Disable+0x46>
    1ce8:	2000005c 	.long	0x2000005c
    1cec:	78870000 	.long	0x78870000
    1cf0:	00ff03ff 	.long	0x00ff03ff
    1cf4:	000001ff 	.long	0x000001ff
    1cf8:	00001f09 	.long	0x00001f09
    1cfc:	0000070c 	.long	0x0000070c
    1d00:	0003ffff 	.long	0x0003ffff
    1d04:	d22d0000 	.long	0xd22d0000
    1d08:	20000068 	.long	0x20000068
    1d0c:	c33c0000 	.long	0xc33c0000
    1d10:	20000050 	.long	0x20000050
    1d14:	78875555 	.long	0x78875555
    1d18:	87780000 	.long	0x87780000
    1d1c:	b44b0000 	.long	0xb44b0000
    1d20:	4bb50000 	.long	0x4bb50000
    1d24:	b44b000a 	.long	0xb44b000a
    1d28:	927e      	ld.w      	r3, (r2, 0x78)
    1d2a:	3bab      	bseti      	r3, r3, 11
    1d2c:	b27e      	st.w      	r3, (r2, 0x78)
}
    1d2e:	783c      	rts

00001d30 <EXTI_trigger_CMD>:
//EXI_tringer_mode:_EXIRT,_EXIFT
//ReturnValue: LVD detection flag
/*************************************************************/
void EXTI_trigger_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef  EXIPIN , EXI_tringer_mode_TypeDef EXI_tringer_mode)
{
	switch(EXI_tringer_mode)
    1d30:	3a40      	cmpnei      	r2, 0
    1d32:	0c04      	bf      	0x1d3a	// 1d3a <EXTI_trigger_CMD+0xa>
    1d34:	3a41      	cmpnei      	r2, 1
    1d36:	0c0e      	bf      	0x1d52	// 1d52 <EXTI_trigger_CMD+0x22>
			{
				SYSCON->EXIFT &=~EXIPIN;	
			}
			break;
	}	
}
    1d38:	783c      	rts
    1d3a:	1372      	lrw      	r3, 0x2000005c	// 1f00 <EXI3_Int_Enable+0xc>
			if(NewState != DISABLE)
    1d3c:	3840      	cmpnei      	r0, 0
				SYSCON->EXIRT |=EXIPIN;
    1d3e:	9360      	ld.w      	r3, (r3, 0)
    1d40:	237f      	addi      	r3, 128
    1d42:	9345      	ld.w      	r2, (r3, 0x14)
			if(NewState != DISABLE)
    1d44:	0c04      	bf      	0x1d4c	// 1d4c <EXTI_trigger_CMD+0x1c>
				SYSCON->EXIRT |=EXIPIN;
    1d46:	6c48      	or      	r1, r2
				SYSCON->EXIRT &=~EXIPIN;	
    1d48:	b325      	st.w      	r1, (r3, 0x14)
    1d4a:	07f7      	br      	0x1d38	// 1d38 <EXTI_trigger_CMD+0x8>
    1d4c:	6c46      	nor      	r1, r1
    1d4e:	6848      	and      	r1, r2
    1d50:	07fc      	br      	0x1d48	// 1d48 <EXTI_trigger_CMD+0x18>
    1d52:	136c      	lrw      	r3, 0x2000005c	// 1f00 <EXI3_Int_Enable+0xc>
			if(NewState != DISABLE)
    1d54:	3840      	cmpnei      	r0, 0
				SYSCON->EXIFT |=EXIPIN;
    1d56:	9360      	ld.w      	r3, (r3, 0)
    1d58:	237f      	addi      	r3, 128
    1d5a:	9346      	ld.w      	r2, (r3, 0x18)
			if(NewState != DISABLE)
    1d5c:	0c04      	bf      	0x1d64	// 1d64 <EXTI_trigger_CMD+0x34>
				SYSCON->EXIFT |=EXIPIN;
    1d5e:	6c48      	or      	r1, r2
				SYSCON->EXIFT &=~EXIPIN;	
    1d60:	b326      	st.w      	r1, (r3, 0x18)
}
    1d62:	07eb      	br      	0x1d38	// 1d38 <EXTI_trigger_CMD+0x8>
				SYSCON->EXIFT &=~EXIPIN;	
    1d64:	6c46      	nor      	r1, r1
    1d66:	6848      	and      	r1, r2
    1d68:	07fc      	br      	0x1d60	// 1d60 <EXTI_trigger_CMD+0x30>

00001d6a <EXTI_interrupt_CMD>:
//EXIPIN:EXI_PIN0/1/2/3/4/5/6/7/8/9/10/11/12/13
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void EXTI_interrupt_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef  EXIPIN )
{
    1d6a:	1366      	lrw      	r3, 0x2000005c	// 1f00 <EXI3_Int_Enable+0xc>
	if(NewState != DISABLE)
    1d6c:	3840      	cmpnei      	r0, 0
	{
		SYSCON->EXIER|=EXIPIN;								//EXI4 interrupt enable
    1d6e:	9360      	ld.w      	r3, (r3, 0)
    1d70:	237f      	addi      	r3, 128
	if(NewState != DISABLE)
    1d72:	0c0c      	bf      	0x1d8a	// 1d8a <EXTI_interrupt_CMD+0x20>
		SYSCON->EXIER|=EXIPIN;								//EXI4 interrupt enable
    1d74:	9347      	ld.w      	r2, (r3, 0x1c)
    1d76:	6c84      	or      	r2, r1
    1d78:	b347      	st.w      	r2, (r3, 0x1c)
		while(!(SYSCON->EXIMR&EXIPIN));						//Check EXI4 is enabled or not
    1d7a:	9349      	ld.w      	r2, (r3, 0x24)
    1d7c:	6884      	and      	r2, r1
    1d7e:	3a40      	cmpnei      	r2, 0
    1d80:	0ffd      	bf      	0x1d7a	// 1d7a <EXTI_interrupt_CMD+0x10>
		SYSCON->EXICR |=EXIPIN;								// Clear EXI4 status bit
    1d82:	934b      	ld.w      	r2, (r3, 0x2c)
    1d84:	6c48      	or      	r1, r2
    1d86:	b32b      	st.w      	r1, (r3, 0x2c)
	}
	else
	{
		SYSCON->EXIDR|=EXIPIN;
	}
}
    1d88:	783c      	rts
		SYSCON->EXIDR|=EXIPIN;
    1d8a:	9348      	ld.w      	r2, (r3, 0x20)
    1d8c:	6c48      	or      	r1, r2
    1d8e:	b328      	st.w      	r1, (r3, 0x20)
}
    1d90:	07fc      	br      	0x1d88	// 1d88 <EXTI_interrupt_CMD+0x1e>

00001d92 <GPIO_EXTI_interrupt>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPIO_EXTI_interrupt(CSP_GPIO_T * GPIOX,U32_T GPIO_IECR_VALUE)
{
	GPIOX->IECR=GPIO_IECR_VALUE;
    1d92:	b02b      	st.w      	r1, (r0, 0x2c)
}
    1d94:	783c      	rts

00001d96 <SleepMode_goto_sleep_prg>:
//外接32.768K晶振做CTC时钟，进入SLEEP模式配置
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SleepMode_goto_sleep_prg(void)
{
    1d96:	14d0      	push      	r15
	SYSCON_WDT_CMD(DISABLE);
    1d98:	3000      	movi      	r0, 0
    1d9a:	e3ffff51 	bsr      	0x1c3c	// 1c3c <SYSCON_WDT_CMD>
	SYSCON -> PWRCR = (SYSCON -> PWRCR & 0xFFFF3FE3) | (0xA66Aul<<16) | (0x1<<14) | (0x07<<2);
    1d9e:	1279      	lrw      	r3, 0x2000005c	// 1f00 <EXI3_Int_Enable+0xc>
    1da0:	1239      	lrw      	r1, 0x59953fe3	// 1f04 <EXI3_Int_Enable+0x10>
    1da2:	9340      	ld.w      	r2, (r3, 0)
    1da4:	9275      	ld.w      	r3, (r2, 0x54)
    1da6:	68c4      	and      	r3, r1
    1da8:	1238      	lrw      	r1, 0xa66a401c	// 1f08 <EXI3_Int_Enable+0x14>
    1daa:	6cc4      	or      	r3, r1
	SystemCLK_HCLKDIV_PCLKDIV_Config(SYSCLK_EMOSC,HCLK_DIV_1,PCLK_DIV_1);
    1dac:	3180      	movi      	r1, 128
	SYSCON -> PWRCR = (SYSCON -> PWRCR & 0xFFFF3FE3) | (0xA66Aul<<16) | (0x1<<14) | (0x07<<2);
    1dae:	b275      	st.w      	r3, (r2, 0x54)
	SystemCLK_HCLKDIV_PCLKDIV_Config(SYSCLK_EMOSC,HCLK_DIV_1,PCLK_DIV_1);
    1db0:	4121      	lsli      	r1, r1, 1
    1db2:	3200      	movi      	r2, 0
    1db4:	3001      	movi      	r0, 1
    1db6:	e3ffff24 	bsr      	0x1bfe	// 1bfe <SystemCLK_HCLKDIV_PCLKDIV_Config>
	//外部晶振做系统时钟
	SYSCON_General_CMD(DISABLE,ENDIS_SYSTICK);
    1dba:	3180      	movi      	r1, 128
    1dbc:	4124      	lsli      	r1, r1, 4
    1dbe:	3000      	movi      	r0, 0
    1dc0:	e3ffff10 	bsr      	0x1be0	// 1be0 <SYSCON_General_CMD>
	//关闭 Coret 时钟
	SYSCON_General_CMD(DISABLE,ENDIS_IMOSC);
    1dc4:	3102      	movi      	r1, 2
    1dc6:	3000      	movi      	r0, 0
    1dc8:	e3ffff0c 	bsr      	0x1be0	// 1be0 <SYSCON_General_CMD>
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void PCLK_goto_idle_mode(void)
{
	asm ("doze");											// Enter sleep mode
    1dcc:	c0005020 	doze
}
    1dd0:	1490      	pop      	r15

00001dd2 <SleepMode_wakeup_prg>:
{
    1dd2:	14d0      	push      	r15
    1dd4:	3080      	movi      	r0, 128
    1dd6:	4004      	lsli      	r0, r0, 4
    1dd8:	e3fffe8c 	bsr      	0x1af0	// 1af0 <SYSCON_General_CMD.part.0>
    1ddc:	3002      	movi      	r0, 2
    1dde:	e3fffe89 	bsr      	0x1af0	// 1af0 <SYSCON_General_CMD.part.0>
	SystemCLK_HCLKDIV_PCLKDIV_Config(SYSCLK_IMOSC,HCLK_DIV_1,PCLK_DIV_1);
    1de2:	3180      	movi      	r1, 128
    1de4:	3200      	movi      	r2, 0
    1de6:	4121      	lsli      	r1, r1, 1
    1de8:	3000      	movi      	r0, 0
    1dea:	e3ffff0a 	bsr      	0x1bfe	// 1bfe <SystemCLK_HCLKDIV_PCLKDIV_Config>
    1dee:	e3fffeb5 	bsr      	0x1b58	// 1b58 <SYSCON_WDT_CMD.part.2>
	SYSCON_IWDCNT_Reload();
    1df2:	e3ffff44 	bsr      	0x1c7a	// 1c7a <SYSCON_IWDCNT_Reload>
}
    1df6:	1490      	pop      	r15

00001df8 <PCLK_goto_idle_mode>:
	asm ("doze");											// Enter sleep mode
    1df8:	c0005020 	doze
}  
    1dfc:	783c      	rts

00001dfe <PCLK_goto_deepsleep_mode>:
//ReturnValue:NONE
/*************************************************************/
void PCLK_goto_deepsleep_mode(void)
{	
	//LVD_Disable();																//上电缺省LVR Enable，Disable LVR	
	SYSCON -> PWRCR = (SYSCON -> PWRCR & 0xFFFFCFFC) | (0xA66Aul<<16) | (0x3<<12) | 0x3 ;
    1dfe:	1261      	lrw      	r3, 0x2000005c	// 1f00 <EXI3_Int_Enable+0xc>
    1e00:	1223      	lrw      	r1, 0xa66a3003	// 1f0c <EXI3_Int_Enable+0x18>
    1e02:	9360      	ld.w      	r3, (r3, 0)
    1e04:	9355      	ld.w      	r2, (r3, 0x54)
    1e06:	6c84      	or      	r2, r1
    1e08:	b355      	st.w      	r2, (r3, 0x54)
	SYSCON->SCLKCR= (SYSCON -> SCLKCR & 0xFFFFF0FF) | SYSCLK_KEY | HCLK_DIV_2;		//睡眠前HCLK分频必须>=2,否则debug单步跑有问题
    1e0a:	9327      	ld.w      	r1, (r3, 0x1c)
    1e0c:	1201      	lrw      	r0, 0x2dd2f0ff	// 1f10 <EXI3_Int_Enable+0x1c>
    1e0e:	6840      	and      	r1, r0
    1e10:	1241      	lrw      	r2, 0xd22d0200	// 1f14 <EXI3_Int_Enable+0x20>
    1e12:	6c48      	or      	r1, r2
    1e14:	b327      	st.w      	r1, (r3, 0x1c)
	asm ("stop");																	// Enter sleep mode
    1e16:	c0004820 	stop
	SYSCON->SCLKCR= (SYSCON -> SCLKCR & 0xFFFFF0FF) | SYSCLK_KEY | HCLK_DIV_1;		
    1e1a:	9347      	ld.w      	r2, (r3, 0x1c)
    1e1c:	6880      	and      	r2, r0
    1e1e:	113f      	lrw      	r1, 0xd22d0100	// 1f18 <EXI3_Int_Enable+0x24>
    1e20:	6c84      	or      	r2, r1
    1e22:	b347      	st.w      	r2, (r3, 0x1c)
}  
    1e24:	783c      	rts

00001e26 <SYSCON_IMOSC_SETECTE>:
//EntryParameter:IMOSC_SETECTE_X
//IMOSC_SETECTE_X:IMOSC_SETECTE_20M,IMOSC_SETECTE_40M
//ReturnValue:NONE
/*************************************************************/  
void SYSCON_IMOSC_SETECTE(IMOSC_SETECTE_TypeDef IMOSC_SETECTE_X)
{		
    1e26:	14d2      	push      	r4-r5, r15
	SYSCON->SCLKCR=SYSCLK_KEY|SYSCLK_ISOSC;						//内部副振作系统时钟
    1e28:	1196      	lrw      	r4, 0x2000005c	// 1f00 <EXI3_Int_Enable+0xc>
    1e2a:	115d      	lrw      	r2, 0xd22d0004	// 1f1c <EXI3_Int_Enable+0x28>
    1e2c:	9460      	ld.w      	r3, (r4, 0)
{		
    1e2e:	6d43      	mov      	r5, r0
	SYSCON->SCLKCR=SYSCLK_KEY|SYSCLK_ISOSC;						//内部副振作系统时钟
    1e30:	b347      	st.w      	r2, (r3, 0x1c)
	SYSCON_General_CMD(DISABLE,ENDIS_IMOSC);					//disalbe IMOSC
    1e32:	3102      	movi      	r1, 2
    1e34:	3000      	movi      	r0, 0
    1e36:	e3fffed5 	bsr      	0x1be0	// 1be0 <SYSCON_General_CMD>
	if(IMOSC_SETECTE_X==IMOSC_SETECTE_20M)
    1e3a:	3d41      	cmpnei      	r5, 1
    1e3c:	0811      	bt      	0x1e5e	// 1e5e <SYSCON_IMOSC_SETECTE+0x38>
	{
		SYSCON->CLCR=(SYSCON->CLCR&0XFF8FFFFF)|(0X00<<22);		//使能内部高频振荡器，选择20M作为主震荡频率
    1e3e:	9420      	ld.w      	r1, (r4, 0)
    1e40:	32e0      	movi      	r2, 224
    1e42:	9174      	ld.w      	r3, (r1, 0x50)
    1e44:	424f      	lsli      	r2, r2, 15
    1e46:	68c9      	andn      	r3, r2
    1e48:	b174      	st.w      	r3, (r1, 0x50)
		IFC->CEDR=0X01;
    1e4a:	3201      	movi      	r2, 1
    1e4c:	1175      	lrw      	r3, 0x20000060	// 1f20 <EXI3_Int_Enable+0x2c>
    1e4e:	9360      	ld.w      	r3, (r3, 0)
    1e50:	b341      	st.w      	r2, (r3, 0x4)
		IFC->MR=0;
    1e52:	3200      	movi      	r2, 0
	}
	else if(IMOSC_SETECTE_X==IMOSC_SETECTE_40M)
	{
		SYSCON->CLCR=(SYSCON->CLCR&0XFF8FFFFF)|(0x01<<22);		//使能内部高频振荡器，选择40M作为主震荡频率
		IFC->CEDR=0X01;
		IFC->MR=1;
    1e54:	b345      	st.w      	r2, (r3, 0x14)
    1e56:	3002      	movi      	r0, 2
    1e58:	e3fffe4c 	bsr      	0x1af0	// 1af0 <SYSCON_General_CMD.part.0>
	}
	SYSCON_General_CMD(ENABLE,ENDIS_IMOSC);						//enable IMOSC
}
    1e5c:	1492      	pop      	r4-r5, r15
	else if(IMOSC_SETECTE_X==IMOSC_SETECTE_40M)
    1e5e:	3d42      	cmpnei      	r5, 2
    1e60:	0bfb      	bt      	0x1e56	// 1e56 <SYSCON_IMOSC_SETECTE+0x30>
		SYSCON->CLCR=(SYSCON->CLCR&0XFF8FFFFF)|(0x01<<22);		//使能内部高频振荡器，选择40M作为主震荡频率
    1e62:	9420      	ld.w      	r1, (r4, 0)
    1e64:	32e0      	movi      	r2, 224
    1e66:	9174      	ld.w      	r3, (r1, 0x50)
    1e68:	424f      	lsli      	r2, r2, 15
    1e6a:	68c9      	andn      	r3, r2
    1e6c:	3bb6      	bseti      	r3, r3, 22
    1e6e:	b174      	st.w      	r3, (r1, 0x50)
		IFC->CEDR=0X01;
    1e70:	3201      	movi      	r2, 1
    1e72:	116c      	lrw      	r3, 0x20000060	// 1f20 <EXI3_Int_Enable+0x2c>
    1e74:	9360      	ld.w      	r3, (r3, 0)
    1e76:	b341      	st.w      	r2, (r3, 0x4)
    1e78:	07ee      	br      	0x1e54	// 1e54 <SYSCON_IMOSC_SETECTE+0x2e>

00001e7a <SYSON_EMOSC_32k_EN>:
//ESOSC 32.768 ENABLE
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSON_EMOSC_32k_EN(void)
{
    1e7a:	14d0      	push      	r15
	SYSCON -> PWRCR = ( ((SYSCON -> PWRCR) & 0x0000F0FF) | (0xA66Aul<<16) ) ;
    1e7c:	1161      	lrw      	r3, 0x2000005c	// 1f00 <EXI3_Int_Enable+0xc>
    1e7e:	112a      	lrw      	r1, 0xf0ff	// 1f24 <EXI3_Int_Enable+0x30>
    1e80:	9340      	ld.w      	r2, (r3, 0)
    1e82:	9275      	ld.w      	r3, (r2, 0x54)
    1e84:	68c4      	and      	r3, r1
    1e86:	1129      	lrw      	r1, 0xa66a0000	// 1f28 <EXI3_Int_Enable+0x34>
    1e88:	6cc4      	or      	r3, r1
    1e8a:	b275      	st.w      	r3, (r2, 0x54)
	SYSCON->OSTR=0XAD;
    1e8c:	33ad      	movi      	r3, 173
    1e8e:	b270      	st.w      	r3, (r2, 0x40)
    1e90:	3008      	movi      	r0, 8
    1e92:	e3fffe2f 	bsr      	0x1af0	// 1af0 <SYSCON_General_CMD.part.0>
	SYSCON_General_CMD(ENABLE,ENDIS_EMOSC);										//enable EMOSC
}
    1e96:	1490      	pop      	r15

00001e98 <EXI0_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0_Int_Enable(void)
{
    INTC_ISER_WRITE(EXI0_INT);    
    1e98:	1165      	lrw      	r3, 0x20000064	// 1f2c <EXI3_Int_Enable+0x38>
    1e9a:	3280      	movi      	r2, 128
    1e9c:	9360      	ld.w      	r3, (r3, 0)
    1e9e:	23ff      	addi      	r3, 256
    1ea0:	b340      	st.w      	r2, (r3, 0)
}
    1ea2:	783c      	rts

00001ea4 <EXI0_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0_Int_Disable(void)
{
    INTC_ICER_WRITE(EXI0_INT);    
    1ea4:	1162      	lrw      	r3, 0x20000064	// 1f2c <EXI3_Int_Enable+0x38>
    1ea6:	32c0      	movi      	r2, 192
    1ea8:	9360      	ld.w      	r3, (r3, 0)
    1eaa:	4241      	lsli      	r2, r2, 1
    1eac:	60c8      	addu      	r3, r2
    1eae:	3280      	movi      	r2, 128
    1eb0:	b340      	st.w      	r2, (r3, 0)
}
    1eb2:	783c      	rts

00001eb4 <EXI1_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1_Int_Enable(void)
{
    INTC_ISER_WRITE(EXI1_INT);    
    1eb4:	107e      	lrw      	r3, 0x20000064	// 1f2c <EXI3_Int_Enable+0x38>
    1eb6:	3280      	movi      	r2, 128
    1eb8:	9360      	ld.w      	r3, (r3, 0)
    1eba:	23ff      	addi      	r3, 256
    1ebc:	4241      	lsli      	r2, r2, 1
    1ebe:	b340      	st.w      	r2, (r3, 0)
}
    1ec0:	783c      	rts

00001ec2 <EXI1_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1_Int_Disable(void)
{
    INTC_ICER_WRITE(EXI1_INT);    
    1ec2:	107b      	lrw      	r3, 0x20000064	// 1f2c <EXI3_Int_Enable+0x38>
    1ec4:	32c0      	movi      	r2, 192
    1ec6:	9360      	ld.w      	r3, (r3, 0)
    1ec8:	4241      	lsli      	r2, r2, 1
    1eca:	60c8      	addu      	r3, r2
    1ecc:	3280      	movi      	r2, 128
    1ece:	4241      	lsli      	r2, r2, 1
    1ed0:	b340      	st.w      	r2, (r3, 0)
}
    1ed2:	783c      	rts

00001ed4 <EXI2_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2_Int_Enable(void)
{
    INTC_ISER_WRITE(EXI2_INT);    
    1ed4:	1076      	lrw      	r3, 0x20000064	// 1f2c <EXI3_Int_Enable+0x38>
    1ed6:	3280      	movi      	r2, 128
    1ed8:	9360      	ld.w      	r3, (r3, 0)
    1eda:	23ff      	addi      	r3, 256
    1edc:	424e      	lsli      	r2, r2, 14
    1ede:	b340      	st.w      	r2, (r3, 0)
}
    1ee0:	783c      	rts

00001ee2 <EXI2_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2_Int_Disable(void)
{
    INTC_ICER_WRITE(EXI2_INT);    
    1ee2:	1073      	lrw      	r3, 0x20000064	// 1f2c <EXI3_Int_Enable+0x38>
    1ee4:	32c0      	movi      	r2, 192
    1ee6:	9360      	ld.w      	r3, (r3, 0)
    1ee8:	4241      	lsli      	r2, r2, 1
    1eea:	60c8      	addu      	r3, r2
    1eec:	3280      	movi      	r2, 128
    1eee:	424e      	lsli      	r2, r2, 14
    1ef0:	b340      	st.w      	r2, (r3, 0)
}
    1ef2:	783c      	rts

00001ef4 <EXI3_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI3_Int_Enable(void)
{
    INTC_ISER_WRITE(EXI3_INT);    
    1ef4:	106e      	lrw      	r3, 0x20000064	// 1f2c <EXI3_Int_Enable+0x38>
    1ef6:	3280      	movi      	r2, 128
    1ef8:	9360      	ld.w      	r3, (r3, 0)
    1efa:	23ff      	addi      	r3, 256
    1efc:	424f      	lsli      	r2, r2, 15
    1efe:	0419      	br      	0x1f30	// 1f30 <EXI3_Int_Enable+0x3c>
    1f00:	2000005c 	.long	0x2000005c
    1f04:	59953fe3 	.long	0x59953fe3
    1f08:	a66a401c 	.long	0xa66a401c
    1f0c:	a66a3003 	.long	0xa66a3003
    1f10:	2dd2f0ff 	.long	0x2dd2f0ff
    1f14:	d22d0200 	.long	0xd22d0200
    1f18:	d22d0100 	.long	0xd22d0100
    1f1c:	d22d0004 	.long	0xd22d0004
    1f20:	20000060 	.long	0x20000060
    1f24:	0000f0ff 	.long	0x0000f0ff
    1f28:	a66a0000 	.long	0xa66a0000
    1f2c:	20000064 	.long	0x20000064
    1f30:	b340      	st.w      	r2, (r3, 0)
}
    1f32:	783c      	rts

00001f34 <EXI3_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI3_Int_Disable(void)
{
    INTC_ICER_WRITE(EXI3_INT);    
    1f34:	1275      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1f36:	32c0      	movi      	r2, 192
    1f38:	9360      	ld.w      	r3, (r3, 0)
    1f3a:	4241      	lsli      	r2, r2, 1
    1f3c:	60c8      	addu      	r3, r2
    1f3e:	3280      	movi      	r2, 128
    1f40:	424f      	lsli      	r2, r2, 15
    1f42:	b340      	st.w      	r2, (r3, 0)
}
    1f44:	783c      	rts

00001f46 <EXI4_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4_Int_Enable(void)
{
    INTC_ISER_WRITE(EXI4_INT);    
    1f46:	1271      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1f48:	3280      	movi      	r2, 128
    1f4a:	9360      	ld.w      	r3, (r3, 0)
    1f4c:	23ff      	addi      	r3, 256
    1f4e:	4250      	lsli      	r2, r2, 16
    1f50:	b340      	st.w      	r2, (r3, 0)
}
    1f52:	783c      	rts

00001f54 <EXI4_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4_Int_Disable(void)
{
    INTC_ICER_WRITE(EXI4_INT);    
    1f54:	126d      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1f56:	32c0      	movi      	r2, 192
    1f58:	9360      	ld.w      	r3, (r3, 0)
    1f5a:	4241      	lsli      	r2, r2, 1
    1f5c:	60c8      	addu      	r3, r2
    1f5e:	3280      	movi      	r2, 128
    1f60:	4250      	lsli      	r2, r2, 16
    1f62:	b340      	st.w      	r2, (r3, 0)
}
    1f64:	783c      	rts

00001f66 <EXI0_WakeUp_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0_WakeUp_Enable(void)
{
    INTC_IWER_WRITE(EXI0_INT);    
    1f66:	1269      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1f68:	3280      	movi      	r2, 128
    1f6a:	9360      	ld.w      	r3, (r3, 0)
    1f6c:	23ff      	addi      	r3, 256
    1f6e:	b350      	st.w      	r2, (r3, 0x40)
}
    1f70:	783c      	rts

00001f72 <EXI0_WakeUp_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0_WakeUp_Disable(void)
{
    INTC_IWDR_WRITE(EXI0_INT);    
    1f72:	1266      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1f74:	32e0      	movi      	r2, 224
    1f76:	9360      	ld.w      	r3, (r3, 0)
    1f78:	4241      	lsli      	r2, r2, 1
    1f7a:	60c8      	addu      	r3, r2
    1f7c:	3280      	movi      	r2, 128
    1f7e:	b340      	st.w      	r2, (r3, 0)
}
    1f80:	783c      	rts

00001f82 <EXI1_WakeUp_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1_WakeUp_Enable(void)
{
    INTC_IWER_WRITE(EXI1_INT);    
    1f82:	1262      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1f84:	3280      	movi      	r2, 128
    1f86:	9360      	ld.w      	r3, (r3, 0)
    1f88:	23ff      	addi      	r3, 256
    1f8a:	4241      	lsli      	r2, r2, 1
    1f8c:	b350      	st.w      	r2, (r3, 0x40)
}
    1f8e:	783c      	rts

00001f90 <EXI1_WakeUp_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1_WakeUp_Disable(void)
{
    INTC_IWDR_WRITE(EXI1_INT);    
    1f90:	117e      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1f92:	32e0      	movi      	r2, 224
    1f94:	9360      	ld.w      	r3, (r3, 0)
    1f96:	4241      	lsli      	r2, r2, 1
    1f98:	60c8      	addu      	r3, r2
    1f9a:	3280      	movi      	r2, 128
    1f9c:	4241      	lsli      	r2, r2, 1
    1f9e:	b340      	st.w      	r2, (r3, 0)
}
    1fa0:	783c      	rts

00001fa2 <EXI2_WakeUp_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2_WakeUp_Enable(void)
{
    INTC_IWER_WRITE(EXI2_INT);    
    1fa2:	117a      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1fa4:	3280      	movi      	r2, 128
    1fa6:	9360      	ld.w      	r3, (r3, 0)
    1fa8:	23ff      	addi      	r3, 256
    1faa:	424e      	lsli      	r2, r2, 14
    1fac:	b350      	st.w      	r2, (r3, 0x40)
}
    1fae:	783c      	rts

00001fb0 <EXI2_WakeUp_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2_WakeUp_Disable(void)
{
    INTC_IWDR_WRITE(EXI2_INT);    
    1fb0:	1176      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1fb2:	32e0      	movi      	r2, 224
    1fb4:	9360      	ld.w      	r3, (r3, 0)
    1fb6:	4241      	lsli      	r2, r2, 1
    1fb8:	60c8      	addu      	r3, r2
    1fba:	3280      	movi      	r2, 128
    1fbc:	424e      	lsli      	r2, r2, 14
    1fbe:	b340      	st.w      	r2, (r3, 0)
}
    1fc0:	783c      	rts

00001fc2 <EXI3_WakeUp_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI3_WakeUp_Enable(void)
{
    INTC_IWER_WRITE(EXI3_INT);    
    1fc2:	1172      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1fc4:	3280      	movi      	r2, 128
    1fc6:	9360      	ld.w      	r3, (r3, 0)
    1fc8:	23ff      	addi      	r3, 256
    1fca:	424f      	lsli      	r2, r2, 15
    1fcc:	b350      	st.w      	r2, (r3, 0x40)
}
    1fce:	783c      	rts

00001fd0 <EXI3_WakeUp_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI3_WakeUp_Disable(void)
{
    INTC_IWDR_WRITE(EXI3_INT);    
    1fd0:	116e      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1fd2:	32e0      	movi      	r2, 224
    1fd4:	9360      	ld.w      	r3, (r3, 0)
    1fd6:	4241      	lsli      	r2, r2, 1
    1fd8:	60c8      	addu      	r3, r2
    1fda:	3280      	movi      	r2, 128
    1fdc:	424f      	lsli      	r2, r2, 15
    1fde:	b340      	st.w      	r2, (r3, 0)
}
    1fe0:	783c      	rts

00001fe2 <EXI4_WakeUp_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4_WakeUp_Enable(void)
{
    INTC_IWER_WRITE(EXI4_INT);    
    1fe2:	116a      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1fe4:	3280      	movi      	r2, 128
    1fe6:	9360      	ld.w      	r3, (r3, 0)
    1fe8:	23ff      	addi      	r3, 256
    1fea:	4250      	lsli      	r2, r2, 16
    1fec:	b350      	st.w      	r2, (r3, 0x40)
}
    1fee:	783c      	rts

00001ff0 <EXI4_WakeUp_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4_WakeUp_Disable(void)
{
    INTC_IWDR_WRITE(EXI4_INT);    
    1ff0:	1166      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    1ff2:	32e0      	movi      	r2, 224
    1ff4:	9360      	ld.w      	r3, (r3, 0)
    1ff6:	4241      	lsli      	r2, r2, 1
    1ff8:	60c8      	addu      	r3, r2
    1ffa:	3280      	movi      	r2, 128
    1ffc:	4250      	lsli      	r2, r2, 16
    1ffe:	b340      	st.w      	r2, (r3, 0)
}
    2000:	783c      	rts

00002002 <SYSCON_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_Int_Enable(void)
{
    INTC_ISER_WRITE(SYSCON_INT);    
    2002:	1162      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    2004:	3202      	movi      	r2, 2
    2006:	9360      	ld.w      	r3, (r3, 0)
    2008:	23ff      	addi      	r3, 256
    200a:	b340      	st.w      	r2, (r3, 0)
}
    200c:	783c      	rts

0000200e <SYSCON_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_Int_Disable(void)
{
    INTC_ICER_WRITE(SYSCON_INT);    
    200e:	107f      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    2010:	32c0      	movi      	r2, 192
    2012:	9360      	ld.w      	r3, (r3, 0)
    2014:	4241      	lsli      	r2, r2, 1
    2016:	60c8      	addu      	r3, r2
    2018:	3202      	movi      	r2, 2
    201a:	b340      	st.w      	r2, (r3, 0)
}
    201c:	783c      	rts

0000201e <SYSCON_WakeUp_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_WakeUp_Enable(void)
{
    INTC_IWER_WRITE(SYSCON_INT);    
    201e:	107b      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    2020:	3202      	movi      	r2, 2
    2022:	9360      	ld.w      	r3, (r3, 0)
    2024:	23ff      	addi      	r3, 256
    2026:	b350      	st.w      	r2, (r3, 0x40)
}
    2028:	783c      	rts

0000202a <SYSCON_WakeUp_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_WakeUp_Disable(void)
{
    INTC_IWDR_WRITE(SYSCON_INT);    
    202a:	1078      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    202c:	32e0      	movi      	r2, 224
    202e:	9360      	ld.w      	r3, (r3, 0)
    2030:	4241      	lsli      	r2, r2, 1
    2032:	60c8      	addu      	r3, r2
    2034:	3202      	movi      	r2, 2
    2036:	b340      	st.w      	r2, (r3, 0)
}
    2038:	783c      	rts

0000203a <SYSCON_Software_Reset>:
//EntryParameter:None
//ReturnValue:MCU reset
/*************************************************************/
void SYSCON_Software_Reset(void)
{
	SYSCON->IDCCR=IDCCR_KEY|SWRST;
    203a:	1075      	lrw      	r3, 0x2000005c	// 208c <SYSCON_INT_Priority+0x48>
    203c:	1055      	lrw      	r2, 0xe11e0080	// 2090 <SYSCON_INT_Priority+0x4c>
    203e:	9360      	ld.w      	r3, (r3, 0)
    2040:	b340      	st.w      	r2, (r3, 0)
}
    2042:	783c      	rts

00002044 <SYSCON_INT_Priority>:
//LED_INT 	  IRQ27
//ReturnValue:None
/*************************************************************/
void SYSCON_INT_Priority(void)
{
	INTC_IPR0_WRITE(0X00000000);   //IQR0-3
    2044:	1071      	lrw      	r3, 0x20000064	// 2088 <SYSCON_INT_Priority+0x44>
    2046:	3280      	movi      	r2, 128
    2048:	9360      	ld.w      	r3, (r3, 0)
    204a:	4243      	lsli      	r2, r2, 3
    204c:	3100      	movi      	r1, 0
    204e:	608c      	addu      	r2, r3
    2050:	b220      	st.w      	r1, (r2, 0)
	INTC_IPR1_WRITE(0X00000000);   //IQR4-7  
    2052:	1051      	lrw      	r2, 0x404	// 2094 <SYSCON_INT_Priority+0x50>
    2054:	608c      	addu      	r2, r3
    2056:	b220      	st.w      	r1, (r2, 0)
	INTC_IPR2_WRITE(0X00000000);   //IQR8-11  
    2058:	3281      	movi      	r2, 129
    205a:	4243      	lsli      	r2, r2, 3
    205c:	608c      	addu      	r2, r3
    205e:	b220      	st.w      	r1, (r2, 0)
	INTC_IPR3_WRITE(0X00000000);   //IQR12-15  
    2060:	104e      	lrw      	r2, 0x40c	// 2098 <SYSCON_INT_Priority+0x54>
    2062:	608c      	addu      	r2, r3
    2064:	b220      	st.w      	r1, (r2, 0)
	INTC_IPR4_WRITE(0X00000000);   //IQR16-19  
    2066:	3282      	movi      	r2, 130
    2068:	4243      	lsli      	r2, r2, 3
    206a:	608c      	addu      	r2, r3
    206c:	b220      	st.w      	r1, (r2, 0)
	INTC_IPR5_WRITE(0X00000000);   //IQR20-23 
    206e:	104c      	lrw      	r2, 0x414	// 209c <SYSCON_INT_Priority+0x58>
    2070:	608c      	addu      	r2, r3
    2072:	b220      	st.w      	r1, (r2, 0)
	INTC_IPR6_WRITE(0X00000000);   //IQR24-27  
    2074:	3283      	movi      	r2, 131
    2076:	4243      	lsli      	r2, r2, 3
    2078:	608c      	addu      	r2, r3
    207a:	b220      	st.w      	r1, (r2, 0)
	INTC_IPR7_WRITE(0X00000000);   //IQR28-31
    207c:	1049      	lrw      	r2, 0x41c	// 20a0 <SYSCON_INT_Priority+0x5c>
    207e:	60c8      	addu      	r3, r2
    2080:	3200      	movi      	r2, 0
    2082:	b340      	st.w      	r2, (r3, 0)
}
    2084:	783c      	rts
    2086:	0000      	bkpt
    2088:	20000064 	.long	0x20000064
    208c:	2000005c 	.long	0x2000005c
    2090:	e11e0080 	.long	0xe11e0080
    2094:	00000404 	.long	0x00000404
    2098:	0000040c 	.long	0x0000040c
    209c:	00000414 	.long	0x00000414
    20a0:	0000041c 	.long	0x0000041c

000020a4 <GPT_RESET_VALUE>:
//*GPTCHX:GPTCH0,GPTCH1,GPTCH2
//ReturnValue:NONE
/*************************************************************/  
void GPT_RESET_VALUE(CSP_GPT_T *GPTCHX)									//reset value
{
	GPTCHX->ECR		=	GPT_ECR_RST;          		/**< ECR reset value       */
    20a4:	3300      	movi      	r3, 0
    20a6:	b074      	st.w      	r3, (r0, 0x50)
	GPTCHX->DCR		=	GPT_DCR_RST;	     	 	/**< DCR reset value       */
    20a8:	b075      	st.w      	r3, (r0, 0x54)
	GPTCHX->PMSR	=	GPT_PMSR_RST;	     		/**< PMSR reset value      */
    20aa:	106f      	lrw      	r3, 0x2aaaaaa0	// 20e4 <GPT_RESET_VALUE+0x40>
    20ac:	b076      	st.w      	r3, (r0, 0x58)
	GPTCHX->CR		=	GPT_CR_RST;           		/**< CR reset value        */
    20ae:	3300      	movi      	r3, 0
    20b0:	b078      	st.w      	r3, (r0, 0x60)
	GPTCHX->MR		=	GPT_MR_RST;          		/**< MR reset value        */
    20b2:	b079      	st.w      	r3, (r0, 0x64)
	GPTCHX->CSR		= 	GPT_CSR_RST;         		/**< CSR reset value       */
    20b4:	b07b      	st.w      	r3, (r0, 0x6c)
	GPTCHX->SR 		=	GPT_SR_RST;           		/**< SR reset value        */
    20b6:	b07c      	st.w      	r3, (r0, 0x70)
	GPTCHX->IER		=	GPT_IER_RST;          		/**< IER reset value       */
    20b8:	b07d      	st.w      	r3, (r0, 0x74)
	GPTCHX->IDR		=	GPT_IDR_RST;          		/**< IDR reset value       */
    20ba:	b07e      	st.w      	r3, (r0, 0x78)
	GPTCHX->IMR		=	GPT_IMR_RST;          		/**< IMR Rreset value      */
    20bc:	b07f      	st.w      	r3, (r0, 0x7c)
	GPTCHX->CV		=	GPT_CV_RST;           		/**< CV reset value        */
    20be:	207f      	addi      	r0, 128
    20c0:	b060      	st.w      	r3, (r0, 0)
	GPTCHX->RA		= 	GPT_RA_RST;           	 	/**< RA reset value        */
	GPTCHX->RB		=	GPT_RB_RST;           	 	/**< RB reset value        */
	GPTCHX->RC		=	GPT_RC_RST;           		/**< RC reset value        */
	
	GPT->BCR	=	GPT_BCR_RST;          			/**< BCR reset value       */
    20c2:	32c0      	movi      	r2, 192
	GPTCHX->RA		= 	GPT_RA_RST;           	 	/**< RA reset value        */
    20c4:	b061      	st.w      	r3, (r0, 0x4)
	GPTCHX->RB		=	GPT_RB_RST;           	 	/**< RB reset value        */
    20c6:	b062      	st.w      	r3, (r0, 0x8)
	GPTCHX->RC		=	GPT_RC_RST;           		/**< RC reset value        */
    20c8:	b063      	st.w      	r3, (r0, 0xc)
	GPT->BCR	=	GPT_BCR_RST;          			/**< BCR reset value       */
    20ca:	4242      	lsli      	r2, r2, 2
    20cc:	1067      	lrw      	r3, 0x20000038	// 20e8 <GPT_RESET_VALUE+0x44>
    20ce:	3100      	movi      	r1, 0
    20d0:	9360      	ld.w      	r3, (r3, 0)
    20d2:	608c      	addu      	r2, r3
    20d4:	b220      	st.w      	r1, (r2, 0)
	GPT->BMR	=	GPT_BMR_RST;          			/**< BMR reset value       */
    20d6:	32c1      	movi      	r2, 193
    20d8:	4242      	lsli      	r2, r2, 2
    20da:	60c8      	addu      	r3, r2
    20dc:	3200      	movi      	r2, 0
    20de:	b340      	st.w      	r2, (r3, 0)
}
    20e0:	783c      	rts
    20e2:	0000      	bkpt
    20e4:	2aaaaaa0 	.long	0x2aaaaaa0
    20e8:	20000038 	.long	0x20000038

000020ec <GPT_IO_Init>:
//GPT_IO_IO2B(0->PA0.14(AF1) ; 1->PA1.5(AF2))
//ReturnValue:NONE
/*************************************************************/
void GPT_IO_Init(GPT_IO_MODE_TypeDef  GPT_IO_MODE_X , U8_T GPT_IO_G )
{
	if(GPT_IO_MODE_X==GPT_IO_CLK0)
    20ec:	3841      	cmpnei      	r0, 1
    20ee:	0816      	bt      	0x211a	// 211a <GPT_IO_Init+0x2e>
	{
		if(GPT_IO_G==0)
    20f0:	3940      	cmpnei      	r1, 0
    20f2:	0809      	bt      	0x2104	// 2104 <GPT_IO_Init+0x18>
		{
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFF0F)|0x00000050;										//GPT_IO_CLK0(PA0.1->AF2)
    20f4:	1360      	lrw      	r3, 0x20000050	// 2274 <GPT_IO_Init+0x188>
	}
	else if(GPT_IO_MODE_X==GPT_IO_ETR)
	{
		if(GPT_IO_G==0)
		{
			GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000050;										//GPT_IO_ETR(PB0.1->AF2)
    20f6:	9340      	ld.w      	r2, (r3, 0)
    20f8:	9260      	ld.w      	r3, (r2, 0)
    20fa:	31f0      	movi      	r1, 240
    20fc:	68c5      	andn      	r3, r1
    20fe:	3ba4      	bseti      	r3, r3, 4
    2100:	3ba6      	bseti      	r3, r3, 6
    2102:	040a      	br      	0x2116	// 2116 <GPT_IO_Init+0x2a>
		else if(GPT_IO_G==1)
    2104:	3941      	cmpnei      	r1, 1
    2106:	0809      	bt      	0x2118	// 2118 <GPT_IO_Init+0x2c>
			GPIOD0->CONLR=(GPIOD0->CONLR & 0XFFFFFF0F)|0x00000060;										//GPT_IO_CLK0(PD0.1->AF3)
    2108:	127c      	lrw      	r3, 0x20000040	// 2278 <GPT_IO_Init+0x18c>
    210a:	9340      	ld.w      	r2, (r3, 0)
    210c:	9260      	ld.w      	r3, (r2, 0)
    210e:	31f0      	movi      	r1, 240
    2110:	68c5      	andn      	r3, r1
    2112:	3ba5      	bseti      	r3, r3, 5
    2114:	3ba6      	bseti      	r3, r3, 6
    2116:	b260      	st.w      	r3, (r2, 0)
		else if(GPT_IO_G==1)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00500000;										//GPT_IO_IO1A(PA1.5->AF2)
		}
	}
}
    2118:	783c      	rts
	else if(GPT_IO_MODE_X==GPT_IO_CLK1)
    211a:	3842      	cmpnei      	r0, 2
    211c:	080c      	bt      	0x2134	// 2134 <GPT_IO_Init+0x48>
		if(GPT_IO_G==0)
    211e:	3940      	cmpnei      	r1, 0
    2120:	0bfc      	bt      	0x2118	// 2118 <GPT_IO_Init+0x2c>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x60000000;										//GPT_IO_CLK1(PA0.15->AF3)
    2122:	1275      	lrw      	r3, 0x20000050	// 2274 <GPT_IO_Init+0x188>
    2124:	9340      	ld.w      	r2, (r3, 0)
    2126:	9261      	ld.w      	r3, (r2, 0x4)
    2128:	4364      	lsli      	r3, r3, 4
    212a:	4b64      	lsri      	r3, r3, 4
    212c:	3bbd      	bseti      	r3, r3, 29
    212e:	3bbe      	bseti      	r3, r3, 30
    2130:	b261      	st.w      	r3, (r2, 0x4)
    2132:	07f3      	br      	0x2118	// 2118 <GPT_IO_Init+0x2c>
	else if(GPT_IO_MODE_X==GPT_IO_CLK2)
    2134:	3843      	cmpnei      	r0, 3
    2136:	0805      	bt      	0x2140	// 2140 <GPT_IO_Init+0x54>
		if(GPT_IO_G==0)
    2138:	3940      	cmpnei      	r1, 0
    213a:	0bef      	bt      	0x2118	// 2118 <GPT_IO_Init+0x2c>
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFFF0F)|0x00000060;										//GPT_IO_CLK2(PC0.1->AF3)
    213c:	1270      	lrw      	r3, 0x20000044	// 227c <GPT_IO_Init+0x190>
    213e:	07e6      	br      	0x210a	// 210a <GPT_IO_Init+0x1e>
	else if(GPT_IO_MODE_X==GPT_IO_ETR)
    2140:	3844      	cmpnei      	r0, 4
    2142:	080f      	bt      	0x2160	// 2160 <GPT_IO_Init+0x74>
		if(GPT_IO_G==0)
    2144:	3940      	cmpnei      	r1, 0
    2146:	0803      	bt      	0x214c	// 214c <GPT_IO_Init+0x60>
			GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000050;										//GPT_IO_ETR(PB0.1->AF2)
    2148:	126e      	lrw      	r3, 0x20000048	// 2280 <GPT_IO_Init+0x194>
    214a:	07d6      	br      	0x20f6	// 20f6 <GPT_IO_Init+0xa>
		else if(GPT_IO_G==1)
    214c:	3941      	cmpnei      	r1, 1
    214e:	0be5      	bt      	0x2118	// 2118 <GPT_IO_Init+0x2c>
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFFFF0)|0x00000006;										//GPT_IO_ETR(PC0.0->AF3)
    2150:	126b      	lrw      	r3, 0x20000044	// 227c <GPT_IO_Init+0x190>
    2152:	310f      	movi      	r1, 15
    2154:	9340      	ld.w      	r2, (r3, 0)
    2156:	9260      	ld.w      	r3, (r2, 0)
    2158:	68c5      	andn      	r3, r1
    215a:	3ba1      	bseti      	r3, r3, 1
    215c:	3ba2      	bseti      	r3, r3, 2
    215e:	07dc      	br      	0x2116	// 2116 <GPT_IO_Init+0x2a>
	else if(GPT_IO_MODE_X==GPT_IO_IO0A)
    2160:	3845      	cmpnei      	r0, 5
    2162:	0825      	bt      	0x21ac	// 21ac <GPT_IO_Init+0xc0>
		if(GPT_IO_G==0)
    2164:	3940      	cmpnei      	r1, 0
    2166:	0803      	bt      	0x216c	// 216c <GPT_IO_Init+0x80>
			GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000060;										//GPT_IO_IO0A(PB0.1->AF3)
    2168:	1266      	lrw      	r3, 0x20000048	// 2280 <GPT_IO_Init+0x194>
    216a:	07d0      	br      	0x210a	// 210a <GPT_IO_Init+0x1e>
		else if(GPT_IO_G==1)
    216c:	3941      	cmpnei      	r1, 1
    216e:	080c      	bt      	0x2186	// 2186 <GPT_IO_Init+0x9a>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFF0FFF)|0x00007000;										//GPT_IO_IO0A(PA0.3->AF4)
    2170:	1261      	lrw      	r3, 0x20000050	// 2274 <GPT_IO_Init+0x188>
    2172:	32f0      	movi      	r2, 240
    2174:	9320      	ld.w      	r1, (r3, 0)
    2176:	4248      	lsli      	r2, r2, 8
    2178:	9160      	ld.w      	r3, (r1, 0)
    217a:	68c9      	andn      	r3, r2
    217c:	32e0      	movi      	r2, 224
    217e:	4247      	lsli      	r2, r2, 7
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFF0FFFF)|0x00070000;										//GPT_IO_IO0B(PA0.4->AF4)
    2180:	6cc8      	or      	r3, r2
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00500000;										//GPT_IO_IO1A(PA1.5->AF2)
    2182:	b160      	st.w      	r3, (r1, 0)
}
    2184:	07ca      	br      	0x2118	// 2118 <GPT_IO_Init+0x2c>
		else if(GPT_IO_G==2)
    2186:	3942      	cmpnei      	r1, 2
    2188:	0808      	bt      	0x2198	// 2198 <GPT_IO_Init+0xac>
			GPIOD0->CONLR=(GPIOD0->CONLR & 0XFFFFFFF0)|0x00000004;										//GPT_IO_IO0A(PD0.0->AF1)
    218a:	117c      	lrw      	r3, 0x20000040	// 2278 <GPT_IO_Init+0x18c>
    218c:	310f      	movi      	r1, 15
    218e:	9340      	ld.w      	r2, (r3, 0)
    2190:	9260      	ld.w      	r3, (r2, 0)
    2192:	68c5      	andn      	r3, r1
    2194:	3ba2      	bseti      	r3, r3, 2
    2196:	07c0      	br      	0x2116	// 2116 <GPT_IO_Init+0x2a>
		else if(GPT_IO_G==3)
    2198:	3943      	cmpnei      	r1, 3
    219a:	0bbf      	bt      	0x2118	// 2118 <GPT_IO_Init+0x2c>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFFF0)|0x00000005;										//GPT_IO_IO0A(PA1.0->AF2)
    219c:	117a      	lrw      	r3, 0x2000004c	// 2284 <GPT_IO_Init+0x198>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000006;										//GPT_IO_IO0B(PA0.0->AF3)
    219e:	9340      	ld.w      	r2, (r3, 0)
    21a0:	9260      	ld.w      	r3, (r2, 0)
    21a2:	310f      	movi      	r1, 15
    21a4:	68c5      	andn      	r3, r1
    21a6:	6c0c      	or      	r0, r3
    21a8:	b200      	st.w      	r0, (r2, 0)
    21aa:	07b7      	br      	0x2118	// 2118 <GPT_IO_Init+0x2c>
	else if(GPT_IO_MODE_X==GPT_IO_IO0B)
    21ac:	3846      	cmpnei      	r0, 6
    21ae:	081d      	bt      	0x21e8	// 21e8 <GPT_IO_Init+0xfc>
		if(GPT_IO_G==0)
    21b0:	3940      	cmpnei      	r1, 0
    21b2:	0803      	bt      	0x21b8	// 21b8 <GPT_IO_Init+0xcc>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000006;										//GPT_IO_IO0B(PA0.0->AF3)
    21b4:	1170      	lrw      	r3, 0x20000050	// 2274 <GPT_IO_Init+0x188>
    21b6:	07f4      	br      	0x219e	// 219e <GPT_IO_Init+0xb2>
		else if(GPT_IO_G==1)
    21b8:	3941      	cmpnei      	r1, 1
    21ba:	080a      	bt      	0x21ce	// 21ce <GPT_IO_Init+0xe2>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFF0FFFF)|0x00070000;										//GPT_IO_IO0B(PA0.4->AF4)
    21bc:	116e      	lrw      	r3, 0x20000050	// 2274 <GPT_IO_Init+0x188>
    21be:	32f0      	movi      	r2, 240
    21c0:	9320      	ld.w      	r1, (r3, 0)
    21c2:	424c      	lsli      	r2, r2, 12
    21c4:	9160      	ld.w      	r3, (r1, 0)
    21c6:	68c9      	andn      	r3, r2
    21c8:	32e0      	movi      	r2, 224
    21ca:	424b      	lsli      	r2, r2, 11
    21cc:	07da      	br      	0x2180	// 2180 <GPT_IO_Init+0x94>
		else if(GPT_IO_G==2)
    21ce:	3942      	cmpnei      	r1, 2
    21d0:	0808      	bt      	0x21e0	// 21e0 <GPT_IO_Init+0xf4>
			GPIOD0->CONLR=(GPIOD0->CONLR & 0XFFFFFF0F)|0x00000040;										//GPT_IO_IO0B(PD0.1->AF1)
    21d2:	116a      	lrw      	r3, 0x20000040	// 2278 <GPT_IO_Init+0x18c>
    21d4:	31f0      	movi      	r1, 240
    21d6:	9340      	ld.w      	r2, (r3, 0)
    21d8:	9260      	ld.w      	r3, (r2, 0)
    21da:	68c5      	andn      	r3, r1
    21dc:	3ba6      	bseti      	r3, r3, 6
    21de:	079c      	br      	0x2116	// 2116 <GPT_IO_Init+0x2a>
		else if(GPT_IO_G==3)
    21e0:	3943      	cmpnei      	r1, 3
    21e2:	0b9b      	bt      	0x2118	// 2118 <GPT_IO_Init+0x2c>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFF0F)|0x00000050;										//GPT_IO_IO0B(PA1.1->AF2)
    21e4:	1168      	lrw      	r3, 0x2000004c	// 2284 <GPT_IO_Init+0x198>
    21e6:	0788      	br      	0x20f6	// 20f6 <GPT_IO_Init+0xa>
	else if(GPT_IO_MODE_X==GPT_IO_IO1A)
    21e8:	3847      	cmpnei      	r0, 7
    21ea:	0817      	bt      	0x2218	// 2218 <GPT_IO_Init+0x12c>
		if(GPT_IO_G==0)
    21ec:	3940      	cmpnei      	r1, 0
    21ee:	080a      	bt      	0x2202	// 2202 <GPT_IO_Init+0x116>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00004000;										//GPT_IO_IO1A(PA0.11->AF1)
    21f0:	1161      	lrw      	r3, 0x20000050	// 2274 <GPT_IO_Init+0x188>
    21f2:	32f0      	movi      	r2, 240
    21f4:	9320      	ld.w      	r1, (r3, 0)
    21f6:	9161      	ld.w      	r3, (r1, 0x4)
    21f8:	4248      	lsli      	r2, r2, 8
    21fa:	68c9      	andn      	r3, r2
    21fc:	3bae      	bseti      	r3, r3, 14
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x04000000;										//GPT_IO_IO2B(PA0.14->AF1)
    21fe:	b161      	st.w      	r3, (r1, 0x4)
    2200:	078c      	br      	0x2118	// 2118 <GPT_IO_Init+0x2c>
		else if(GPT_IO_G==1)
    2202:	3941      	cmpnei      	r1, 1
    2204:	0b8a      	bt      	0x2118	// 2118 <GPT_IO_Init+0x2c>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFF0FF)|0x00000500;										//GPT_IO_IO1A(PA1.2->AF2)
    2206:	1160      	lrw      	r3, 0x2000004c	// 2284 <GPT_IO_Init+0x198>
    2208:	32f0      	movi      	r2, 240
    220a:	9320      	ld.w      	r1, (r3, 0)
    220c:	9160      	ld.w      	r3, (r1, 0)
    220e:	4244      	lsli      	r2, r2, 4
    2210:	68c9      	andn      	r3, r2
    2212:	3ba8      	bseti      	r3, r3, 8
    2214:	3baa      	bseti      	r3, r3, 10
    2216:	07b6      	br      	0x2182	// 2182 <GPT_IO_Init+0x96>
	else if(GPT_IO_MODE_X==GPT_IO_IO1B)
    2218:	3848      	cmpnei      	r0, 8
    221a:	0816      	bt      	0x2246	// 2246 <GPT_IO_Init+0x15a>
		if(GPT_IO_G==0)
    221c:	3940      	cmpnei      	r1, 0
    221e:	0809      	bt      	0x2230	// 2230 <GPT_IO_Init+0x144>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFF0FFFF)|0x00040000;										//GPT_IO_IO1A(PA0.12->AF1)
    2220:	1075      	lrw      	r3, 0x20000050	// 2274 <GPT_IO_Init+0x188>
    2222:	32f0      	movi      	r2, 240
    2224:	9320      	ld.w      	r1, (r3, 0)
    2226:	9161      	ld.w      	r3, (r1, 0x4)
    2228:	424c      	lsli      	r2, r2, 12
    222a:	68c9      	andn      	r3, r2
    222c:	3bb2      	bseti      	r3, r3, 18
    222e:	07e8      	br      	0x21fe	// 21fe <GPT_IO_Init+0x112>
		else if(GPT_IO_G==1)
    2230:	3941      	cmpnei      	r1, 1
    2232:	0b73      	bt      	0x2118	// 2118 <GPT_IO_Init+0x2c>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFF0FFF)|0x00005000;										//GPT_IO_IO1A(PA1.3->AF2)
    2234:	1074      	lrw      	r3, 0x2000004c	// 2284 <GPT_IO_Init+0x198>
    2236:	32f0      	movi      	r2, 240
    2238:	9320      	ld.w      	r1, (r3, 0)
    223a:	9160      	ld.w      	r3, (r1, 0)
    223c:	4248      	lsli      	r2, r2, 8
    223e:	68c9      	andn      	r3, r2
    2240:	3bac      	bseti      	r3, r3, 12
    2242:	3bae      	bseti      	r3, r3, 14
    2244:	079f      	br      	0x2182	// 2182 <GPT_IO_Init+0x96>
	else if(GPT_IO_MODE_X==GPT_IO_IO2A)
    2246:	3849      	cmpnei      	r0, 9
    2248:	0820      	bt      	0x2288	// 2288 <GPT_IO_Init+0x19c>
		if(GPT_IO_G==0)
    224a:	3940      	cmpnei      	r1, 0
    224c:	0809      	bt      	0x225e	// 225e <GPT_IO_Init+0x172>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFF0FFFFF)|0x00400000;										//GPT_IO_IO2A(PA0.13->AF1)
    224e:	106a      	lrw      	r3, 0x20000050	// 2274 <GPT_IO_Init+0x188>
    2250:	32f0      	movi      	r2, 240
    2252:	9320      	ld.w      	r1, (r3, 0)
    2254:	9161      	ld.w      	r3, (r1, 0x4)
    2256:	4250      	lsli      	r2, r2, 16
    2258:	68c9      	andn      	r3, r2
    225a:	3bb6      	bseti      	r3, r3, 22
    225c:	07d1      	br      	0x21fe	// 21fe <GPT_IO_Init+0x112>
		else if(GPT_IO_G==1)
    225e:	3941      	cmpnei      	r1, 1
    2260:	0b5c      	bt      	0x2118	// 2118 <GPT_IO_Init+0x2c>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFF0FFFF)|0x00050000;										//GPT_IO_IO2A(PA1.4->AF2)
    2262:	1069      	lrw      	r3, 0x2000004c	// 2284 <GPT_IO_Init+0x198>
    2264:	32f0      	movi      	r2, 240
    2266:	9320      	ld.w      	r1, (r3, 0)
    2268:	9160      	ld.w      	r3, (r1, 0)
    226a:	424c      	lsli      	r2, r2, 12
    226c:	68c9      	andn      	r3, r2
    226e:	3bb0      	bseti      	r3, r3, 16
    2270:	3bb2      	bseti      	r3, r3, 18
    2272:	0788      	br      	0x2182	// 2182 <GPT_IO_Init+0x96>
    2274:	20000050 	.long	0x20000050
    2278:	20000040 	.long	0x20000040
    227c:	20000044 	.long	0x20000044
    2280:	20000048 	.long	0x20000048
    2284:	2000004c 	.long	0x2000004c
	else if(GPT_IO_MODE_X==GPT_IO_IO2B)
    2288:	384a      	cmpnei      	r0, 10
    228a:	0b47      	bt      	0x2118	// 2118 <GPT_IO_Init+0x2c>
		if(GPT_IO_G==0)
    228c:	3940      	cmpnei      	r1, 0
    228e:	0809      	bt      	0x22a0	// 22a0 <GPT_IO_Init+0x1b4>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x04000000;										//GPT_IO_IO2B(PA0.14->AF1)
    2290:	1365      	lrw      	r3, 0x20000050	// 2424 <GPTCHX_PWM_Configure+0x66>
    2292:	32f0      	movi      	r2, 240
    2294:	9320      	ld.w      	r1, (r3, 0)
    2296:	9161      	ld.w      	r3, (r1, 0x4)
    2298:	4254      	lsli      	r2, r2, 20
    229a:	68c9      	andn      	r3, r2
    229c:	3bba      	bseti      	r3, r3, 26
    229e:	07b0      	br      	0x21fe	// 21fe <GPT_IO_Init+0x112>
		else if(GPT_IO_G==1)
    22a0:	3941      	cmpnei      	r1, 1
    22a2:	0b3b      	bt      	0x2118	// 2118 <GPT_IO_Init+0x2c>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00500000;										//GPT_IO_IO1A(PA1.5->AF2)
    22a4:	1361      	lrw      	r3, 0x2000004c	// 2428 <GPTCHX_PWM_Configure+0x6a>
    22a6:	32f0      	movi      	r2, 240
    22a8:	9320      	ld.w      	r1, (r3, 0)
    22aa:	9160      	ld.w      	r3, (r1, 0)
    22ac:	4250      	lsli      	r2, r2, 16
    22ae:	68c9      	andn      	r3, r2
    22b0:	3bb4      	bseti      	r3, r3, 20
    22b2:	3bb6      	bseti      	r3, r3, 22
    22b4:	0767      	br      	0x2182	// 2182 <GPT_IO_Init+0x96>

000022b6 <All_GPT_SoftwareReset>:
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void All_GPT_SoftwareReset(void)
{
	GPT->BCR = 0x01;							// all GPT Software reset
    22b6:	127e      	lrw      	r3, 0x20000038	// 242c <GPTCHX_PWM_Configure+0x6e>
    22b8:	32c0      	movi      	r2, 192
    22ba:	9360      	ld.w      	r3, (r3, 0)
    22bc:	4242      	lsli      	r2, r2, 2
    22be:	60c8      	addu      	r3, r2
    22c0:	3201      	movi      	r2, 1
    22c2:	b340      	st.w      	r2, (r3, 0)
}
    22c4:	783c      	rts

000022c6 <All_GPT_SWTRG>:
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void All_GPT_SWTRG(void)
{
	GPT->BCR = 0x02;							// all GPT SWTRG
    22c6:	127a      	lrw      	r3, 0x20000038	// 242c <GPTCHX_PWM_Configure+0x6e>
    22c8:	32c0      	movi      	r2, 192
    22ca:	9360      	ld.w      	r3, (r3, 0)
    22cc:	4242      	lsli      	r2, r2, 2
    22ce:	60c8      	addu      	r3, r2
    22d0:	3202      	movi      	r2, 2
    22d2:	b340      	st.w      	r2, (r3, 0)
}
    22d4:	783c      	rts

000022d6 <GPTCHX_SWTRG>:
//*GPTCHX:GPTCH0,GPTCH1,GPTCH2
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_SWTRG(CSP_GPT_T *GPTCHX)
{
	GPTCHX->CR = 0x08;							//GPTCHX SWTRG
    22d6:	3308      	movi      	r3, 8
    22d8:	b078      	st.w      	r3, (r0, 0x60)
}
    22da:	783c      	rts

000022dc <GPTCHX_SoftwareReset>:
//*GPTCHX:GPTCH0,GPTCH1,GPTCH2
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_SoftwareReset(CSP_GPT_T *GPTCHX)
{
	GPTCHX->CR = 0x01;							//GPTCHX Software reset
    22dc:	3301      	movi      	r3, 1
    22de:	b078      	st.w      	r3, (r0, 0x60)
}
    22e0:	783c      	rts

000022e2 <GPTCHX_CountClk_CMD>:
//NewState:DISABLE,ENABLE
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_CountClk_CMD(CSP_GPT_T *GPTCHX , FunctionalStatus NewState)
{
	if(NewState != DISABLE)
    22e2:	3940      	cmpnei      	r1, 0
    22e4:	0c04      	bf      	0x22ec	// 22ec <GPTCHX_CountClk_CMD+0xa>
	{
		GPTCHX->CR = 0x02;							//enable counter clk 
    22e6:	3302      	movi      	r3, 2
	}
	else
	{
		GPTCHX->CR = 0x04;							//Disable counter clk 
    22e8:	b078      	st.w      	r3, (r0, 0x60)
	}
}
    22ea:	783c      	rts
		GPTCHX->CR = 0x04;							//Disable counter clk 
    22ec:	3304      	movi      	r3, 4
    22ee:	07fd      	br      	0x22e8	// 22e8 <GPTCHX_CountClk_CMD+0x6>

000022f0 <GPTCHX_Clk_CMD>:
//NewState:DISABLE,ENABLE
//ReturnValue:NONE
/*************************************************************/
void GPTCHX_Clk_CMD(CSP_GPT_T *GPTCHX , FunctionalStatus NewState)
{
	if(NewState != DISABLE)
    22f0:	3940      	cmpnei      	r1, 0
	{
		GPTCHX->ECR	=0X02;									//GPT CLK enable
    22f2:	3302      	movi      	r3, 2
	if(NewState != DISABLE)
    22f4:	0c08      	bf      	0x2304	// 2304 <GPTCHX_Clk_CMD+0x14>
		GPTCHX->ECR	=0X02;									//GPT CLK enable
    22f6:	b074      	st.w      	r3, (r0, 0x50)
		while(!(GPTCHX->PMSR&0X02));
    22f8:	3202      	movi      	r2, 2
    22fa:	9076      	ld.w      	r3, (r0, 0x58)
    22fc:	68c8      	and      	r3, r2
    22fe:	3b40      	cmpnei      	r3, 0
    2300:	0ffd      	bf      	0x22fa	// 22fa <GPTCHX_Clk_CMD+0xa>
	else 
	{
		GPTCHX->DCR	=0X02;									//GPT CLK disable
		while(GPTCHX->PMSR&0X02);
	}
}
    2302:	783c      	rts
		GPTCHX->DCR	=0X02;									//GPT CLK disable
    2304:	b075      	st.w      	r3, (r0, 0x54)
		while(GPTCHX->PMSR&0X02);
    2306:	3202      	movi      	r2, 2
    2308:	9076      	ld.w      	r3, (r0, 0x58)
    230a:	68c8      	and      	r3, r2
    230c:	3b40      	cmpnei      	r3, 0
    230e:	0bfd      	bt      	0x2308	// 2308 <GPTCHX_Clk_CMD+0x18>
    2310:	07f9      	br      	0x2302	// 2302 <GPTCHX_Clk_CMD+0x12>

00002312 <GPTCHX_Set_RA_RB_RC>:
//load_RC:0~0xffff
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_Set_RA_RB_RC(CSP_GPT_T *GPTCHX , U16_T load_RA , U16_T load_RB , U16_T load_RC)
{
	GPTCHX->RA = load_RA;											//Set GPT RA
    2312:	207f      	addi      	r0, 128
    2314:	b021      	st.w      	r1, (r0, 0x4)
	GPTCHX->RB = load_RB;											//Set GPT RB
    2316:	b042      	st.w      	r2, (r0, 0x8)
	GPTCHX->RC = load_RC;											//Set GPT RC
    2318:	b063      	st.w      	r3, (r0, 0xc)
}
    231a:	783c      	rts

0000231c <GPTCHX_CLK_Configure>:
//GPTCHX_BURST_SET_X:GPTCHX_BURST_SET_None,GPTCHX_BURST_SET_XC0,GPTCHX_BURST_SET_XC1,GPTCHX_BURST_SET_XC2
//ReturnValue:NONE
/*************************************************************/
void GPTCHX_CLK_Configure(CSP_GPT_T *GPTCHX , GPT_Mclk_Selecte_TypeDef GPT_Mclk_Selecte_X , GptClks_Selecte_TypeDef GptClks_Selecte_X ,
						GPTCHX_CLKI_SET_TypeDef GPTCHX_CLKI_X , GPTCHX_BURST_SET_TypeDef GPTCHX_BURST_SET_X)
{
    231c:	14c3      	push      	r4-r6
    231e:	9883      	ld.w      	r4, (sp, 0xc)
    2320:	6d93      	mov      	r6, r4
	GPTCHX->MR=GPTCHX->MR&0XFFFFFFC0;
    2322:	353f      	movi      	r5, 63
    2324:	9099      	ld.w      	r4, (r0, 0x64)
    2326:	6915      	andn      	r4, r5
    2328:	b099      	st.w      	r4, (r0, 0x64)
	GPTCHX->MR|=GptClks_Selecte_X|GPTCHX_CLKI_X|GPTCHX_BURST_SET_X;
    232a:	6cd8      	or      	r3, r6
    232c:	9099      	ld.w      	r4, (r0, 0x64)
    232e:	6c8c      	or      	r2, r3
    2330:	6c90      	or      	r2, r4
    2332:	b059      	st.w      	r2, (r0, 0x64)
	GPT->BMR=GPT->BMR&0xFFFFFEFF;
    2334:	32c1      	movi      	r2, 193
    2336:	117e      	lrw      	r3, 0x20000038	// 242c <GPTCHX_PWM_Configure+0x6e>
    2338:	4242      	lsli      	r2, r2, 2
    233a:	9360      	ld.w      	r3, (r3, 0)
    233c:	60c8      	addu      	r3, r2
    233e:	9340      	ld.w      	r2, (r3, 0)
    2340:	3a88      	bclri      	r2, r2, 8
    2342:	b340      	st.w      	r2, (r3, 0)
	GPT->BMR|=GPT_Mclk_Selecte_X;								//MCLK选择PCLK或者96MHz		
    2344:	9340      	ld.w      	r2, (r3, 0)
    2346:	6c84      	or      	r2, r1
    2348:	b340      	st.w      	r2, (r3, 0)
	if(GPT_Mclk_Selecte_X==GPT_Mclk_Selecte_HFOSC)				//若选择96MHz需要增加配置
    234a:	3380      	movi      	r3, 128
    234c:	4361      	lsli      	r3, r3, 1
    234e:	64c6      	cmpne      	r1, r3
	GPTCHX->MR|=GptClks_Selecte_X|GPTCHX_CLKI_X|GPTCHX_BURST_SET_X;
    2350:	6d5b      	mov      	r5, r6
	if(GPT_Mclk_Selecte_X==GPT_Mclk_Selecte_HFOSC)				//若选择96MHz需要增加配置
    2352:	080c      	bt      	0x236a	// 236a <GPTCHX_CLK_Configure+0x4e>
	{
		SYSCON->CLCR|=(0X01<<20);
    2354:	1177      	lrw      	r3, 0x2000005c	// 2430 <GPTCHX_PWM_Configure+0x72>
		while(!(SYSCON->CLCR&(0x01<<21)));
    2356:	3280      	movi      	r2, 128
		SYSCON->CLCR|=(0X01<<20);
    2358:	9320      	ld.w      	r1, (r3, 0)
    235a:	9174      	ld.w      	r3, (r1, 0x50)
    235c:	3bb4      	bseti      	r3, r3, 20
    235e:	b174      	st.w      	r3, (r1, 0x50)
		while(!(SYSCON->CLCR&(0x01<<21)));
    2360:	424e      	lsli      	r2, r2, 14
    2362:	9174      	ld.w      	r3, (r1, 0x50)
    2364:	68c8      	and      	r3, r2
    2366:	3b40      	cmpnei      	r3, 0
    2368:	0ffd      	bf      	0x2362	// 2362 <GPTCHX_CLK_Configure+0x46>
	}
}
    236a:	1483      	pop      	r4-r6

0000236c <GPTCHX_XCn_Configure>:
//				XC2_Selecte_TCLK2,XC2_Selecte_TIOA0,XC2_Selecte_TIOA1,
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_XCn_Configure(XCn_Configure_TypeDef XCn_Configure , XCn_Selecte_TypeDef XCn_Selecte_x)
{
	if(XCn_Configure==XC0_Configure)
    236c:	3840      	cmpnei      	r0, 0
    236e:	080e      	bt      	0x238a	// 238a <GPTCHX_XCn_Configure+0x1e>
	{
		GPT->BMR=GPT->BMR&0xFFFFFFFC;
    2370:	116f      	lrw      	r3, 0x20000038	// 242c <GPTCHX_PWM_Configure+0x6e>
    2372:	32c1      	movi      	r2, 193
    2374:	4242      	lsli      	r2, r2, 2
    2376:	9360      	ld.w      	r3, (r3, 0)
    2378:	60c8      	addu      	r3, r2
    237a:	9340      	ld.w      	r2, (r3, 0)
    237c:	3a80      	bclri      	r2, r2, 0
    237e:	3a81      	bclri      	r2, r2, 1
		GPT->BMR=GPT->BMR&0xFFFFFFF3;
		GPT->BMR|=XCn_Selecte_x;
	}
	else if(XCn_Configure==XC2_Configure)
	{
		GPT->BMR=GPT->BMR&0xFFFFFFCF;
    2380:	b340      	st.w      	r2, (r3, 0)
		GPT->BMR|=XCn_Selecte_x;
    2382:	9340      	ld.w      	r2, (r3, 0)
    2384:	6c48      	or      	r1, r2
    2386:	b320      	st.w      	r1, (r3, 0)
	}
}
    2388:	783c      	rts
	else if(XCn_Configure==XC1_Configure)
    238a:	3842      	cmpnei      	r0, 2
    238c:	080a      	bt      	0x23a0	// 23a0 <GPTCHX_XCn_Configure+0x34>
		GPT->BMR=GPT->BMR&0xFFFFFFF3;
    238e:	1168      	lrw      	r3, 0x20000038	// 242c <GPTCHX_PWM_Configure+0x6e>
    2390:	32c1      	movi      	r2, 193
    2392:	4242      	lsli      	r2, r2, 2
    2394:	9360      	ld.w      	r3, (r3, 0)
    2396:	60c8      	addu      	r3, r2
    2398:	9340      	ld.w      	r2, (r3, 0)
    239a:	3a82      	bclri      	r2, r2, 2
    239c:	3a83      	bclri      	r2, r2, 3
    239e:	07f1      	br      	0x2380	// 2380 <GPTCHX_XCn_Configure+0x14>
	else if(XCn_Configure==XC2_Configure)
    23a0:	3843      	cmpnei      	r0, 3
    23a2:	0bf3      	bt      	0x2388	// 2388 <GPTCHX_XCn_Configure+0x1c>
		GPT->BMR=GPT->BMR&0xFFFFFFCF;
    23a4:	1162      	lrw      	r3, 0x20000038	// 242c <GPTCHX_PWM_Configure+0x6e>
    23a6:	32c1      	movi      	r2, 193
    23a8:	4242      	lsli      	r2, r2, 2
    23aa:	9360      	ld.w      	r3, (r3, 0)
    23ac:	60c8      	addu      	r3, r2
    23ae:	9340      	ld.w      	r2, (r3, 0)
    23b0:	3a84      	bclri      	r2, r2, 4
    23b2:	3a85      	bclri      	r2, r2, 5
    23b4:	07e6      	br      	0x2380	// 2380 <GPTCHX_XCn_Configure+0x14>

000023b6 <GPTCHX_COUNT_Configure>:
//CPC_Reload_CMD:CPC_Reload_DISABLE,CPC_Reload_ENABLE
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_COUNT_Configure(CSP_GPT_T *GPTCHX , CPC_TRG_CMD_TypeDef CPC_Reload_CMD)
{
	GPTCHX->MR|=CPC_Reload_CMD;
    23b6:	9079      	ld.w      	r3, (r0, 0x64)
    23b8:	6c4c      	or      	r1, r3
    23ba:	b039      	st.w      	r1, (r0, 0x64)
}
    23bc:	783c      	rts

000023be <GPTCHX_PWM_Configure>:
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_PWM_Configure(CSP_GPT_T *GPTCHX , CPC_STOP_CMD_TypeDef CPC_STOP_CMD , CPC_DisCountClk_CMD_TypeDef CPC_DisCountClk_CMD , CPC_TRG_CMD_TypeDef CPC_Reload_CMD , ENETRG_CMD_TypeDef EEVT_Reload_CMD , EEVT_SET_TypeDef EEVT_SET_X ,
						 TIOA_SWTRG_OutPutX_TypeDef TIOA_SWTRG_OutPutX , TIOA_EEVT_OutPutX_TypeDef TIOA_EEVT_OutPutX , TIOA_CPA_OutPutX_TypeDef TIOA_CPA_OutPutX , TIOA_CPC_OutPutX_TypeDef TIOA_CPC_OutPutX ,
						 TIOB_SWTRG_OutPutX_TypeDef TIOB_SWTRG_OutPutX , TIOB_EEVT_OutPutX_TypeDef TIOB_EEVT_OutPutX , TIOB_CPB_OutPutX_TypeDef TIOB_CPB_OutPutX , TIOB_CPC_OutPutX_TypeDef TIOB_CPC_OutPutX)
{
    23be:	14c4      	push      	r4-r7
    23c0:	1428      	subi      	sp, sp, 32
    23c2:	98ae      	ld.w      	r5, (sp, 0x38)
    23c4:	b8a1      	st.w      	r5, (sp, 0x4)
    23c6:	98af      	ld.w      	r5, (sp, 0x3c)
    23c8:	b8a2      	st.w      	r5, (sp, 0x8)
    23ca:	98b0      	ld.w      	r5, (sp, 0x40)
    23cc:	b8a3      	st.w      	r5, (sp, 0xc)
    23ce:	98b1      	ld.w      	r5, (sp, 0x44)
    23d0:	b8a4      	st.w      	r5, (sp, 0x10)
    23d2:	98b2      	ld.w      	r5, (sp, 0x48)
    23d4:	b8a5      	st.w      	r5, (sp, 0x14)
    23d6:	98b3      	ld.w      	r5, (sp, 0x4c)
    23d8:	b8a6      	st.w      	r5, (sp, 0x18)
    23da:	98b4      	ld.w      	r5, (sp, 0x50)
    23dc:	6dd7      	mov      	r7, r5
    23de:	98b5      	ld.w      	r5, (sp, 0x54)
    23e0:	b8a7      	st.w      	r5, (sp, 0x1c)
	GPTCHX->MR=GPTCHX->MR&0X0000003F;
    23e2:	363f      	movi      	r6, 63
    23e4:	90b9      	ld.w      	r5, (r0, 0x64)
    23e6:	6958      	and      	r5, r6
	GPTCHX->MR|=(0X01<<15)|CPC_STOP_CMD|CPC_DisCountClk_CMD|CPC_Reload_CMD|TIOA_SWTRG_OutPutX|TIOA_EEVT_OutPutX|TIOA_CPA_OutPutX|TIOA_CPC_OutPutX
    23e8:	98c7      	ld.w      	r6, (sp, 0x1c)
    23ea:	3eaf      	bseti      	r6, r6, 15
    23ec:	6d9c      	or      	r6, r7
    23ee:	98e6      	ld.w      	r7, (sp, 0x18)
    23f0:	6d9c      	or      	r6, r7
    23f2:	98e4      	ld.w      	r7, (sp, 0x10)
    23f4:	6d9c      	or      	r6, r7
    23f6:	98e5      	ld.w      	r7, (sp, 0x14)
    23f8:	6d9c      	or      	r6, r7
    23fa:	98e3      	ld.w      	r7, (sp, 0xc)
    23fc:	6d9c      	or      	r6, r7
    23fe:	98e2      	ld.w      	r7, (sp, 0x8)
    2400:	6d9c      	or      	r6, r7
    2402:	98e1      	ld.w      	r7, (sp, 0x4)
    2404:	6d9c      	or      	r6, r7
    2406:	6cd8      	or      	r3, r6
	GPTCHX->MR=GPTCHX->MR&0X0000003F;
    2408:	b0b9      	st.w      	r5, (r0, 0x64)
{
    240a:	988c      	ld.w      	r4, (sp, 0x30)
	GPTCHX->MR|=(0X01<<15)|CPC_STOP_CMD|CPC_DisCountClk_CMD|CPC_Reload_CMD|TIOA_SWTRG_OutPutX|TIOA_EEVT_OutPutX|TIOA_CPA_OutPutX|TIOA_CPC_OutPutX
    240c:	6c8c      	or      	r2, r3
    240e:	90b9      	ld.w      	r5, (r0, 0x64)
{
    2410:	b880      	st.w      	r4, (sp, 0)
	GPTCHX->MR|=(0X01<<15)|CPC_STOP_CMD|CPC_DisCountClk_CMD|CPC_Reload_CMD|TIOA_SWTRG_OutPutX|TIOA_EEVT_OutPutX|TIOA_CPA_OutPutX|TIOA_CPC_OutPutX
    2412:	6c48      	or      	r1, r2
					|TIOB_SWTRG_OutPutX|TIOB_EEVT_OutPutX|TIOB_CPB_OutPutX|TIOB_CPC_OutPutX;
	if(EEVT_Reload_CMD==EEVT_Reload_ENABLE)
    2414:	9860      	ld.w      	r3, (sp, 0)
	GPTCHX->MR|=(0X01<<15)|CPC_STOP_CMD|CPC_DisCountClk_CMD|CPC_Reload_CMD|TIOA_SWTRG_OutPutX|TIOA_EEVT_OutPutX|TIOA_CPA_OutPutX|TIOA_CPC_OutPutX
    2416:	6d44      	or      	r5, r1
    2418:	b0b9      	st.w      	r5, (r0, 0x64)
	if(EEVT_Reload_CMD==EEVT_Reload_ENABLE)
    241a:	3b41      	cmpnei      	r3, 1
{
    241c:	988d      	ld.w      	r4, (sp, 0x34)
	{
		GPTCHX->MR|=(0x00<<12);
    241e:	9079      	ld.w      	r3, (r0, 0x64)
	if(EEVT_Reload_CMD==EEVT_Reload_ENABLE)
    2420:	0811      	bt      	0x2442	// 2442 <GPTCHX_PWM_Configure+0x84>
    2422:	0409      	br      	0x2434	// 2434 <GPTCHX_PWM_Configure+0x76>
    2424:	20000050 	.long	0x20000050
    2428:	2000004c 	.long	0x2000004c
    242c:	20000038 	.long	0x20000038
    2430:	2000005c 	.long	0x2000005c
	}
	else
	{
		GPTCHX->MR|=(0x01<<12);
	}
	if(EEVT_SET_X==EEVT_TIOB_NONE)
    2434:	3c4a      	cmpnei      	r4, 10
		GPTCHX->MR|=(0x01<<12);
    2436:	b079      	st.w      	r3, (r0, 0x64)
	if(EEVT_SET_X==EEVT_TIOB_NONE)
    2438:	0807      	bt      	0x2446	// 2446 <GPTCHX_PWM_Configure+0x88>
	{
		GPTCHX->MR|=(0x00<<10)|(0x00<<8);
    243a:	9079      	ld.w      	r3, (r0, 0x64)
	{
		GPTCHX->MR|=(0x03<<10)|(0x02<<8);
	}
	else if(EEVT_SET_X==EEVT_XC2_Rise_Fall)
	{
		GPTCHX->MR|=(0x03<<10)|(0x03<<8);
    243c:	b079      	st.w      	r3, (r0, 0x64)
	}
}
    243e:	1408      	addi      	sp, sp, 32
    2440:	1484      	pop      	r4-r7
		GPTCHX->MR|=(0x01<<12);
    2442:	3bac      	bseti      	r3, r3, 12
    2444:	07f8      	br      	0x2434	// 2434 <GPTCHX_PWM_Configure+0x76>
	else if(EEVT_SET_X==EEVT_TIOB_Rise)
    2446:	3c4b      	cmpnei      	r4, 11
    2448:	0804      	bt      	0x2450	// 2450 <GPTCHX_PWM_Configure+0x92>
		GPTCHX->MR|=(0x00<<10)|(0x01<<8);
    244a:	9079      	ld.w      	r3, (r0, 0x64)
    244c:	3ba8      	bseti      	r3, r3, 8
    244e:	07f7      	br      	0x243c	// 243c <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_TIOB_Fall)
    2450:	3c4c      	cmpnei      	r4, 12
    2452:	0804      	bt      	0x245a	// 245a <GPTCHX_PWM_Configure+0x9c>
		GPTCHX->MR|=(0x00<<10)|(0x02<<8);
    2454:	9079      	ld.w      	r3, (r0, 0x64)
    2456:	3ba9      	bseti      	r3, r3, 9
    2458:	07f2      	br      	0x243c	// 243c <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_TIOB_Rise_Fall)
    245a:	3c4d      	cmpnei      	r4, 13
    245c:	0805      	bt      	0x2466	// 2466 <GPTCHX_PWM_Configure+0xa8>
		GPTCHX->MR|=(0x00<<10)|(0x03<<8);
    245e:	9079      	ld.w      	r3, (r0, 0x64)
    2460:	3ba8      	bseti      	r3, r3, 8
    2462:	3ba9      	bseti      	r3, r3, 9
    2464:	07ec      	br      	0x243c	// 243c <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC0_NONE)
    2466:	3c4e      	cmpnei      	r4, 14
    2468:	0804      	bt      	0x2470	// 2470 <GPTCHX_PWM_Configure+0xb2>
		GPTCHX->MR|=(0x01<<10)|(0x00<<8);
    246a:	9079      	ld.w      	r3, (r0, 0x64)
    246c:	3baa      	bseti      	r3, r3, 10
    246e:	07e7      	br      	0x243c	// 243c <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC0_Rise)
    2470:	3c4f      	cmpnei      	r4, 15
    2472:	0805      	bt      	0x247c	// 247c <GPTCHX_PWM_Configure+0xbe>
		GPTCHX->MR|=(0x01<<10)|(0x01<<8);
    2474:	9079      	ld.w      	r3, (r0, 0x64)
    2476:	3ba8      	bseti      	r3, r3, 8
    2478:	3baa      	bseti      	r3, r3, 10
    247a:	07e1      	br      	0x243c	// 243c <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC0_Fall)
    247c:	3c50      	cmpnei      	r4, 16
    247e:	0805      	bt      	0x2488	// 2488 <GPTCHX_PWM_Configure+0xca>
		GPTCHX->MR|=(0x01<<10)|(0x02<<8);
    2480:	9079      	ld.w      	r3, (r0, 0x64)
    2482:	3ba9      	bseti      	r3, r3, 9
    2484:	3baa      	bseti      	r3, r3, 10
    2486:	07db      	br      	0x243c	// 243c <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC0_Rise_Fall)
    2488:	3c51      	cmpnei      	r4, 17
    248a:	0806      	bt      	0x2496	// 2496 <GPTCHX_PWM_Configure+0xd8>
		GPTCHX->MR|=(0x01<<10)|(0x03<<8);
    248c:	32e0      	movi      	r2, 224
    248e:	9079      	ld.w      	r3, (r0, 0x64)
    2490:	4243      	lsli      	r2, r2, 3
		GPTCHX->MR|=(0x03<<10)|(0x03<<8);
    2492:	6cc8      	or      	r3, r2
    2494:	07d4      	br      	0x243c	// 243c <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC1_NONE)
    2496:	3c52      	cmpnei      	r4, 18
    2498:	0804      	bt      	0x24a0	// 24a0 <GPTCHX_PWM_Configure+0xe2>
		GPTCHX->MR|=(0x02<<10)|(0x00<<8);
    249a:	9079      	ld.w      	r3, (r0, 0x64)
    249c:	3bab      	bseti      	r3, r3, 11
    249e:	07cf      	br      	0x243c	// 243c <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC1_Rise)
    24a0:	3c53      	cmpnei      	r4, 19
    24a2:	0805      	bt      	0x24ac	// 24ac <GPTCHX_PWM_Configure+0xee>
		GPTCHX->MR|=(0x02<<10)|(0x01<<8);
    24a4:	9079      	ld.w      	r3, (r0, 0x64)
    24a6:	3ba8      	bseti      	r3, r3, 8
    24a8:	3bab      	bseti      	r3, r3, 11
    24aa:	07c9      	br      	0x243c	// 243c <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC1_Fall)
    24ac:	3c54      	cmpnei      	r4, 20
    24ae:	0805      	bt      	0x24b8	// 24b8 <GPTCHX_PWM_Configure+0xfa>
		GPTCHX->MR|=(0x02<<10)|(0x02<<8);
    24b0:	9079      	ld.w      	r3, (r0, 0x64)
    24b2:	3ba9      	bseti      	r3, r3, 9
    24b4:	3bab      	bseti      	r3, r3, 11
    24b6:	07c3      	br      	0x243c	// 243c <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC1_Rise_Fall)
    24b8:	3c55      	cmpnei      	r4, 21
    24ba:	0805      	bt      	0x24c4	// 24c4 <GPTCHX_PWM_Configure+0x106>
		GPTCHX->MR|=(0x02<<10)|(0x03<<8);
    24bc:	9079      	ld.w      	r3, (r0, 0x64)
    24be:	32b0      	movi      	r2, 176
		GPTCHX->MR|=(0x03<<10)|(0x03<<8);
    24c0:	4244      	lsli      	r2, r2, 4
    24c2:	07e8      	br      	0x2492	// 2492 <GPTCHX_PWM_Configure+0xd4>
	else if(EEVT_SET_X==EEVT_XC2_NONE)
    24c4:	3c56      	cmpnei      	r4, 22
    24c6:	0805      	bt      	0x24d0	// 24d0 <GPTCHX_PWM_Configure+0x112>
		GPTCHX->MR|=(0x03<<10)|(0x00<<8);
    24c8:	9079      	ld.w      	r3, (r0, 0x64)
    24ca:	3baa      	bseti      	r3, r3, 10
    24cc:	3bab      	bseti      	r3, r3, 11
    24ce:	07b7      	br      	0x243c	// 243c <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC2_Rise)
    24d0:	3c57      	cmpnei      	r4, 23
    24d2:	0804      	bt      	0x24da	// 24da <GPTCHX_PWM_Configure+0x11c>
		GPTCHX->MR|=(0x03<<10)|(0x01<<8);
    24d4:	9079      	ld.w      	r3, (r0, 0x64)
    24d6:	32d0      	movi      	r2, 208
    24d8:	07f4      	br      	0x24c0	// 24c0 <GPTCHX_PWM_Configure+0x102>
	else if(EEVT_SET_X==EEVT_XC2_Fall)
    24da:	3c58      	cmpnei      	r4, 24
    24dc:	0804      	bt      	0x24e4	// 24e4 <GPTCHX_PWM_Configure+0x126>
		GPTCHX->MR|=(0x03<<10)|(0x02<<8);
    24de:	9079      	ld.w      	r3, (r0, 0x64)
    24e0:	32e0      	movi      	r2, 224
    24e2:	07ef      	br      	0x24c0	// 24c0 <GPTCHX_PWM_Configure+0x102>
	else if(EEVT_SET_X==EEVT_XC2_Rise_Fall)
    24e4:	3c59      	cmpnei      	r4, 25
    24e6:	0bac      	bt      	0x243e	// 243e <GPTCHX_PWM_Configure+0x80>
		GPTCHX->MR|=(0x03<<10)|(0x03<<8);
    24e8:	9079      	ld.w      	r3, (r0, 0x64)
    24ea:	32f0      	movi      	r2, 240
    24ec:	07ea      	br      	0x24c0	// 24c0 <GPTCHX_PWM_Configure+0x102>

000024ee <GPTCHX_Capture_Configure>:
//LDRB_TIOA_SET_X:LDRB_TIOA_NONE,LDRB_TIOA_Rise,LDRB_TIOA_Fall,LDRB_TIOA_Rise_Fall
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_Capture_Configure(CSP_GPT_T *GPTCHX , LDB_STOP_CMD_TypeDef LDB_STOP_CMD_X , LDB_DISCountClk_CMD_TypeDef LDB_DIS_CMD_X , 
		ABETRG_SET_TypeDef ABETRG_SET_X , CPC_TRG_CMD_TypeDef CPC_Reload_CMD , LDRA_TIOA_SET_TypeDef LDRA_TIOA_SET_X , LDRB_TIOA_SET_TypeDef LDRB_TIOA_SET_X)
{
    24ee:	14c4      	push      	r4-r7
    24f0:	1421      	subi      	sp, sp, 4
    24f2:	9885      	ld.w      	r4, (sp, 0x14)
    24f4:	6dd3      	mov      	r7, r4
    24f6:	9886      	ld.w      	r4, (sp, 0x18)
    24f8:	6d93      	mov      	r6, r4
    24fa:	9887      	ld.w      	r4, (sp, 0x1c)
    24fc:	b880      	st.w      	r4, (sp, 0)
	GPTCHX->MR=GPTCHX->MR&0X0000003F;
    24fe:	353f      	movi      	r5, 63
    2500:	9099      	ld.w      	r4, (r0, 0x64)
    2502:	6914      	and      	r4, r5
	GPTCHX->MR|=CPC_Reload_CMD|LDB_STOP_CMD_X|LDB_DIS_CMD_X|LDRA_TIOA_SET_X|LDRB_TIOA_SET_X;
    2504:	6d5b      	mov      	r5, r6
    2506:	98c0      	ld.w      	r6, (sp, 0)
    2508:	6d58      	or      	r5, r6
    250a:	6c94      	or      	r2, r5
	GPTCHX->MR=GPTCHX->MR&0X0000003F;
    250c:	b099      	st.w      	r4, (r0, 0x64)
	GPTCHX->MR|=CPC_Reload_CMD|LDB_STOP_CMD_X|LDB_DIS_CMD_X|LDRA_TIOA_SET_X|LDRB_TIOA_SET_X;
    250e:	6c48      	or      	r1, r2
    2510:	9099      	ld.w      	r4, (r0, 0x64)
    2512:	6c5c      	or      	r1, r7
    2514:	6c50      	or      	r1, r4
	if(ABETRG_SET_X==ABETRG_TIOA_NONE)
    2516:	3b4a      	cmpnei      	r3, 10
	GPTCHX->MR|=CPC_Reload_CMD|LDB_STOP_CMD_X|LDB_DIS_CMD_X|LDRA_TIOA_SET_X|LDRB_TIOA_SET_X;
    2518:	b039      	st.w      	r1, (r0, 0x64)
	if(ABETRG_SET_X==ABETRG_TIOA_NONE)
    251a:	0806      	bt      	0x2526	// 2526 <GPTCHX_Capture_Configure+0x38>
	{
		GPTCHX->MR|=(0x01<<10)|(0x00<<8);
    251c:	9079      	ld.w      	r3, (r0, 0x64)
    251e:	3baa      	bseti      	r3, r3, 10
	{
		GPTCHX->MR|=(0x00<<10)|(0x02<<8);
	}
	else if(ABETRG_SET_X==ABETRG_TIOB_Rise_Fall)
	{
		GPTCHX->MR|=(0x00<<10)|(0x03<<8);
    2520:	b079      	st.w      	r3, (r0, 0x64)
	}
}
    2522:	1401      	addi      	sp, sp, 4
    2524:	1484      	pop      	r4-r7
	else if(ABETRG_SET_X==ABETRG_TIOA_Rise)
    2526:	3b4b      	cmpnei      	r3, 11
    2528:	0805      	bt      	0x2532	// 2532 <GPTCHX_Capture_Configure+0x44>
		GPTCHX->MR|=(0x01<<10)|(0x01<<8);
    252a:	9079      	ld.w      	r3, (r0, 0x64)
    252c:	3ba8      	bseti      	r3, r3, 8
    252e:	3baa      	bseti      	r3, r3, 10
    2530:	07f8      	br      	0x2520	// 2520 <GPTCHX_Capture_Configure+0x32>
	else if(ABETRG_SET_X==ABETRG_TIOA_Fall)
    2532:	3b4c      	cmpnei      	r3, 12
    2534:	0805      	bt      	0x253e	// 253e <GPTCHX_Capture_Configure+0x50>
		GPTCHX->MR|=(0x01<<10)|(0x02<<8);
    2536:	9079      	ld.w      	r3, (r0, 0x64)
    2538:	3ba9      	bseti      	r3, r3, 9
    253a:	3baa      	bseti      	r3, r3, 10
    253c:	07f2      	br      	0x2520	// 2520 <GPTCHX_Capture_Configure+0x32>
	else if(ABETRG_SET_X==ABETRG_TIOA_Rise_Fall)
    253e:	3b4d      	cmpnei      	r3, 13
    2540:	0806      	bt      	0x254c	// 254c <GPTCHX_Capture_Configure+0x5e>
		GPTCHX->MR|=(0x01<<10)|(0x03<<8);
    2542:	32e0      	movi      	r2, 224
    2544:	9079      	ld.w      	r3, (r0, 0x64)
    2546:	4243      	lsli      	r2, r2, 3
    2548:	6cc8      	or      	r3, r2
    254a:	07eb      	br      	0x2520	// 2520 <GPTCHX_Capture_Configure+0x32>
	else if(ABETRG_SET_X==ABETRG_TIOB_NONE)
    254c:	3b4e      	cmpnei      	r3, 14
    254e:	0803      	bt      	0x2554	// 2554 <GPTCHX_Capture_Configure+0x66>
		GPTCHX->MR|=(0x00<<10)|(0x00<<8);
    2550:	9079      	ld.w      	r3, (r0, 0x64)
    2552:	07e7      	br      	0x2520	// 2520 <GPTCHX_Capture_Configure+0x32>
	else if(ABETRG_SET_X==ABETRG_TIOB_Rise)
    2554:	3b4f      	cmpnei      	r3, 15
    2556:	0804      	bt      	0x255e	// 255e <GPTCHX_Capture_Configure+0x70>
		GPTCHX->MR|=(0x00<<10)|(0x01<<8);
    2558:	9079      	ld.w      	r3, (r0, 0x64)
    255a:	3ba8      	bseti      	r3, r3, 8
    255c:	07e2      	br      	0x2520	// 2520 <GPTCHX_Capture_Configure+0x32>
	else if(ABETRG_SET_X==ABETRG_TIOB_Fall)
    255e:	3b50      	cmpnei      	r3, 16
    2560:	0804      	bt      	0x2568	// 2568 <GPTCHX_Capture_Configure+0x7a>
		GPTCHX->MR|=(0x00<<10)|(0x02<<8);
    2562:	9079      	ld.w      	r3, (r0, 0x64)
    2564:	3ba9      	bseti      	r3, r3, 9
    2566:	07dd      	br      	0x2520	// 2520 <GPTCHX_Capture_Configure+0x32>
	else if(ABETRG_SET_X==ABETRG_TIOB_Rise_Fall)
    2568:	3b51      	cmpnei      	r3, 17
    256a:	0bdc      	bt      	0x2522	// 2522 <GPTCHX_Capture_Configure+0x34>
		GPTCHX->MR|=(0x00<<10)|(0x03<<8);
    256c:	9079      	ld.w      	r3, (r0, 0x64)
    256e:	3ba8      	bseti      	r3, r3, 8
    2570:	3ba9      	bseti      	r3, r3, 9
    2572:	07d7      	br      	0x2520	// 2520 <GPTCHX_Capture_Configure+0x32>

00002574 <GPTCHX_ConfigInterrupt_CMD>:
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_ConfigInterrupt_CMD(CSP_GPT_T *GPTCHX , GPTCHX_INT_TypeDef GPTCHX_INT_X , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
    2574:	3a40      	cmpnei      	r2, 0
    2576:	0c07      	bf      	0x2584	// 2584 <GPTCHX_ConfigInterrupt_CMD+0x10>
	{
		GPTCHX->IER  = GPTCHX_INT_X;					//SET
    2578:	b03d      	st.w      	r1, (r0, 0x74)
		while(!(GPTCHX->IMR&GPTCHX_INT_X));
    257a:	907f      	ld.w      	r3, (r0, 0x7c)
    257c:	68c4      	and      	r3, r1
    257e:	3b40      	cmpnei      	r3, 0
    2580:	0ffd      	bf      	0x257a	// 257a <GPTCHX_ConfigInterrupt_CMD+0x6>
	else
	{
		GPTCHX->IDR  =	GPTCHX_INT_X;					//CLR
		while(GPTCHX->IMR&GPTCHX_INT_X);
	}
}
    2582:	783c      	rts
		GPTCHX->IDR  =	GPTCHX_INT_X;					//CLR
    2584:	b03e      	st.w      	r1, (r0, 0x78)
		while(GPTCHX->IMR&GPTCHX_INT_X);
    2586:	907f      	ld.w      	r3, (r0, 0x7c)
    2588:	68c4      	and      	r3, r1
    258a:	3b40      	cmpnei      	r3, 0
    258c:	0bfd      	bt      	0x2586	// 2586 <GPTCHX_ConfigInterrupt_CMD+0x12>
    258e:	07fa      	br      	0x2582	// 2582 <GPTCHX_ConfigInterrupt_CMD+0xe>

00002590 <GPTCH0_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH0_Int_Enable(void)
{
    INTC_ISER_WRITE(TC0_0_INT);    
    2590:	116a      	lrw      	r3, 0x20000064	// 2638 <GPTCH2_Wakeup_Disable+0x10>
    2592:	3210      	movi      	r2, 16
    2594:	9360      	ld.w      	r3, (r3, 0)
    2596:	23ff      	addi      	r3, 256
    2598:	b340      	st.w      	r2, (r3, 0)
}
    259a:	783c      	rts

0000259c <GPTCH1_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH1_Int_Enable(void)
{
    INTC_ISER_WRITE(TC0_1_INT);    
    259c:	1167      	lrw      	r3, 0x20000064	// 2638 <GPTCH2_Wakeup_Disable+0x10>
    259e:	3220      	movi      	r2, 32
    25a0:	9360      	ld.w      	r3, (r3, 0)
    25a2:	23ff      	addi      	r3, 256
    25a4:	b340      	st.w      	r2, (r3, 0)
}
    25a6:	783c      	rts

000025a8 <GPTCH2_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH2_Int_Enable(void)
{
    INTC_ISER_WRITE(TC0_2_INT);    
    25a8:	1164      	lrw      	r3, 0x20000064	// 2638 <GPTCH2_Wakeup_Disable+0x10>
    25aa:	3240      	movi      	r2, 64
    25ac:	9360      	ld.w      	r3, (r3, 0)
    25ae:	23ff      	addi      	r3, 256
    25b0:	b340      	st.w      	r2, (r3, 0)
}
    25b2:	783c      	rts

000025b4 <GPTCH0_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH0_Int_Disable(void)
{
    INTC_ICER_WRITE(TC0_0_INT);    
    25b4:	1161      	lrw      	r3, 0x20000064	// 2638 <GPTCH2_Wakeup_Disable+0x10>
    25b6:	32c0      	movi      	r2, 192
    25b8:	9360      	ld.w      	r3, (r3, 0)
    25ba:	4241      	lsli      	r2, r2, 1
    25bc:	60c8      	addu      	r3, r2
    25be:	3210      	movi      	r2, 16
    25c0:	b340      	st.w      	r2, (r3, 0)
}
    25c2:	783c      	rts

000025c4 <GPTCH1_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH1_Int_Disable(void)
{
    INTC_ICER_WRITE(TC0_1_INT);    
    25c4:	107d      	lrw      	r3, 0x20000064	// 2638 <GPTCH2_Wakeup_Disable+0x10>
    25c6:	32c0      	movi      	r2, 192
    25c8:	9360      	ld.w      	r3, (r3, 0)
    25ca:	4241      	lsli      	r2, r2, 1
    25cc:	60c8      	addu      	r3, r2
    25ce:	3220      	movi      	r2, 32
    25d0:	b340      	st.w      	r2, (r3, 0)
}
    25d2:	783c      	rts

000025d4 <GPTCH2_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH2_Int_Disable(void)
{
    INTC_ICER_WRITE(TC0_2_INT);    
    25d4:	1079      	lrw      	r3, 0x20000064	// 2638 <GPTCH2_Wakeup_Disable+0x10>
    25d6:	32c0      	movi      	r2, 192
    25d8:	9360      	ld.w      	r3, (r3, 0)
    25da:	4241      	lsli      	r2, r2, 1
    25dc:	60c8      	addu      	r3, r2
    25de:	3240      	movi      	r2, 64
    25e0:	b340      	st.w      	r2, (r3, 0)
}
    25e2:	783c      	rts

000025e4 <GPTCH0_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH0_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(TC0_0_INT);    
    25e4:	1075      	lrw      	r3, 0x20000064	// 2638 <GPTCH2_Wakeup_Disable+0x10>
    25e6:	3210      	movi      	r2, 16
    25e8:	9360      	ld.w      	r3, (r3, 0)
    25ea:	23ff      	addi      	r3, 256
    25ec:	b350      	st.w      	r2, (r3, 0x40)
}
    25ee:	783c      	rts

000025f0 <GPTCH0_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH0_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(TC0_0_INT);    
    25f0:	1072      	lrw      	r3, 0x20000064	// 2638 <GPTCH2_Wakeup_Disable+0x10>
    25f2:	32e0      	movi      	r2, 224
    25f4:	9360      	ld.w      	r3, (r3, 0)
    25f6:	4241      	lsli      	r2, r2, 1
    25f8:	60c8      	addu      	r3, r2
    25fa:	3210      	movi      	r2, 16
    25fc:	b340      	st.w      	r2, (r3, 0)
}
    25fe:	783c      	rts

00002600 <GPTCH1_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH1_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(TC0_1_INT);    
    2600:	106e      	lrw      	r3, 0x20000064	// 2638 <GPTCH2_Wakeup_Disable+0x10>
    2602:	3220      	movi      	r2, 32
    2604:	9360      	ld.w      	r3, (r3, 0)
    2606:	23ff      	addi      	r3, 256
    2608:	b350      	st.w      	r2, (r3, 0x40)
}
    260a:	783c      	rts

0000260c <GPTCH1_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH1_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(TC0_1_INT);    
    260c:	106b      	lrw      	r3, 0x20000064	// 2638 <GPTCH2_Wakeup_Disable+0x10>
    260e:	32e0      	movi      	r2, 224
    2610:	9360      	ld.w      	r3, (r3, 0)
    2612:	4241      	lsli      	r2, r2, 1
    2614:	60c8      	addu      	r3, r2
    2616:	3220      	movi      	r2, 32
    2618:	b340      	st.w      	r2, (r3, 0)
}
    261a:	783c      	rts

0000261c <GPTCH2_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH2_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(TC0_2_INT);    
    261c:	1067      	lrw      	r3, 0x20000064	// 2638 <GPTCH2_Wakeup_Disable+0x10>
    261e:	3240      	movi      	r2, 64
    2620:	9360      	ld.w      	r3, (r3, 0)
    2622:	23ff      	addi      	r3, 256
    2624:	b350      	st.w      	r2, (r3, 0x40)
}
    2626:	783c      	rts

00002628 <GPTCH2_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH2_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(TC0_2_INT);    
    2628:	1064      	lrw      	r3, 0x20000064	// 2638 <GPTCH2_Wakeup_Disable+0x10>
    262a:	32e0      	movi      	r2, 224
    262c:	9360      	ld.w      	r3, (r3, 0)
    262e:	4241      	lsli      	r2, r2, 1
    2630:	60c8      	addu      	r3, r2
    2632:	3240      	movi      	r2, 64
    2634:	b340      	st.w      	r2, (r3, 0)
}
    2636:	783c      	rts
    2638:	20000064 	.long	0x20000064

0000263c <GTC_ControlSet_Configure.part.0>:
/*************************************************************/  
void GTC_ControlSet_Configure (GTC_ControlSet_TypeDef GTC_ControlSet_x , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
	{
		GTC->CSR |= GTC_ControlSet_x;
    263c:	1066      	lrw      	r3, 0x20000028	// 2654 <GTC_ControlSet_Configure.part.0+0x18>
		if(GTC_ControlSet_x)
    263e:	3840      	cmpnei      	r0, 0
		GTC->CSR |= GTC_ControlSet_x;
    2640:	9340      	ld.w      	r2, (r3, 0)
    2642:	9264      	ld.w      	r3, (r2, 0x10)
    2644:	6cc0      	or      	r3, r0
    2646:	b264      	st.w      	r3, (r2, 0x10)
		if(GTC_ControlSet_x)
    2648:	0c05      	bf      	0x2652	// 2652 <GTC_ControlSet_Configure.part.0+0x16>
		{
			while(!(GTC->SR&GTC_ControlSet_x));
    264a:	9266      	ld.w      	r3, (r2, 0x18)
    264c:	68c0      	and      	r3, r0
    264e:	3b40      	cmpnei      	r3, 0
    2650:	0ffd      	bf      	0x264a	// 264a <GTC_ControlSet_Configure.part.0+0xe>
	else
	{
		GTC->CCR |= GTC_ControlSet_x;
		while(GTC->SR&GTC_ControlSet_x);
	}
}
    2652:	783c      	rts
    2654:	20000028 	.long	0x20000028

00002658 <GTC_RESET_VALUE>:
	GTC->IDR 	= GTC_IDR_RST;											/**< IDR reset value         */    
    2658:	1369      	lrw      	r3, 0x20000028	// 27fc <GTC_IO_Init+0x8c>
    265a:	134a      	lrw      	r2, 0x11000a	// 2800 <GTC_IO_Init+0x90>
    265c:	9360      	ld.w      	r3, (r3, 0)
    265e:	b340      	st.w      	r2, (r3, 0)
	GTC->CSSR 	= GTC_CSSR_RST;	     								   	/**< CSSR reset value        */
    2660:	3200      	movi      	r2, 0
    2662:	b341      	st.w      	r2, (r3, 0x4)
	GTC->CEDR 	= GTC_CEDR_RST;  	 									/**< CEDR reset value        */
    2664:	b342      	st.w      	r2, (r3, 0x8)
	GTC->SRR 	= GTC_SRR_RST;             								/**< SRR reset value         */
    2666:	b343      	st.w      	r2, (r3, 0xc)
	GTC->CSR 	= GTC_CSR_RST;             	 							/**< CSR reset value         */
    2668:	b344      	st.w      	r2, (r3, 0x10)
	GTC->CCR 	= GTC_CCR_RST;              							/**< CCR reset value         */
    266a:	b345      	st.w      	r2, (r3, 0x14)
	GTC->SR 	= GTC_SR_RST;           								/**< SR reset value          */
    266c:	3202      	movi      	r2, 2
    266e:	b346      	st.w      	r2, (r3, 0x18)
	GTC->IMSCR 	= GTC_IMSCR_RST;        								/**< IMSCR reset value       */
    2670:	3200      	movi      	r2, 0
    2672:	b347      	st.w      	r2, (r3, 0x1c)
	GTC->RISR	= GTC_RISR_RST;          								/**< RISR reset value        */
    2674:	b348      	st.w      	r2, (r3, 0x20)
	GTC->MISR 	= GTC_MISR_RST;         								/**< MIS reset value        */
    2676:	b349      	st.w      	r2, (r3, 0x24)
	GTC->ICR 	= GTC_ICR_RST;          								/**< ICR reset value         */
    2678:	b34a      	st.w      	r2, (r3, 0x28)
	GTC->CDR 	= GTC_CDR_RST;        									/**< SR reset value          */
    267a:	b34b      	st.w      	r2, (r3, 0x2c)
	GTC->CSMR 	= GTC_CSMR_RST;           								/**< SR reset value          */
    267c:	321f      	movi      	r2, 31
    267e:	b34c      	st.w      	r2, (r3, 0x30)
	GTC->PRDR 	= GTC_PRDR_RST;           								/**< DR reset value          */
    2680:	3200      	movi      	r2, 0
    2682:	b34d      	st.w      	r2, (r3, 0x34)
	GTC->PULR	= GTC_PULR_RST;          								/**< SR reset value          */
    2684:	b34e      	st.w      	r2, (r3, 0x38)
	GTC->CUCR 	= GTC_CUCR_RST;         								/**< SR reset value          */
    2686:	b353      	st.w      	r2, (r3, 0x4c)
	GTC->CDCR 	= GTC_CDCR_RST;            								/**< SR reset value          */
    2688:	b354      	st.w      	r2, (r3, 0x50)
	GTC->CVR	= GTC_CVR_RST;											/**< CVR reset value         */
    268a:	b355      	st.w      	r2, (r3, 0x54)
}
    268c:	783c      	rts

0000268e <GTC_Configure>:
{
    268e:	14c3      	push      	r4-r6
    2690:	9883      	ld.w      	r4, (sp, 0xc)
    2692:	6d53      	mov      	r5, r4
    2694:	9884      	ld.w      	r4, (sp, 0x10)
    2696:	6d93      	mov      	r6, r4
	GTC->CSSR = GTC_FIN_X;													//selected GTC clk
    2698:	1299      	lrw      	r4, 0x20000028	// 27fc <GTC_IO_Init+0x8c>
	GTC->CDR = GTC_DIVN|(GTC_DINM<<4);										//DIVN and DINM set
    269a:	4244      	lsli      	r2, r2, 4
	GTC->CSSR = GTC_FIN_X;													//selected GTC clk
    269c:	9480      	ld.w      	r4, (r4, 0)
    269e:	b401      	st.w      	r0, (r4, 0x4)
	GTC->CDR = GTC_DIVN|(GTC_DINM<<4);										//DIVN and DINM set
    26a0:	6c48      	or      	r1, r2
	GTC->CEDR = GTC_CLKEN|GTC_DBGEN;										//ENABLE GTC CLK
    26a2:	1219      	lrw      	r0, 0x80000001	// 2804 <GTC_IO_Init+0x94>
    26a4:	b402      	st.w      	r0, (r4, 0x8)
	GTC->CDR = GTC_DIVN|(GTC_DINM<<4);										//DIVN and DINM set
    26a6:	b42b      	st.w      	r1, (r4, 0x2c)
	GTC->CSMR = Counter_Size_X;												//selected GTC conter size
    26a8:	b46c      	st.w      	r3, (r4, 0x30)
	GTC->PRDR = loadCounter_PRDR;											//Period of GTC date register
    26aa:	b4ad      	st.w      	r5, (r4, 0x34)
	GTC->PULR = loadCounter_PULR;											//Pulse of GTC date register
    26ac:	b4ce      	st.w      	r6, (r4, 0x38)
}
    26ae:	1483      	pop      	r4-r6

000026b0 <GTC_ControlSet_Configure>:
{
    26b0:	14d0      	push      	r15
	if (NewState != DISABLE)
    26b2:	3940      	cmpnei      	r1, 0
    26b4:	0c04      	bf      	0x26bc	// 26bc <GTC_ControlSet_Configure+0xc>
    26b6:	e3ffffc3 	bsr      	0x263c	// 263c <GTC_ControlSet_Configure.part.0>
}
    26ba:	1490      	pop      	r15
		GTC->CCR |= GTC_ControlSet_x;
    26bc:	1270      	lrw      	r3, 0x20000028	// 27fc <GTC_IO_Init+0x8c>
    26be:	9340      	ld.w      	r2, (r3, 0)
    26c0:	9265      	ld.w      	r3, (r2, 0x14)
    26c2:	6cc0      	or      	r3, r0
    26c4:	b265      	st.w      	r3, (r2, 0x14)
		while(GTC->SR&GTC_ControlSet_x);
    26c6:	9266      	ld.w      	r3, (r2, 0x18)
    26c8:	68c0      	and      	r3, r0
    26ca:	3b40      	cmpnei      	r3, 0
    26cc:	0bfd      	bt      	0x26c6	// 26c6 <GTC_ControlSet_Configure+0x16>
    26ce:	07f6      	br      	0x26ba	// 26ba <GTC_ControlSet_Configure+0xa>

000026d0 <GTC_ConfigInterrupt_CMD>:
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void GTC_ConfigInterrupt_CMD(GTC_IMSCR_TypeDef GTC_IMSCR_X , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
    26d0:	3940      	cmpnei      	r1, 0
    26d2:	126b      	lrw      	r3, 0x20000028	// 27fc <GTC_IO_Init+0x8c>
    26d4:	0c06      	bf      	0x26e0	// 26e0 <GTC_ConfigInterrupt_CMD+0x10>
	{
		GTC->IMSCR  |= GTC_IMSCR_X;						//SET
    26d6:	9340      	ld.w      	r2, (r3, 0)
    26d8:	9267      	ld.w      	r3, (r2, 0x1c)
    26da:	6c0c      	or      	r0, r3
    26dc:	b207      	st.w      	r0, (r2, 0x1c)
	}
	else
	{
		GTC->IMSCR  &= ~GTC_IMSCR_X;					//CLR
	}
}
    26de:	783c      	rts
		GTC->IMSCR  &= ~GTC_IMSCR_X;					//CLR
    26e0:	9360      	ld.w      	r3, (r3, 0)
    26e2:	9347      	ld.w      	r2, (r3, 0x1c)
    26e4:	6c02      	nor      	r0, r0
    26e6:	6808      	and      	r0, r2
    26e8:	b307      	st.w      	r0, (r3, 0x1c)
}
    26ea:	07fa      	br      	0x26de	// 26de <GTC_ConfigInterrupt_CMD+0xe>

000026ec <GTC_SoftwareReset>:
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void GTC_SoftwareReset(void)
{
	GTC->SRR = GTC_SWRST;							// Software reset
    26ec:	1264      	lrw      	r3, 0x20000028	// 27fc <GTC_IO_Init+0x8c>
    26ee:	3201      	movi      	r2, 1
    26f0:	9360      	ld.w      	r3, (r3, 0)
    26f2:	b343      	st.w      	r2, (r3, 0xc)
}
    26f4:	783c      	rts

000026f6 <GTC_Start>:
//gtc start
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void GTC_Start(void)
{
    26f6:	14d0      	push      	r15
    26f8:	3001      	movi      	r0, 1
    26fa:	e3ffffa1 	bsr      	0x263c	// 263c <GTC_ControlSet_Configure.part.0>
	GTC_ControlSet_Configure (GTC_ControlSet_start_stop , ENABLE); 
}
    26fe:	1490      	pop      	r15

00002700 <GTC_start_stop>:
    2700:	14d0      	push      	r15
    2702:	e3fffffa 	bsr      	0x26f6	// 26f6 <GTC_Start>
    2706:	1490      	pop      	r15

00002708 <GTC_Stop>:
//gtc stop
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void GTC_Stop(void)
{
    2708:	14d0      	push      	r15
	GTC_ControlSet_Configure (GTC_ControlSet_start_stop , DISABLE); 
    270a:	3100      	movi      	r1, 0
    270c:	3001      	movi      	r0, 1
    270e:	e3ffffd1 	bsr      	0x26b0	// 26b0 <GTC_ControlSet_Configure>
}
    2712:	1490      	pop      	r15

00002714 <GTC_Set_Period>:
//gtc counter period DATA read 
//EntryParameter:loadCounter_PRDR,loadCounter_PULR
//ReturnValue:Conter prdr register value
/*************************************************************/  
void GTC_Set_Period(U32_T loadCounter_PRDR , U32_T loadCounter_PULR)
{
    2714:	14c1      	push      	r4
	GTC->CSR = (GTC->CSR & 0xFFFFFFFD) | 0x02;
    2716:	117a      	lrw      	r3, 0x20000028	// 27fc <GTC_IO_Init+0x8c>
	while(!((GTC->SR & 0x02)==0X02));
    2718:	3402      	movi      	r4, 2
	GTC->CSR = (GTC->CSR & 0xFFFFFFFD) | 0x02;
    271a:	9360      	ld.w      	r3, (r3, 0)
    271c:	9344      	ld.w      	r2, (r3, 0x10)
    271e:	3aa1      	bseti      	r2, r2, 1
    2720:	b344      	st.w      	r2, (r3, 0x10)
	while(!((GTC->SR & 0x02)==0X02));
    2722:	9346      	ld.w      	r2, (r3, 0x18)
    2724:	6890      	and      	r2, r4
    2726:	3a40      	cmpnei      	r2, 0
    2728:	0ffd      	bf      	0x2722	// 2722 <GTC_Set_Period+0xe>
	GTC->PRDR = loadCounter_PRDR;											//Period of GTC date register
    272a:	b30d      	st.w      	r0, (r3, 0x34)
	GTC->PULR = loadCounter_PULR;											//Pulse of GTC date register
    272c:	b32e      	st.w      	r1, (r3, 0x38)
}
    272e:	1481      	pop      	r4

00002730 <GTC_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTC_Int_Enable(void)
{
    INTC_ISER_WRITE(TC1_INT);    
    2730:	1176      	lrw      	r3, 0x20000064	// 2808 <GTC_IO_Init+0x98>
    2732:	3280      	movi      	r2, 128
    2734:	9360      	ld.w      	r3, (r3, 0)
    2736:	23ff      	addi      	r3, 256
    2738:	4243      	lsli      	r2, r2, 3
    273a:	b340      	st.w      	r2, (r3, 0)
}
    273c:	783c      	rts

0000273e <GTC_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTC_Int_Disable(void)
{
    INTC_ICER_WRITE(TC1_INT);    
    273e:	1173      	lrw      	r3, 0x20000064	// 2808 <GTC_IO_Init+0x98>
    2740:	32c0      	movi      	r2, 192
    2742:	9360      	ld.w      	r3, (r3, 0)
    2744:	4241      	lsli      	r2, r2, 1
    2746:	60c8      	addu      	r3, r2
    2748:	3280      	movi      	r2, 128
    274a:	4243      	lsli      	r2, r2, 3
    274c:	b340      	st.w      	r2, (r3, 0)
}
    274e:	783c      	rts

00002750 <GTC_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTC_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(TC1_INT);    
    2750:	116e      	lrw      	r3, 0x20000064	// 2808 <GTC_IO_Init+0x98>
    2752:	3280      	movi      	r2, 128
    2754:	9360      	ld.w      	r3, (r3, 0)
    2756:	23ff      	addi      	r3, 256
    2758:	4243      	lsli      	r2, r2, 3
    275a:	b350      	st.w      	r2, (r3, 0x40)
}
    275c:	783c      	rts

0000275e <GTC_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTC_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(TC1_INT);    
    275e:	116b      	lrw      	r3, 0x20000064	// 2808 <GTC_IO_Init+0x98>
    2760:	32e0      	movi      	r2, 224
    2762:	9360      	ld.w      	r3, (r3, 0)
    2764:	4241      	lsli      	r2, r2, 1
    2766:	60c8      	addu      	r3, r2
    2768:	3280      	movi      	r2, 128
    276a:	4243      	lsli      	r2, r2, 3
    276c:	b340      	st.w      	r2, (r3, 0)
}
    276e:	783c      	rts

00002770 <GTC_IO_Init>:
//GTC_IO_G;GTC_IO_TXOUT(0->PB0.00 ;1->PA0.06;2->PC0.02;3->PA0.15),GTC_IO_TCLK(0->PA0.0),GTC_IO_TCAPX(0->PA1.0;1->PA1.1)
//ReturnValue:NONE
/*************************************************************/
void GTC_IO_Init(GTC_IO_MODE_TypeDef  GTC_IO_MODE_X , U8_T GTC_IO_G )
{
	if(GTC_IO_MODE_X==GTC_IO_TXOUT)
    2770:	3841      	cmpnei      	r0, 1
    2772:	082c      	bt      	0x27ca	// 27ca <GTC_IO_Init+0x5a>
	{
		if(GTC_IO_G==0)
    2774:	3940      	cmpnei      	r1, 0
    2776:	0809      	bt      	0x2788	// 2788 <GTC_IO_Init+0x18>
		{
			GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFFF0)|0x00000006;										//T1OUT(PB0.00->AF3)
    2778:	1165      	lrw      	r3, 0x20000048	// 280c <GTC_IO_Init+0x9c>
	}
	else if(GTC_IO_MODE_X==GTC_IO_TCAPX)
	{
		if(GTC_IO_G==0)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFFF0)|0x00000006;										//TCAP1(PA1.0->AF3)
    277a:	9340      	ld.w      	r2, (r3, 0)
    277c:	9260      	ld.w      	r3, (r2, 0)
    277e:	310f      	movi      	r1, 15
    2780:	68c5      	andn      	r3, r1
    2782:	3ba1      	bseti      	r3, r3, 1
    2784:	3ba2      	bseti      	r3, r3, 2
    2786:	042d      	br      	0x27e0	// 27e0 <GTC_IO_Init+0x70>
		else if(GTC_IO_G==1)
    2788:	3941      	cmpnei      	r1, 1
    278a:	080b      	bt      	0x27a0	// 27a0 <GTC_IO_Init+0x30>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XF0FFFFFF)|0x05000000;										//T1OUT(PA0.06->AF2)
    278c:	1161      	lrw      	r3, 0x20000050	// 2810 <GTC_IO_Init+0xa0>
    278e:	32f0      	movi      	r2, 240
    2790:	9320      	ld.w      	r1, (r3, 0)
    2792:	9160      	ld.w      	r3, (r1, 0)
    2794:	4254      	lsli      	r2, r2, 20
    2796:	68c9      	andn      	r3, r2
    2798:	3bb8      	bseti      	r3, r3, 24
    279a:	3bba      	bseti      	r3, r3, 26
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFF0FF)|0x00000500;										//T1OUT(PC0.02->AF2)
    279c:	b160      	st.w      	r3, (r1, 0)
		else if(GTC_IO_G==1)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFF0F)|0x00000040;										//TCAP1(PA1.1->AF1)
		}
	}
}
    279e:	783c      	rts
		else if(GTC_IO_G==2)
    27a0:	3942      	cmpnei      	r1, 2
    27a2:	080a      	bt      	0x27b6	// 27b6 <GTC_IO_Init+0x46>
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFF0FF)|0x00000500;										//T1OUT(PC0.02->AF2)
    27a4:	107c      	lrw      	r3, 0x20000044	// 2814 <GTC_IO_Init+0xa4>
    27a6:	32f0      	movi      	r2, 240
    27a8:	9320      	ld.w      	r1, (r3, 0)
    27aa:	9160      	ld.w      	r3, (r1, 0)
    27ac:	4244      	lsli      	r2, r2, 4
    27ae:	68c9      	andn      	r3, r2
    27b0:	3ba8      	bseti      	r3, r3, 8
    27b2:	3baa      	bseti      	r3, r3, 10
    27b4:	07f4      	br      	0x279c	// 279c <GTC_IO_Init+0x2c>
		else if(GTC_IO_G==3)
    27b6:	3943      	cmpnei      	r1, 3
    27b8:	0bf3      	bt      	0x279e	// 279e <GTC_IO_Init+0x2e>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x40000000;										//T1OUT(PA0.15->AF1)
    27ba:	1076      	lrw      	r3, 0x20000050	// 2810 <GTC_IO_Init+0xa0>
    27bc:	9340      	ld.w      	r2, (r3, 0)
    27be:	9261      	ld.w      	r3, (r2, 0x4)
    27c0:	4364      	lsli      	r3, r3, 4
    27c2:	4b64      	lsri      	r3, r3, 4
    27c4:	3bbe      	bseti      	r3, r3, 30
    27c6:	b261      	st.w      	r3, (r2, 0x4)
    27c8:	07eb      	br      	0x279e	// 279e <GTC_IO_Init+0x2e>
	else if(GTC_IO_MODE_X==GTC_IO_TCLK)
    27ca:	3842      	cmpnei      	r0, 2
    27cc:	080c      	bt      	0x27e4	// 27e4 <GTC_IO_Init+0x74>
		if(GTC_IO_G==0)
    27ce:	3940      	cmpnei      	r1, 0
    27d0:	0be7      	bt      	0x279e	// 279e <GTC_IO_Init+0x2e>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000005;										//TCLK(PA0.0->AF2)
    27d2:	1070      	lrw      	r3, 0x20000050	// 2810 <GTC_IO_Init+0xa0>
    27d4:	310f      	movi      	r1, 15
    27d6:	9340      	ld.w      	r2, (r3, 0)
    27d8:	9260      	ld.w      	r3, (r2, 0)
    27da:	68c5      	andn      	r3, r1
    27dc:	3ba0      	bseti      	r3, r3, 0
    27de:	3ba2      	bseti      	r3, r3, 2
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFF0F)|0x00000040;										//TCAP1(PA1.1->AF1)
    27e0:	b260      	st.w      	r3, (r2, 0)
}
    27e2:	07de      	br      	0x279e	// 279e <GTC_IO_Init+0x2e>
	else if(GTC_IO_MODE_X==GTC_IO_TCAPX)
    27e4:	3843      	cmpnei      	r0, 3
    27e6:	0bdc      	bt      	0x279e	// 279e <GTC_IO_Init+0x2e>
		if(GTC_IO_G==0)
    27e8:	3940      	cmpnei      	r1, 0
    27ea:	0803      	bt      	0x27f0	// 27f0 <GTC_IO_Init+0x80>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFFF0)|0x00000006;										//TCAP1(PA1.0->AF3)
    27ec:	106b      	lrw      	r3, 0x2000004c	// 2818 <GTC_IO_Init+0xa8>
    27ee:	07c6      	br      	0x277a	// 277a <GTC_IO_Init+0xa>
		else if(GTC_IO_G==1)
    27f0:	3941      	cmpnei      	r1, 1
    27f2:	0bd6      	bt      	0x279e	// 279e <GTC_IO_Init+0x2e>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFF0F)|0x00000040;										//TCAP1(PA1.1->AF1)
    27f4:	1069      	lrw      	r3, 0x2000004c	// 2818 <GTC_IO_Init+0xa8>
    27f6:	31f0      	movi      	r1, 240
    27f8:	0412      	br      	0x281c	// 281c <GTC_IO_Init+0xac>
    27fa:	0000      	bkpt
    27fc:	20000028 	.long	0x20000028
    2800:	0011000a 	.long	0x0011000a
    2804:	80000001 	.long	0x80000001
    2808:	20000064 	.long	0x20000064
    280c:	20000048 	.long	0x20000048
    2810:	20000050 	.long	0x20000050
    2814:	20000044 	.long	0x20000044
    2818:	2000004c 	.long	0x2000004c
    281c:	9340      	ld.w      	r2, (r3, 0)
    281e:	9260      	ld.w      	r3, (r2, 0)
    2820:	68c5      	andn      	r3, r1
    2822:	3ba6      	bseti      	r3, r3, 6
    2824:	07de      	br      	0x27e0	// 27e0 <GTC_IO_Init+0x70>
	...

00002828 <STC16_RESET_VALUE>:
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/  
void STC16_RESET_VALUE(void)									//reset value
{
  	ST16->IDR=STC_IDR_RST;          			/**< IDR reset value      */
    2828:	106e      	lrw      	r3, 0x20000024	// 2860 <STC16_RESET_VALUE+0x38>
    282a:	104f      	lrw      	r2, 0x41000a	// 2864 <STC16_RESET_VALUE+0x3c>
    282c:	9360      	ld.w      	r3, (r3, 0)
    282e:	b340      	st.w      	r2, (r3, 0)
   	ST16->CEDR=STC_CEDR_RST;		 			/**< CEDR reset value     */	
    2830:	3200      	movi      	r2, 0
    2832:	b341      	st.w      	r2, (r3, 0x4)
   	ST16->RSSR=STC_RSSR_RST;					/**< RSSR reset value     */	
    2834:	b342      	st.w      	r2, (r3, 0x8)
   	ST16->IMSCR=STC_IMSCR_RST;					/**< IMSCR reset value    */	
    2836:	b343      	st.w      	r2, (r3, 0xc)
   	ST16->RISR=STC_RISR_RST;					/**< RISR reset value     */	
    2838:	b344      	st.w      	r2, (r3, 0x10)
  	ST16->MISR=STC_MISR_RST;					/**< MISR reset value     */	
    283a:	b345      	st.w      	r2, (r3, 0x14)
   	ST16->ICR=STC_ICR_RST;						/**< ICR reset value      */	
    283c:	b346      	st.w      	r2, (r3, 0x18)
   	ST16->SR=STC_SR_RST;						/**< SR reset value       */	
    283e:	b347      	st.w      	r2, (r3, 0x1c)
   	ST16->MR=STC_MR_RST;						/**< MR reset value       */	
    2840:	b349      	st.w      	r2, (r3, 0x24)
  	ST16->CNTBR=STC_CNTBR_RST;					/**< CNTBR reset value    */
    2842:	b34c      	st.w      	r2, (r3, 0x30)
   	ST16->CNTR=STC_CNTR_RST;					/**< CNTR reset value     */
    2844:	b34d      	st.w      	r2, (r3, 0x34)
   	ST16->CDR=STC_CDR_RST;						/**< CDR reset value      */
    2846:	b34e      	st.w      	r2, (r3, 0x38)
   	ST16->PCNTR=STC_PCNTR_RST;					/**< PCNTR reset value    */
    2848:	b354      	st.w      	r2, (r3, 0x50)
   	ST16->CRR=STC_CRR_RST;						/**< CRR reset value      */
    284a:	237f      	addi      	r3, 128
    284c:	b340      	st.w      	r2, (r3, 0)
   	ST16->CMR=STC_CMR_RST;						/**< CMR reset value      */
    284e:	b341      	st.w      	r2, (r3, 0x4)
  	ST16->CIMSCR=STC_CIMSCR_RST;				/**< CIMSCR reset value   */	
    2850:	b342      	st.w      	r2, (r3, 0x8)
   	ST16->CRISR=STC_CRISR_RST;					/**< CRISR reset value    */	
    2852:	b343      	st.w      	r2, (r3, 0xc)
   	ST16->CMISR=STC_CMISR_RST;					/**< CMISR reset value    */
    2854:	b344      	st.w      	r2, (r3, 0x10)
   	ST16->CICR=STC_CICR_RST;					/**< CICR reset value     */	
    2856:	b345      	st.w      	r2, (r3, 0x14)
   	ST16->CAPSR=STC_CAPSR_RST;					/**< CAPSR reset value    */
    2858:	b347      	st.w      	r2, (r3, 0x1c)
   	ST16->CC0R=STC_CC0R_RST;					/**< CC0R reset value     */
    285a:	b350      	st.w      	r2, (r3, 0x40)
   	ST16->CC1R=STC_CC1R_RST;					/**< CC1R reset value     */
    285c:	b351      	st.w      	r2, (r3, 0x44)
}
    285e:	783c      	rts
    2860:	20000024 	.long	0x20000024
    2864:	0041000a 	.long	0x0041000a

00002868 <STC16_IO_Init>:
//STC16_IO_CAP1(0->PA1.2(AF1))
//ReturnValue:NONE
/*************************************************************/
void STC16_IO_Init(ST16_IO_MODE_TypeDef  STC16_IO_MODE_X , U8_T STC16_IO_G )
{
	if(STC16_IO_MODE_X==STC16_IO_CAP0)
    2868:	3840      	cmpnei      	r0, 0
    286a:	0815      	bt      	0x2894	// 2894 <STC16_IO_Init+0x2c>
	{
		if(STC16_IO_G==0)
    286c:	3940      	cmpnei      	r1, 0
    286e:	080a      	bt      	0x2882	// 2882 <STC16_IO_Init+0x1a>
		{
			GPIOA0->CONLR=(GPIOA0->CONLR & 0X0FFFFFFF)|0x50000000;										//STC16_IO_CAP0(PA0.7->AF2)
    2870:	127f      	lrw      	r3, 0x20000050	// 29ec <STC16_CNR_CC0_CC1_Load+0xa>
    2872:	9340      	ld.w      	r2, (r3, 0)
    2874:	9260      	ld.w      	r3, (r2, 0)
    2876:	4364      	lsli      	r3, r3, 4
    2878:	4b64      	lsri      	r3, r3, 4
    287a:	3bbc      	bseti      	r3, r3, 28
    287c:	3bbe      	bseti      	r3, r3, 30
		}
		else if(STC16_IO_G==1)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFFF0)|0x00000004;										//STC16_IO_CAP0(PA1.0->AF1)
    287e:	b260      	st.w      	r3, (r2, 0)
		if(STC16_IO_G==0)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFF0FF)|0x00000400;										//STC16_IO_CAP0(PA1.2->AF1)
		}
	}
}
    2880:	783c      	rts
		else if(STC16_IO_G==1)
    2882:	3941      	cmpnei      	r1, 1
    2884:	0bfe      	bt      	0x2880	// 2880 <STC16_IO_Init+0x18>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFFF0)|0x00000004;										//STC16_IO_CAP0(PA1.0->AF1)
    2886:	127b      	lrw      	r3, 0x2000004c	// 29f0 <STC16_CNR_CC0_CC1_Load+0xe>
    2888:	310f      	movi      	r1, 15
    288a:	9340      	ld.w      	r2, (r3, 0)
    288c:	9260      	ld.w      	r3, (r2, 0)
    288e:	68c5      	andn      	r3, r1
    2890:	3ba2      	bseti      	r3, r3, 2
    2892:	07f6      	br      	0x287e	// 287e <STC16_IO_Init+0x16>
	else if(STC16_IO_MODE_X==STC16_IO_CAP1)
    2894:	3841      	cmpnei      	r0, 1
    2896:	0bf5      	bt      	0x2880	// 2880 <STC16_IO_Init+0x18>
		if(STC16_IO_G==0)
    2898:	3940      	cmpnei      	r1, 0
    289a:	0bf3      	bt      	0x2880	// 2880 <STC16_IO_Init+0x18>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFF0FF)|0x00000400;										//STC16_IO_CAP0(PA1.2->AF1)
    289c:	1275      	lrw      	r3, 0x2000004c	// 29f0 <STC16_CNR_CC0_CC1_Load+0xe>
    289e:	32f0      	movi      	r2, 240
    28a0:	9320      	ld.w      	r1, (r3, 0)
    28a2:	9160      	ld.w      	r3, (r1, 0)
    28a4:	4244      	lsli      	r2, r2, 4
    28a6:	68c9      	andn      	r3, r2
    28a8:	3baa      	bseti      	r3, r3, 10
    28aa:	b160      	st.w      	r3, (r1, 0)
}
    28ac:	07ea      	br      	0x2880	// 2880 <STC16_IO_Init+0x18>

000028ae <STC16_Clk_CMD>:
//EntryParameter:NewState
//NewState:DISABLE,ENABLE
//ReturnValue:NONE
/*************************************************************/
void STC16_Clk_CMD(FunctionalStatus NewState)
{
    28ae:	1272      	lrw      	r3, 0x20000024	// 29f4 <STC16_CNR_CC0_CC1_Load+0x12>
	if(NewState != DISABLE)
    28b0:	3840      	cmpnei      	r0, 0
	{
		ST16->CEDR |= 0x01;							//enable STC16 clk 
    28b2:	9340      	ld.w      	r2, (r3, 0)
    28b4:	9261      	ld.w      	r3, (r2, 0x4)
	if(NewState != DISABLE)
    28b6:	0c04      	bf      	0x28be	// 28be <STC16_Clk_CMD+0x10>
		ST16->CEDR |= 0x01;							//enable STC16 clk 
    28b8:	3ba0      	bseti      	r3, r3, 0
	}
	else
	{
		ST16->CEDR &= 0XFFFFFFFE;					//Disable STC16 clk 
    28ba:	b261      	st.w      	r3, (r2, 0x4)
	}
}
    28bc:	783c      	rts
		ST16->CEDR &= 0XFFFFFFFE;					//Disable STC16 clk 
    28be:	3b80      	bclri      	r3, r3, 0
    28c0:	07fd      	br      	0x28ba	// 28ba <STC16_Clk_CMD+0xc>

000028c2 <STC16_Softreset>:
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void STC16_Softreset(void)
{
	ST16->RSSR|=0x80000000;
    28c2:	126d      	lrw      	r3, 0x20000024	// 29f4 <STC16_CNR_CC0_CC1_Load+0x12>
    28c4:	9340      	ld.w      	r2, (r3, 0)
    28c6:	9262      	ld.w      	r3, (r2, 0x8)
    28c8:	3bbf      	bseti      	r3, r3, 31
    28ca:	b262      	st.w      	r3, (r2, 0x8)
}
    28cc:	783c      	rts

000028ce <STC16_Start>:
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void STC16_Start(void)
{
	ST16->RSSR|=0X01;									//STC16 start
    28ce:	126a      	lrw      	r3, 0x20000024	// 29f4 <STC16_CNR_CC0_CC1_Load+0x12>
    28d0:	9360      	ld.w      	r3, (r3, 0)
    28d2:	9342      	ld.w      	r2, (r3, 0x8)
    28d4:	3aa0      	bseti      	r2, r2, 0
    28d6:	b342      	st.w      	r2, (r3, 0x8)
	while(!(ST16->SR&0X80000000));						//计数器正在工作
    28d8:	9347      	ld.w      	r2, (r3, 0x1c)
    28da:	3adf      	btsti      	r2, 31
    28dc:	0ffe      	bf      	0x28d8	// 28d8 <STC16_Start+0xa>
}
    28de:	783c      	rts

000028e0 <STC16_stop>:
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void STC16_stop(void)
{
	ST16->RSSR|=0X02;									//STC16 stop
    28e0:	1265      	lrw      	r3, 0x20000024	// 29f4 <STC16_CNR_CC0_CC1_Load+0x12>
    28e2:	9360      	ld.w      	r3, (r3, 0)
    28e4:	9342      	ld.w      	r2, (r3, 0x8)
    28e6:	3aa1      	bseti      	r2, r2, 1
    28e8:	b342      	st.w      	r2, (r3, 0x8)
	while(ST16->SR&0X80000000);							//计数器没有工作
    28ea:	9347      	ld.w      	r2, (r3, 0x1c)
    28ec:	3adf      	btsti      	r2, 31
    28ee:	0bfe      	bt      	0x28ea	// 28ea <STC16_stop+0xa>
}
    28f0:	783c      	rts

000028f2 <STC16_Channel0_CMD>:
//EntryParameter:NewState
//NewState:DISABLE,ENABLE
//ReturnValue:NONE
/*************************************************************/ 
void STC16_Channel0_CMD(FunctionalStatus NewState)
{
    28f2:	1261      	lrw      	r3, 0x20000024	// 29f4 <STC16_CNR_CC0_CC1_Load+0x12>
	if(NewState != DISABLE)
    28f4:	3840      	cmpnei      	r0, 0
	{
		ST16->CRR |= 0x01;							//enable STC16 Channel0 clk 
    28f6:	9360      	ld.w      	r3, (r3, 0)
    28f8:	237f      	addi      	r3, 128
    28fa:	9340      	ld.w      	r2, (r3, 0)
	if(NewState != DISABLE)
    28fc:	0c04      	bf      	0x2904	// 2904 <STC16_Channel0_CMD+0x12>
		ST16->CRR |= 0x01;							//enable STC16 Channel0 clk 
    28fe:	3aa0      	bseti      	r2, r2, 0
	}
	else
	{
		ST16->CRR &= 0XFFFFFFFE;						//Disable STC16 Channel0 clk 
    2900:	b340      	st.w      	r2, (r3, 0)
	}
}
    2902:	783c      	rts
		ST16->CRR &= 0XFFFFFFFE;						//Disable STC16 Channel0 clk 
    2904:	3a80      	bclri      	r2, r2, 0
    2906:	07fd      	br      	0x2900	// 2900 <STC16_Channel0_CMD+0xe>

00002908 <STC16_Channel1_CMD>:
//STC16 Channel1 CMD
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void STC16_Channel1_CMD(FunctionalStatus NewState)
{
    2908:	117b      	lrw      	r3, 0x20000024	// 29f4 <STC16_CNR_CC0_CC1_Load+0x12>
	if(NewState != DISABLE)
    290a:	3840      	cmpnei      	r0, 0
	{
		ST16->CRR |= 0x02;							//enable STC16 Channel1 clk 
    290c:	9360      	ld.w      	r3, (r3, 0)
    290e:	237f      	addi      	r3, 128
    2910:	9340      	ld.w      	r2, (r3, 0)
	if(NewState != DISABLE)
    2912:	0c04      	bf      	0x291a	// 291a <STC16_Channel1_CMD+0x12>
		ST16->CRR |= 0x02;							//enable STC16 Channel1 clk 
    2914:	3aa1      	bseti      	r2, r2, 1
	}
	else
	{
		ST16->CRR &= 0XFFFFFFFD;						//Disable STC16 Channel1 clk 
    2916:	b340      	st.w      	r2, (r3, 0)
	}
}
    2918:	783c      	rts
		ST16->CRR &= 0XFFFFFFFD;						//Disable STC16 Channel1 clk 
    291a:	3a81      	bclri      	r2, r2, 1
    291c:	07fd      	br      	0x2916	// 2916 <STC16_Channel1_CMD+0xe>

0000291e <STC16_MINT_CMD>:
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void STC16_MINT_CMD(STC16_MINT_TypeDef STC16_MINT_X , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
    291e:	3940      	cmpnei      	r1, 0
    2920:	1175      	lrw      	r3, 0x20000024	// 29f4 <STC16_CNR_CC0_CC1_Load+0x12>
    2922:	0c06      	bf      	0x292e	// 292e <STC16_MINT_CMD+0x10>
	{
		ST16->IMSCR |= STC16_MINT_X;					//SET
    2924:	9340      	ld.w      	r2, (r3, 0)
    2926:	9263      	ld.w      	r3, (r2, 0xc)
    2928:	6c0c      	or      	r0, r3
    292a:	b203      	st.w      	r0, (r2, 0xc)
	}
	else
	{
		ST16->IMSCR &= ~ STC16_MINT_X;				//CLR
	}
}
    292c:	783c      	rts
		ST16->IMSCR &= ~ STC16_MINT_X;				//CLR
    292e:	9360      	ld.w      	r3, (r3, 0)
    2930:	9343      	ld.w      	r2, (r3, 0xc)
    2932:	6c02      	nor      	r0, r0
    2934:	6808      	and      	r0, r2
    2936:	b303      	st.w      	r0, (r3, 0xc)
}
    2938:	07fa      	br      	0x292c	// 292c <STC16_MINT_CMD+0xe>

0000293a <STC16_CINT_CMD>:
//STC16_CINT_X:ST16_CC0RI,ST16_CC1RI,ST16_CC0FI,ST16_CC1FI,ST16_Match0,ST16_Match1
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void STC16_CINT_CMD(STC16_CINT_TypeDef STC16_CINT_X , FunctionalStatus NewState)
{
    293a:	116f      	lrw      	r3, 0x20000024	// 29f4 <STC16_CNR_CC0_CC1_Load+0x12>
	if (NewState != DISABLE)
    293c:	3940      	cmpnei      	r1, 0
	{
		ST16->CIMSCR |=STC16_CINT_X;					//SET
    293e:	9360      	ld.w      	r3, (r3, 0)
    2940:	237f      	addi      	r3, 128
    2942:	9342      	ld.w      	r2, (r3, 0x8)
	if (NewState != DISABLE)
    2944:	0c04      	bf      	0x294c	// 294c <STC16_CINT_CMD+0x12>
		ST16->CIMSCR |=STC16_CINT_X;					//SET
    2946:	6c08      	or      	r0, r2
	}
	else
	{
		ST16->CIMSCR &=(~STC16_CINT_X);				//CLR
    2948:	b302      	st.w      	r0, (r3, 0x8)
	}
}
    294a:	783c      	rts
		ST16->CIMSCR &=(~STC16_CINT_X);				//CLR
    294c:	6c02      	nor      	r0, r0
    294e:	6808      	and      	r0, r2
    2950:	07fc      	br      	0x2948	// 2948 <STC16_CINT_CMD+0xe>

00002952 <STC16_Configure>:
//STC16_DIVN:0~0x0f
//ReturnValue:NONE
/*************************************************************/
void STC16_Configure(STC16_Count_mode_TypeDef STC16_Count_mode_X , STC16_Count_STOPTYPE_TypeDef STC16_Count_STOPTYPE
					 , STC16_CM0_Mode_TypeDef STC16_CM0_Mode_X , STC16_CM1_Mode_TypeDef STC16_CM1_Mode_X , int STC16_DIVM , int STC16_DIVN)
{
    2952:	14c4      	push      	r4-r7
    2954:	1421      	subi      	sp, sp, 4
    2956:	9885      	ld.w      	r4, (sp, 0x14)
    2958:	6dd3      	mov      	r7, r4
    295a:	9886      	ld.w      	r4, (sp, 0x18)
    295c:	b880      	st.w      	r4, (sp, 0)
    ST16->MR&=0xfefffdff;
	ST16->CDR&=0Xffff8000;
	ST16->CMR&=0XFFFFFFFA;
    295e:	3680      	movi      	r6, 128
    ST16->MR&=0xfefffdff;
    2960:	1185      	lrw      	r4, 0x20000024	// 29f4 <STC16_CNR_CC0_CC1_Load+0x12>
    2962:	9480      	ld.w      	r4, (r4, 0)
    2964:	94a9      	ld.w      	r5, (r4, 0x24)
    2966:	3d89      	bclri      	r5, r5, 9
    2968:	3d98      	bclri      	r5, r5, 24
    296a:	b4a9      	st.w      	r5, (r4, 0x24)
	ST16->CDR&=0Xffff8000;
    296c:	94ae      	ld.w      	r5, (r4, 0x38)
    296e:	4daf      	lsri      	r5, r5, 15
    2970:	45af      	lsli      	r5, r5, 15
    2972:	b4ae      	st.w      	r5, (r4, 0x38)
	ST16->CMR&=0XFFFFFFFA;
    2974:	6190      	addu      	r6, r4
    2976:	96a1      	ld.w      	r5, (r6, 0x4)
    2978:	3d80      	bclri      	r5, r5, 0
    297a:	3d82      	bclri      	r5, r5, 2
    297c:	b6a1      	st.w      	r5, (r6, 0x4)
	ST16->MR|=STC16_Count_mode_X|STC16_Count_STOPTYPE;
    297e:	94a9      	ld.w      	r5, (r4, 0x24)
    2980:	6c54      	or      	r1, r5
    2982:	6c04      	or      	r0, r1
    2984:	b409      	st.w      	r0, (r4, 0x24)
	ST16->CDR|=(STC16_DIVM<<4)|STC16_DIVN;
    2986:	4724      	lsli      	r1, r7, 4
    2988:	98a0      	ld.w      	r5, (sp, 0)
    298a:	940e      	ld.w      	r0, (r4, 0x38)
    298c:	6c54      	or      	r1, r5
    298e:	6c40      	or      	r1, r0
    2990:	b42e      	st.w      	r1, (r4, 0x38)
	ST16->CMR|=STC16_CM0_Mode_X|STC16_CM1_Mode_X;
    2992:	9621      	ld.w      	r1, (r6, 0x4)
    2994:	6cc4      	or      	r3, r1
    2996:	6c8c      	or      	r2, r3
    2998:	b641      	st.w      	r2, (r6, 0x4)
}
    299a:	1401      	addi      	sp, sp, 4
    299c:	1484      	pop      	r4-r7

0000299e <STC16_Channel0_Capture_LoadMode_set>:
//STC16_C0SR_X:STC16_C0SR_CaptureRise,STC16_C0SR_CaptureFall,STC16_C0SR_CaptureRiseFall
//ReturnValue:Conter prdr register value
/*************************************************************/ 
void STC16_Channel0_Capture_LoadMode_set(STC16_C0SR_TypeDef STC16_C0SR_X)
{
	ST16->CRR &= 0XFFFFFFFE;						//Disable STC16 Channel0 clk 
    299e:	1076      	lrw      	r3, 0x20000024	// 29f4 <STC16_CNR_CC0_CC1_Load+0x12>
    29a0:	9360      	ld.w      	r3, (r3, 0)
    29a2:	237f      	addi      	r3, 128
    29a4:	9340      	ld.w      	r2, (r3, 0)
    29a6:	3a80      	bclri      	r2, r2, 0
    29a8:	b340      	st.w      	r2, (r3, 0)
	ST16->CMR&=0XFFFCFFFF;
    29aa:	9341      	ld.w      	r2, (r3, 0x4)
    29ac:	3a90      	bclri      	r2, r2, 16
    29ae:	3a91      	bclri      	r2, r2, 17
    29b0:	b341      	st.w      	r2, (r3, 0x4)
	ST16->CMR|=STC16_C0SR_X;
    29b2:	9341      	ld.w      	r2, (r3, 0x4)
    29b4:	6c08      	or      	r0, r2
    29b6:	b301      	st.w      	r0, (r3, 0x4)
	ST16->CRR |= 0x01;							//enable STC16 Channel0 clk
    29b8:	9340      	ld.w      	r2, (r3, 0)
    29ba:	3aa0      	bseti      	r2, r2, 0
    29bc:	b340      	st.w      	r2, (r3, 0)
}
    29be:	783c      	rts

000029c0 <STC16_Channel1_Capture_LoadMode_set>:
//STC16_C1SR_X:STC16_C1SR_CaptureRise,STC16_C1SR_CaptureFall,STC16_C1SR_CaptureRiseFall
//ReturnValue:Conter prdr register value
/*************************************************************/ 
void STC16_Channel1_Capture_LoadMode_set(STC16_C1SR_TypeDef STC16_C1SR_X)
{
	ST16->CRR &= 0XFFFFFFFD;						//Disable STC16 Channel0 clk 
    29c0:	106d      	lrw      	r3, 0x20000024	// 29f4 <STC16_CNR_CC0_CC1_Load+0x12>
    29c2:	9360      	ld.w      	r3, (r3, 0)
    29c4:	237f      	addi      	r3, 128
    29c6:	9340      	ld.w      	r2, (r3, 0)
    29c8:	3a81      	bclri      	r2, r2, 1
    29ca:	b340      	st.w      	r2, (r3, 0)
	ST16->CMR&=0XFFF3FFFF;
    29cc:	9341      	ld.w      	r2, (r3, 0x4)
    29ce:	3a92      	bclri      	r2, r2, 18
    29d0:	3a93      	bclri      	r2, r2, 19
    29d2:	b341      	st.w      	r2, (r3, 0x4)
	ST16->CMR|=STC16_C1SR_X;
    29d4:	9341      	ld.w      	r2, (r3, 0x4)
    29d6:	6c08      	or      	r0, r2
    29d8:	b301      	st.w      	r0, (r3, 0x4)
	ST16->CRR |= 0x02;							//enable STC16 Channel0 clk
    29da:	9340      	ld.w      	r2, (r3, 0)
    29dc:	3aa1      	bseti      	r2, r2, 1
    29de:	b340      	st.w      	r2, (r3, 0)
}
    29e0:	783c      	rts

000029e2 <STC16_CNR_CC0_CC1_Load>:
//EntryParameter:loadCounter_PRDR,loadCounter_PULR
//ReturnValue:Conter prdr register value
/*************************************************************/ 
void STC16_CNR_CC0_CC1_Load(U16_T STC16_CNTR, U16_T STC16_CC0R , U16_T STC16_CC1R)
{
	ST16->CNTR=STC16_CNTR;
    29e2:	1065      	lrw      	r3, 0x20000024	// 29f4 <STC16_CNR_CC0_CC1_Load+0x12>
    29e4:	9360      	ld.w      	r3, (r3, 0)
    29e6:	b30d      	st.w      	r0, (r3, 0x34)
	ST16->CC0R=STC16_CC0R;
    29e8:	237f      	addi      	r3, 128
    29ea:	0407      	br      	0x29f8	// 29f8 <STC16_CNR_CC0_CC1_Load+0x16>
    29ec:	20000050 	.long	0x20000050
    29f0:	2000004c 	.long	0x2000004c
    29f4:	20000024 	.long	0x20000024
    29f8:	b330      	st.w      	r1, (r3, 0x40)
	ST16->CC1R=STC16_CC1R;
    29fa:	b351      	st.w      	r2, (r3, 0x44)
}
    29fc:	783c      	rts

000029fe <STC16_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void STC16_Int_Enable(void)
{
    INTC_ISER_WRITE(TC2_INT);    
    29fe:	1071      	lrw      	r3, 0x20000064	// 2a40 <STC16_Wakeup_Disable+0x14>
    2a00:	3280      	movi      	r2, 128
    2a02:	9360      	ld.w      	r3, (r3, 0)
    2a04:	23ff      	addi      	r3, 256
    2a06:	4244      	lsli      	r2, r2, 4
    2a08:	b340      	st.w      	r2, (r3, 0)
}
    2a0a:	783c      	rts

00002a0c <STC16_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void STC16_Int_Disable(void)
{
    INTC_ICER_WRITE(TC2_INT);    
    2a0c:	106d      	lrw      	r3, 0x20000064	// 2a40 <STC16_Wakeup_Disable+0x14>
    2a0e:	32c0      	movi      	r2, 192
    2a10:	9360      	ld.w      	r3, (r3, 0)
    2a12:	4241      	lsli      	r2, r2, 1
    2a14:	60c8      	addu      	r3, r2
    2a16:	3280      	movi      	r2, 128
    2a18:	4244      	lsli      	r2, r2, 4
    2a1a:	b340      	st.w      	r2, (r3, 0)
}
    2a1c:	783c      	rts

00002a1e <STC16_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void STC16_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(TC2_INT);    
    2a1e:	1069      	lrw      	r3, 0x20000064	// 2a40 <STC16_Wakeup_Disable+0x14>
    2a20:	3280      	movi      	r2, 128
    2a22:	9360      	ld.w      	r3, (r3, 0)
    2a24:	23ff      	addi      	r3, 256
    2a26:	4244      	lsli      	r2, r2, 4
    2a28:	b350      	st.w      	r2, (r3, 0x40)
}
    2a2a:	783c      	rts

00002a2c <STC16_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void STC16_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(TC2_INT);    
    2a2c:	1065      	lrw      	r3, 0x20000064	// 2a40 <STC16_Wakeup_Disable+0x14>
    2a2e:	32e0      	movi      	r2, 224
    2a30:	9360      	ld.w      	r3, (r3, 0)
    2a32:	4241      	lsli      	r2, r2, 1
    2a34:	60c8      	addu      	r3, r2
    2a36:	3280      	movi      	r2, 128
    2a38:	4244      	lsli      	r2, r2, 4
    2a3a:	b340      	st.w      	r2, (r3, 0)
}
    2a3c:	783c      	rts
    2a3e:	0000      	bkpt
    2a40:	20000064 	.long	0x20000064

00002a44 <CTC_RESET_VALUE>:
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/  
void CTC_RESET_VALUE(void)									//reset value
{
  	CTC->IDR=CTC_IDR_RST;          				/**< IDR reset value      */
    2a44:	106a      	lrw      	r3, 0x20000020	// 2a6c <CTC_RESET_VALUE+0x28>
    2a46:	104b      	lrw      	r2, 0x1002d	// 2a70 <CTC_RESET_VALUE+0x2c>
    2a48:	9360      	ld.w      	r3, (r3, 0)
    2a4a:	b340      	st.w      	r2, (r3, 0)
   	CTC->CSSR=CTC_CSSR_RST;		 				/**< CSSR reset value     */	
    2a4c:	3201      	movi      	r2, 1
    2a4e:	b341      	st.w      	r2, (r3, 0x4)
   	CTC->CEDR=CTC_CEDR_RST;						/**< CEDR reset value     */
    2a50:	3200      	movi      	r2, 0
    2a52:	b342      	st.w      	r2, (r3, 0x8)
	CTC->SRR=CTC_SRR_RST;						/**< SRR reset value      */
    2a54:	b343      	st.w      	r2, (r3, 0xc)
	CTC->CR=CTC_CR_RST;							/**< CR reset value       */
    2a56:	3230      	movi      	r2, 48
    2a58:	b344      	st.w      	r2, (r3, 0x10)
	CTC->PRDR=CTC_PRDR_RST;						/**< PRDR reset value     */
    2a5a:	3201      	movi      	r2, 1
    2a5c:	b345      	st.w      	r2, (r3, 0x14)
	CTC->TIMDR=CTC_TIMDR_RST;					/**< TIMDR reset value    */
    2a5e:	3200      	movi      	r2, 0
    2a60:	b346      	st.w      	r2, (r3, 0x18)
	CTC->IMCR=CTC_IMCR_RST;						/**< IMCR reset value     */
    2a62:	b347      	st.w      	r2, (r3, 0x1c)
	CTC->RISR=CTC_RISR_RST;						/**< RISR reset value     */
    2a64:	b348      	st.w      	r2, (r3, 0x20)
	CTC->MISR=CTC_MISR_RST;						/**< MISR reset value     */
    2a66:	b349      	st.w      	r2, (r3, 0x24)
	CTC->ICR=CTC_ICR_RST;						/**< ICR reset value      */
    2a68:	b34a      	st.w      	r2, (r3, 0x28)
}
    2a6a:	783c      	rts
    2a6c:	20000020 	.long	0x20000020
    2a70:	0001002d 	.long	0x0001002d

00002a74 <CTC_IO_Init>:
//(0->PD0.0(AF4);1->PC0.2(AF3))
//ReturnValue:NONE
/*************************************************************/
void CTC_IO_Init(U8_T CTC_IO_G )
{
	if(CTC_IO_G==0)
    2a74:	3840      	cmpnei      	r0, 0
    2a76:	080a      	bt      	0x2a8a	// 2a8a <CTC_IO_Init+0x16>
	{
		GPIOD0->CONLR=(GPIOD0->CONLR & 0XFFFFFFF0)|0x00000007;										//CTC_IO_BUZZ(PD0.0->AF4)
    2a78:	117d      	lrw      	r3, 0x20000040	// 2b6c <CTC_stop+0x14>
    2a7a:	310f      	movi      	r1, 15
    2a7c:	9340      	ld.w      	r2, (r3, 0)
    2a7e:	9260      	ld.w      	r3, (r2, 0)
    2a80:	68c5      	andn      	r3, r1
    2a82:	3107      	movi      	r1, 7
    2a84:	6cc4      	or      	r3, r1
    2a86:	b260      	st.w      	r3, (r2, 0)
	}
	else if(CTC_IO_G==1)
	{
		GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFF0FF)|0x00000600;										//CTC_IO_BUZZ(PC0.2->AF3)
	}
}
    2a88:	783c      	rts
	else if(CTC_IO_G==1)
    2a8a:	3841      	cmpnei      	r0, 1
    2a8c:	0bfe      	bt      	0x2a88	// 2a88 <CTC_IO_Init+0x14>
		GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFF0FF)|0x00000600;										//CTC_IO_BUZZ(PC0.2->AF3)
    2a8e:	1179      	lrw      	r3, 0x20000044	// 2b70 <CTC_stop+0x18>
    2a90:	32f0      	movi      	r2, 240
    2a92:	9320      	ld.w      	r1, (r3, 0)
    2a94:	9160      	ld.w      	r3, (r1, 0)
    2a96:	4244      	lsli      	r2, r2, 4
    2a98:	68c9      	andn      	r3, r2
    2a9a:	3ba9      	bseti      	r3, r3, 9
    2a9c:	3baa      	bseti      	r3, r3, 10
    2a9e:	b160      	st.w      	r3, (r1, 0)
}
    2aa0:	07f4      	br      	0x2a88	// 2a88 <CTC_IO_Init+0x14>

00002aa2 <CTC_Clk_CMD>:
//EntryParameter:NewState
//NewState:DISABLE,ENABLE
//ReturnValue:NONE
/*************************************************************/
void CTC_Clk_CMD(FunctionalStatus NewState)
{
    2aa2:	1175      	lrw      	r3, 0x20000020	// 2b74 <CTC_stop+0x1c>
	if(NewState != DISABLE)
    2aa4:	3840      	cmpnei      	r0, 0
	{
		CTC->CEDR |= 0x03;							//enable CTC clk 
    2aa6:	9340      	ld.w      	r2, (r3, 0)
    2aa8:	9262      	ld.w      	r3, (r2, 0x8)
	if(NewState != DISABLE)
    2aaa:	0c05      	bf      	0x2ab4	// 2ab4 <CTC_Clk_CMD+0x12>
		CTC->CEDR |= 0x03;							//enable CTC clk 
    2aac:	3ba0      	bseti      	r3, r3, 0
    2aae:	3ba1      	bseti      	r3, r3, 1
	}
	else
	{
		CTC->CEDR &= 0XFFFFFFFE;					//Disable CTC clk 
    2ab0:	b262      	st.w      	r3, (r2, 0x8)
	}
}
    2ab2:	783c      	rts
		CTC->CEDR &= 0XFFFFFFFE;					//Disable CTC clk 
    2ab4:	3b80      	bclri      	r3, r3, 0
    2ab6:	07fd      	br      	0x2ab0	// 2ab0 <CTC_Clk_CMD+0xe>

00002ab8 <CTC_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CTC_Int_Enable(void)
{
    INTC_ISER_WRITE(TC3_INT);    
    2ab8:	1170      	lrw      	r3, 0x20000064	// 2b78 <CTC_stop+0x20>
    2aba:	3280      	movi      	r2, 128
    2abc:	9360      	ld.w      	r3, (r3, 0)
    2abe:	23ff      	addi      	r3, 256
    2ac0:	4245      	lsli      	r2, r2, 5
    2ac2:	b340      	st.w      	r2, (r3, 0)
}
    2ac4:	783c      	rts

00002ac6 <CTC_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CTC_Int_Disable(void)
{
    INTC_ICER_WRITE(TC3_INT);    
    2ac6:	116d      	lrw      	r3, 0x20000064	// 2b78 <CTC_stop+0x20>
    2ac8:	32c0      	movi      	r2, 192
    2aca:	9360      	ld.w      	r3, (r3, 0)
    2acc:	4241      	lsli      	r2, r2, 1
    2ace:	60c8      	addu      	r3, r2
    2ad0:	3280      	movi      	r2, 128
    2ad2:	4245      	lsli      	r2, r2, 5
    2ad4:	b340      	st.w      	r2, (r3, 0)
}
    2ad6:	783c      	rts

00002ad8 <CTC_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CTC_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(TC3_INT);    
    2ad8:	1168      	lrw      	r3, 0x20000064	// 2b78 <CTC_stop+0x20>
    2ada:	3280      	movi      	r2, 128
    2adc:	9360      	ld.w      	r3, (r3, 0)
    2ade:	23ff      	addi      	r3, 256
    2ae0:	4245      	lsli      	r2, r2, 5
    2ae2:	b350      	st.w      	r2, (r3, 0x40)
}
    2ae4:	783c      	rts

00002ae6 <CTC_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CTC_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(TC3_INT);    
    2ae6:	1165      	lrw      	r3, 0x20000064	// 2b78 <CTC_stop+0x20>
    2ae8:	32e0      	movi      	r2, 224
    2aea:	9360      	ld.w      	r3, (r3, 0)
    2aec:	4241      	lsli      	r2, r2, 1
    2aee:	60c8      	addu      	r3, r2
    2af0:	3280      	movi      	r2, 128
    2af2:	4245      	lsli      	r2, r2, 5
    2af4:	b340      	st.w      	r2, (r3, 0)
}
    2af6:	783c      	rts

00002af8 <CTC_INT_CMD>:
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void CTC_INT_CMD(CTC_INT_TypeDef CTC_INT_X , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
    2af8:	3940      	cmpnei      	r1, 0
    2afa:	107f      	lrw      	r3, 0x20000020	// 2b74 <CTC_stop+0x1c>
    2afc:	0c06      	bf      	0x2b08	// 2b08 <CTC_INT_CMD+0x10>
	{
		CTC->IMCR |=CTC_INT_X;					//SET
    2afe:	9340      	ld.w      	r2, (r3, 0)
    2b00:	9267      	ld.w      	r3, (r2, 0x1c)
    2b02:	6c0c      	or      	r0, r3
    2b04:	b207      	st.w      	r0, (r2, 0x1c)
	}
	else
	{
		CTC->IMCR &=(~CTC_INT_X);				//CLR
	}
}
    2b06:	783c      	rts
		CTC->IMCR &=(~CTC_INT_X);				//CLR
    2b08:	9360      	ld.w      	r3, (r3, 0)
    2b0a:	9347      	ld.w      	r2, (r3, 0x1c)
    2b0c:	6c02      	nor      	r0, r0
    2b0e:	6808      	and      	r0, r2
    2b10:	b307      	st.w      	r0, (r3, 0x1c)
}
    2b12:	07fa      	br      	0x2b06	// 2b06 <CTC_INT_CMD+0xe>

00002b14 <CTC_Config>:
//CTC_Count_Mode_set_X:CTC_Count_Mode_set_Normal,CTC_Count_Mode_set_Period
//ReturnValue:NONE
/*************************************************************/
void CTC_Config(CTC_CLK_Source_set_TypeDef CTC_CLK_Source_set_X , CTC_BUZZ_Freq_TypeDef CTC_BUZZ_Freq_X ,
			CTC_Count_Period_TypeDef CTC_Count_Period_X )
{
    2b14:	14c2      	push      	r4-r5
	if(CTC_CLK_Source_set_X==CTC_CLK_Source_set_EMOSC)
    2b16:	3840      	cmpnei      	r0, 0
    2b18:	1077      	lrw      	r3, 0x20000020	// 2b74 <CTC_stop+0x1c>
    2b1a:	0809      	bt      	0x2b2c	// 2b2c <CTC_Config+0x18>
	{
		CTC->CSSR&=0XFFFFFFFE;									//选择外部晶振32.768K
    2b1c:	9380      	ld.w      	r4, (r3, 0)
    2b1e:	9401      	ld.w      	r0, (r4, 0x4)
    2b20:	3880      	bclri      	r0, r0, 0
    2b22:	b401      	st.w      	r0, (r4, 0x4)
	}
	else if(CTC_CLK_Source_set_X==CTC_CLK_Source_set_ISOSC)
	{
		CTC->CSSR|=0x01;										//选择内部副频
	}
	CTC->CR=CTC_Count_Period_X|CTC_BUZZ_Freq_X;
    2b24:	9360      	ld.w      	r3, (r3, 0)
    2b26:	6c84      	or      	r2, r1
    2b28:	b344      	st.w      	r2, (r3, 0x10)
}
    2b2a:	1482      	pop      	r4-r5
	else if(CTC_CLK_Source_set_X==CTC_CLK_Source_set_ISOSC)
    2b2c:	3841      	cmpnei      	r0, 1
    2b2e:	0bfb      	bt      	0x2b24	// 2b24 <CTC_Config+0x10>
		CTC->CSSR|=0x01;										//选择内部副频
    2b30:	93a0      	ld.w      	r5, (r3, 0)
    2b32:	9581      	ld.w      	r4, (r5, 0x4)
    2b34:	6c10      	or      	r0, r4
    2b36:	b501      	st.w      	r0, (r5, 0x4)
    2b38:	07f6      	br      	0x2b24	// 2b24 <CTC_Config+0x10>

00002b3a <CTC_SoftReset>:
//EntryParameter:
//ReturnValue:none
/*************************************************************/
void CTC_SoftReset(void)
{
	CTC->SRR=0X01;
    2b3a:	106f      	lrw      	r3, 0x20000020	// 2b74 <CTC_stop+0x1c>
    2b3c:	3201      	movi      	r2, 1
    2b3e:	9360      	ld.w      	r3, (r3, 0)
    2b40:	b343      	st.w      	r2, (r3, 0xc)
} 
    2b42:	783c      	rts

00002b44 <CTC_Start>:
//CTC start 
//EntryParameter:
//ReturnValue:none
/*************************************************************/ 
void CTC_Start(void)
{
    2b44:	14d0      	push      	r15
	delay_nms(100);
    2b46:	3064      	movi      	r0, 100
    2b48:	e0000b7e 	bsr      	0x4244	// 4244 <delay_nms>
	CTC->CR|=0X01;
    2b4c:	106a      	lrw      	r3, 0x20000020	// 2b74 <CTC_stop+0x1c>
    2b4e:	9340      	ld.w      	r2, (r3, 0)
    2b50:	9264      	ld.w      	r3, (r2, 0x10)
    2b52:	3ba0      	bseti      	r3, r3, 0
    2b54:	b264      	st.w      	r3, (r2, 0x10)
}
    2b56:	1490      	pop      	r15

00002b58 <CTC_stop>:
//CTC stop 
//EntryParameter:
//ReturnValue:none
/*************************************************************/ 
void CTC_stop(void)
{
    2b58:	14d0      	push      	r15
	delay_nms(100);
    2b5a:	3064      	movi      	r0, 100
    2b5c:	e0000b74 	bsr      	0x4244	// 4244 <delay_nms>
	CTC->CR&=0Xfffffffe;
    2b60:	1065      	lrw      	r3, 0x20000020	// 2b74 <CTC_stop+0x1c>
    2b62:	9340      	ld.w      	r2, (r3, 0)
    2b64:	9264      	ld.w      	r3, (r2, 0x10)
    2b66:	3b80      	bclri      	r3, r3, 0
    2b68:	b264      	st.w      	r3, (r2, 0x10)
}
    2b6a:	1490      	pop      	r15
    2b6c:	20000040 	.long	0x20000040
    2b70:	20000044 	.long	0x20000044
    2b74:	20000020 	.long	0x20000020
    2b78:	20000064 	.long	0x20000064

00002b7c <CORET_DeInit>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/    
void CORET_DeInit(void)
{
	CK801->CORET_CSR=CORET_CSR_RST;
    2b7c:	1064      	lrw      	r3, 0x20000064	// 2b8c <CORET_DeInit+0x10>
    2b7e:	3204      	movi      	r2, 4
    2b80:	9360      	ld.w      	r3, (r3, 0)
    2b82:	b344      	st.w      	r2, (r3, 0x10)
	CK801->CORET_RVR=CORET_RVR_RST;
    2b84:	3200      	movi      	r2, 0
    2b86:	b345      	st.w      	r2, (r3, 0x14)
	CK801->CORET_CVR=CORET_CVR_RST;
    2b88:	b346      	st.w      	r2, (r3, 0x18)
}
    2b8a:	783c      	rts
    2b8c:	20000064 	.long	0x20000064

00002b90 <CORET_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_Int_Enable(void)
{
    CK801->CORET_CVR = 0x0;							// Clear counter and flag
    2b90:	1164      	lrw      	r3, 0x20000064	// 2c20 <CORET_reload+0xc>
    2b92:	3200      	movi      	r2, 0
    2b94:	9360      	ld.w      	r3, (r3, 0)
    2b96:	b346      	st.w      	r2, (r3, 0x18)
	INTC_ISER_WRITE(CORET_INT);    
    2b98:	23ff      	addi      	r3, 256
    2b9a:	3201      	movi      	r2, 1
    2b9c:	b340      	st.w      	r2, (r3, 0)
}
    2b9e:	783c      	rts

00002ba0 <CORET_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_Int_Disable(void)
{
    INTC_ICER_WRITE(CORET_INT);    
    2ba0:	1160      	lrw      	r3, 0x20000064	// 2c20 <CORET_reload+0xc>
    2ba2:	32c0      	movi      	r2, 192
    2ba4:	9360      	ld.w      	r3, (r3, 0)
    2ba6:	4241      	lsli      	r2, r2, 1
    2ba8:	60c8      	addu      	r3, r2
    2baa:	3201      	movi      	r2, 1
    2bac:	b340      	st.w      	r2, (r3, 0)
}
    2bae:	783c      	rts

00002bb0 <CORET_WakeUp_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void  CORET_WakeUp_Enable(void)
{
    INTC_IWER_WRITE(CORET_INT);    
    2bb0:	107c      	lrw      	r3, 0x20000064	// 2c20 <CORET_reload+0xc>
    2bb2:	3201      	movi      	r2, 1
    2bb4:	9360      	ld.w      	r3, (r3, 0)
    2bb6:	23ff      	addi      	r3, 256
    2bb8:	b350      	st.w      	r2, (r3, 0x40)
}
    2bba:	783c      	rts

00002bbc <CORET_WakeUp_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void  CORET_WakeUp_Disable(void)
{
    INTC_IWDR_WRITE(CORET_INT);    
    2bbc:	1079      	lrw      	r3, 0x20000064	// 2c20 <CORET_reload+0xc>
    2bbe:	32e0      	movi      	r2, 224
    2bc0:	9360      	ld.w      	r3, (r3, 0)
    2bc2:	4241      	lsli      	r2, r2, 1
    2bc4:	60c8      	addu      	r3, r2
    2bc6:	3201      	movi      	r2, 1
    2bc8:	b340      	st.w      	r2, (r3, 0)
}
    2bca:	783c      	rts

00002bcc <CORET_start>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_start(void)
{
	CK801->CORET_CSR|=0x01;
    2bcc:	1075      	lrw      	r3, 0x20000064	// 2c20 <CORET_reload+0xc>
    2bce:	9340      	ld.w      	r2, (r3, 0)
    2bd0:	9264      	ld.w      	r3, (r2, 0x10)
    2bd2:	3ba0      	bseti      	r3, r3, 0
    2bd4:	b264      	st.w      	r3, (r2, 0x10)
}
    2bd6:	783c      	rts

00002bd8 <CORET_stop>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_stop(void)
{
	CK801->CORET_CSR&=0Xfffffffe;
    2bd8:	1072      	lrw      	r3, 0x20000064	// 2c20 <CORET_reload+0xc>
    2bda:	9340      	ld.w      	r2, (r3, 0)
    2bdc:	9264      	ld.w      	r3, (r2, 0x10)
    2bde:	3b80      	bclri      	r3, r3, 0
    2be0:	b264      	st.w      	r3, (r2, 0x10)
}
    2be2:	783c      	rts

00002be4 <CORET_CLKSOURCE_EX>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_CLKSOURCE_EX(void)
{
	CK801->CORET_CSR&=0Xfffffffb;
    2be4:	106f      	lrw      	r3, 0x20000064	// 2c20 <CORET_reload+0xc>
    2be6:	9340      	ld.w      	r2, (r3, 0)
    2be8:	9264      	ld.w      	r3, (r2, 0x10)
    2bea:	3b82      	bclri      	r3, r3, 2
    2bec:	b264      	st.w      	r3, (r2, 0x10)
}
    2bee:	783c      	rts

00002bf0 <CORET_CLKSOURCE_IN>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_CLKSOURCE_IN(void)
{
	CK801->CORET_CSR|=0x04;
    2bf0:	106c      	lrw      	r3, 0x20000064	// 2c20 <CORET_reload+0xc>
    2bf2:	9340      	ld.w      	r2, (r3, 0)
    2bf4:	9264      	ld.w      	r3, (r2, 0x10)
    2bf6:	3ba2      	bseti      	r3, r3, 2
    2bf8:	b264      	st.w      	r3, (r2, 0x10)
}
    2bfa:	783c      	rts

00002bfc <CORET_TICKINT_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_TICKINT_Enable(void)
{
    CK801->CORET_CSR|=0x02;
    2bfc:	1069      	lrw      	r3, 0x20000064	// 2c20 <CORET_reload+0xc>
    2bfe:	9340      	ld.w      	r2, (r3, 0)
    2c00:	9264      	ld.w      	r3, (r2, 0x10)
    2c02:	3ba1      	bseti      	r3, r3, 1
    2c04:	b264      	st.w      	r3, (r2, 0x10)
}
    2c06:	783c      	rts

00002c08 <CORET_TICKINT_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_TICKINT_Disable(void)
{
   CK801->CORET_CSR&=0Xfffffffd;
    2c08:	1066      	lrw      	r3, 0x20000064	// 2c20 <CORET_reload+0xc>
    2c0a:	9340      	ld.w      	r2, (r3, 0)
    2c0c:	9264      	ld.w      	r3, (r2, 0x10)
    2c0e:	3b81      	bclri      	r3, r3, 1
    2c10:	b264      	st.w      	r3, (r2, 0x10)
}
    2c12:	783c      	rts

00002c14 <CORET_reload>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_reload(void)
{
	CK801->CORET_CVR = 0x0;							// Clear counter and flag
    2c14:	1063      	lrw      	r3, 0x20000064	// 2c20 <CORET_reload+0xc>
    2c16:	3200      	movi      	r2, 0
    2c18:	9360      	ld.w      	r3, (r3, 0)
    2c1a:	b346      	st.w      	r2, (r3, 0x18)
}
    2c1c:	783c      	rts
    2c1e:	0000      	bkpt
    2c20:	20000064 	.long	0x20000064

00002c24 <GPIO_DeInit>:
//IO RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void GPIO_DeInit(void)
{
    2c24:	14c2      	push      	r4-r5
    GPIOA0->CONLR = GPIO_RESET_VALUE;                     
    2c26:	116b      	lrw      	r3, 0x20000050	// 2cd0 <GPIO_DeInit+0xac>
    GPIOA1->CONHR = GPIO_RESET_VALUE;
    GPIOB0->CONLR = GPIO_RESET_VALUE;                     
    GPIOB0->CONHR = GPIO_RESET_VALUE;
	GPIOC0->CONLR = GPIO_RESET_VALUE;                     
    GPIOC0->CONHR = GPIO_RESET_VALUE;
	GPIOD0->CONLR = GPIO_RESET_VALUE;                     
    2c28:	3500      	movi      	r5, 0
    GPIOA0->CONLR = GPIO_RESET_VALUE;                     
    2c2a:	9380      	ld.w      	r4, (r3, 0)
    2c2c:	3300      	movi      	r3, 0
    2c2e:	b460      	st.w      	r3, (r4, 0)
    GPIOA0->CONHR = GPIO_RESET_VALUE;
    2c30:	b461      	st.w      	r3, (r4, 0x4)
	GPIOA1->CONLR = GPIO_RESET_VALUE;                     
    2c32:	1169      	lrw      	r3, 0x2000004c	// 2cd4 <GPIO_DeInit+0xb0>
    2c34:	9300      	ld.w      	r0, (r3, 0)
    2c36:	3300      	movi      	r3, 0
    2c38:	b060      	st.w      	r3, (r0, 0)
    GPIOA1->CONHR = GPIO_RESET_VALUE;
    2c3a:	b061      	st.w      	r3, (r0, 0x4)
    GPIOB0->CONLR = GPIO_RESET_VALUE;                     
    2c3c:	1167      	lrw      	r3, 0x20000048	// 2cd8 <GPIO_DeInit+0xb4>
    2c3e:	9320      	ld.w      	r1, (r3, 0)
    2c40:	3300      	movi      	r3, 0
    2c42:	b160      	st.w      	r3, (r1, 0)
    GPIOB0->CONHR = GPIO_RESET_VALUE;
    2c44:	b161      	st.w      	r3, (r1, 0x4)
	GPIOC0->CONLR = GPIO_RESET_VALUE;                     
    2c46:	1166      	lrw      	r3, 0x20000044	// 2cdc <GPIO_DeInit+0xb8>
    2c48:	9340      	ld.w      	r2, (r3, 0)
    2c4a:	3300      	movi      	r3, 0
    2c4c:	b260      	st.w      	r3, (r2, 0)
    GPIOC0->CONHR = GPIO_RESET_VALUE;
    2c4e:	b261      	st.w      	r3, (r2, 0x4)
	GPIOD0->CONLR = GPIO_RESET_VALUE;                     
    2c50:	1164      	lrw      	r3, 0x20000040	// 2ce0 <GPIO_DeInit+0xbc>
    2c52:	9360      	ld.w      	r3, (r3, 0)
    2c54:	b3a0      	st.w      	r5, (r3, 0)
    GPIOD0->CONHR = GPIO_RESET_VALUE;
    2c56:	b3a1      	st.w      	r5, (r3, 0x4)
    GPIOA0->WODR  = GPIO_RESET_VALUE; 
    2c58:	b4a2      	st.w      	r5, (r4, 0x8)
	GPIOA1->WODR  = GPIO_RESET_VALUE; 
    2c5a:	b0a2      	st.w      	r5, (r0, 0x8)
    GPIOB0->WODR  = GPIO_RESET_VALUE;
    2c5c:	b1a2      	st.w      	r5, (r1, 0x8)
	GPIOC0->WODR  = GPIO_RESET_VALUE;
    2c5e:	b2a2      	st.w      	r5, (r2, 0x8)
	GPIOD0->WODR  = GPIO_RESET_VALUE;
    2c60:	b3a2      	st.w      	r5, (r3, 0x8)
    GPIOA0->SODR  = GPIO_RESET_VALUE; 
    2c62:	b4a3      	st.w      	r5, (r4, 0xc)
	GPIOA1->SODR  = GPIO_RESET_VALUE; 
    2c64:	b0a3      	st.w      	r5, (r0, 0xc)
    GPIOB0->SODR  = GPIO_RESET_VALUE;
    2c66:	b1a3      	st.w      	r5, (r1, 0xc)
	GPIOC0->SODR  = GPIO_RESET_VALUE; 
    2c68:	b2a3      	st.w      	r5, (r2, 0xc)
	GPIOD0->SODR  = GPIO_RESET_VALUE; 
    2c6a:	b3a3      	st.w      	r5, (r3, 0xc)
    GPIOA0->CODR  = GPIO_RESET_VALUE; 
    2c6c:	b4a4      	st.w      	r5, (r4, 0x10)
	GPIOA1->CODR  = GPIO_RESET_VALUE; 
    2c6e:	b0a4      	st.w      	r5, (r0, 0x10)
    GPIOB0->CODR  = GPIO_RESET_VALUE;
    2c70:	b1a4      	st.w      	r5, (r1, 0x10)
	GPIOC0->CODR  = GPIO_RESET_VALUE;
    2c72:	b2a4      	st.w      	r5, (r2, 0x10)
	GPIOD0->CODR  = GPIO_RESET_VALUE;
    2c74:	b3a4      	st.w      	r5, (r3, 0x10)
    GPIOA0->PUDR  = GPIO_RESET_VALUE; 
    2c76:	b4a8      	st.w      	r5, (r4, 0x20)
	GPIOA1->PUDR  = GPIO_RESET_VALUE; 
    2c78:	b0a8      	st.w      	r5, (r0, 0x20)
    GPIOB0->PUDR  = GPIO_RESET_VALUE;
    2c7a:	b1a8      	st.w      	r5, (r1, 0x20)
	GPIOC0->PUDR  = GPIO_RESET_VALUE;
    2c7c:	b2a8      	st.w      	r5, (r2, 0x20)
	GPIOD0->PUDR  = GPIO_RESET_VALUE;
    2c7e:	b3a8      	st.w      	r5, (r3, 0x20)
    GPIOA0->DSCR  = GPIO_RESET_VALUE;
    2c80:	b4a9      	st.w      	r5, (r4, 0x24)
	GPIOA1->DSCR  = GPIO_RESET_VALUE;
    2c82:	b0a9      	st.w      	r5, (r0, 0x24)
    GPIOB0->DSCR  = GPIO_RESET_VALUE;
    2c84:	b1a9      	st.w      	r5, (r1, 0x24)
	GPIOC0->DSCR  = GPIO_RESET_VALUE;
    2c86:	b2a9      	st.w      	r5, (r2, 0x24)
	GPIOD0->DSCR  = GPIO_RESET_VALUE;
    2c88:	b3a9      	st.w      	r5, (r3, 0x24)
    GPIOA0->IECR  = GPIO_RESET_VALUE;
    2c8a:	b4ab      	st.w      	r5, (r4, 0x2c)
	GPIOA1->IECR  = GPIO_RESET_VALUE;
    2c8c:	b0ab      	st.w      	r5, (r0, 0x2c)
    GPIOB0->IECR  = GPIO_RESET_VALUE;
    2c8e:	b1ab      	st.w      	r5, (r1, 0x2c)
	GPIOC0->IECR  = GPIO_RESET_VALUE;
    2c90:	b2ab      	st.w      	r5, (r2, 0x2c)
	GPIOD0->IECR  = GPIO_RESET_VALUE;
    2c92:	b3ab      	st.w      	r5, (r3, 0x2c)
	GPIOA0->IEER  = GPIO_RESET_VALUE;
    2c94:	b4ac      	st.w      	r5, (r4, 0x30)
	GPIOA1->IEER  = GPIO_RESET_VALUE;
    2c96:	b0ac      	st.w      	r5, (r0, 0x30)
    GPIOB0->IEER  = GPIO_RESET_VALUE;
    2c98:	b1ac      	st.w      	r5, (r1, 0x30)
	GPIOC0->IEER  = GPIO_RESET_VALUE;
    2c9a:	b2ac      	st.w      	r5, (r2, 0x30)
	GPIOD0->IEER  = GPIO_RESET_VALUE;
    2c9c:	b3ac      	st.w      	r5, (r3, 0x30)
	GPIOA0->IEDR  = GPIO_RESET_VALUE;
    2c9e:	b4ad      	st.w      	r5, (r4, 0x34)
	GPIOA1->IEDR  = GPIO_RESET_VALUE;
    2ca0:	b0ad      	st.w      	r5, (r0, 0x34)
    GPIOB0->IEDR  = GPIO_RESET_VALUE;
    2ca2:	b1ad      	st.w      	r5, (r1, 0x34)
	GPIOC0->IEDR  = GPIO_RESET_VALUE;
    2ca4:	b2ad      	st.w      	r5, (r2, 0x34)
	GPIOD0->IEDR  = GPIO_RESET_VALUE;
    2ca6:	b3ad      	st.w      	r5, (r3, 0x34)
    GPIOA0->ODSR  = GPIO_RESET_VALUE;
    2ca8:	b4a5      	st.w      	r5, (r4, 0x14)
	GPIOA1->ODSR  = GPIO_RESET_VALUE;
    2caa:	b0a5      	st.w      	r5, (r0, 0x14)
    GPIOB0->ODSR  = GPIO_RESET_VALUE;
    2cac:	b1a5      	st.w      	r5, (r1, 0x14)
	GPIOC0->ODSR  = GPIO_RESET_VALUE;
    2cae:	b2a5      	st.w      	r5, (r2, 0x14)
	GPIOD0->ODSR  = GPIO_RESET_VALUE;
    2cb0:	b3a5      	st.w      	r5, (r3, 0x14)
    GPIOA0->OMCR  = GPIO_RESET_VALUE;
    2cb2:	b4aa      	st.w      	r5, (r4, 0x28)
	GPIOA1->OMCR  = GPIO_RESET_VALUE;
    2cb4:	3400      	movi      	r4, 0
    2cb6:	b08a      	st.w      	r4, (r0, 0x28)
    GPIOB0->OMCR  = GPIO_RESET_VALUE;
    2cb8:	3000      	movi      	r0, 0
    2cba:	b10a      	st.w      	r0, (r1, 0x28)
	GPIOC0->OMCR  = GPIO_RESET_VALUE;
    2cbc:	3100      	movi      	r1, 0
    2cbe:	b22a      	st.w      	r1, (r2, 0x28)
	GPIOD0->OMCR  = GPIO_RESET_VALUE;
    2cc0:	3200      	movi      	r2, 0
    2cc2:	b34a      	st.w      	r2, (r3, 0x28)
    EXIGRP->IGRPL = GPIO_RESET_VALUE;
    2cc4:	1068      	lrw      	r3, 0x2000003c	// 2ce4 <GPIO_DeInit+0xc0>
    2cc6:	9360      	ld.w      	r3, (r3, 0)
    2cc8:	b340      	st.w      	r2, (r3, 0)
	EXIGRP->IGRPH = GPIO_RESET_VALUE;
    2cca:	b341      	st.w      	r2, (r3, 0x4)
}  
    2ccc:	1482      	pop      	r4-r5
    2cce:	0000      	bkpt
    2cd0:	20000050 	.long	0x20000050
    2cd4:	2000004c 	.long	0x2000004c
    2cd8:	20000048 	.long	0x20000048
    2cdc:	20000044 	.long	0x20000044
    2ce0:	20000040 	.long	0x20000040
    2ce4:	2000003c 	.long	0x2000003c

00002ce8 <GPIO_Debug_IO_03_04>:
void GPIO_Debug_IO_03_04(void)
{
    GPIOA0->CONLR |= 0x00055000;
    2ce8:	1364      	lrw      	r3, 0x20000050	// 2e78 <GPIO_DriveStrength_DIS+0x4>
    2cea:	32aa      	movi      	r2, 170
    2cec:	9320      	ld.w      	r1, (r3, 0)
    2cee:	9160      	ld.w      	r3, (r1, 0)
    2cf0:	424b      	lsli      	r2, r2, 11
    2cf2:	6cc8      	or      	r3, r2
    2cf4:	b160      	st.w      	r3, (r1, 0)
}
    2cf6:	783c      	rts

00002cf8 <GPIO_Init>:
//byte:Lowbyte(PIN_0~7),Highbyte(PIN_8~15)
//Dir:0:output 1:input
//ReturnValue:NONE
/*************************************************************/  
void GPIO_Init(CSP_GPIO_T *GPIOx,U8_T PinNum,GPIO_Dir_TypeDef Dir)
{
    2cf8:	14d1      	push      	r4, r15
    uint32_t data_temp;
    uint8_t GPIO_Pin;
    if(PinNum<8)
    2cfa:	3907      	cmphsi      	r1, 8
{
    2cfc:	6d03      	mov      	r4, r0
    if(PinNum<8)
    2cfe:	0830      	bt      	0x2d5e	// 2d5e <GPIO_Init+0x66>
    {
    switch (PinNum)
    2d00:	5903      	subi      	r0, r1, 1
    2d02:	3806      	cmphsi      	r0, 7
    2d04:	0827      	bt      	0x2d52	// 2d52 <GPIO_Init+0x5a>
    2d06:	e00012cd 	bsr      	0x52a0	// 52a0 <___gnu_csky_case_uqi>
    2d0a:	1004      	.short	0x1004
    2d0c:	1d1a1613 	.long	0x1d1a1613
    2d10:	0021      	.short	0x0021
    {
        case 0:data_temp=0xfffffff0;GPIO_Pin=0;break;
        case 1:data_temp=0xffffff0f;GPIO_Pin=4;break;
    2d12:	3300      	movi      	r3, 0
    2d14:	3104      	movi      	r1, 4
    2d16:	2bf0      	subi      	r3, 241
        case 4:data_temp=0xfff0ffff;GPIO_Pin=16;break;
        case 5:data_temp=0xff0fffff;GPIO_Pin=20;break;
        case 6:data_temp=0xf0ffffff;GPIO_Pin=24;break;
        case 7:data_temp=0x0fffffff;GPIO_Pin=28;break;
    }
        if (Dir)
    2d18:	3a40      	cmpnei      	r2, 0
        {
          (GPIOx)->CONLR =((GPIOx)->CONLR & data_temp) | 1<<GPIO_Pin;
    2d1a:	9440      	ld.w      	r2, (r4, 0)
    2d1c:	68c8      	and      	r3, r2
        if (Dir)
    2d1e:	0c1e      	bf      	0x2d5a	// 2d5a <GPIO_Init+0x62>
          (GPIOx)->CONLR =((GPIOx)->CONLR & data_temp) | 1<<GPIO_Pin;
    2d20:	3201      	movi      	r2, 1
        }
        else
        {
         (GPIOx)->CONLR = ((GPIOx)->CONLR & data_temp) | 2<<GPIO_Pin; 
    2d22:	7084      	lsl      	r2, r1
    2d24:	6cc8      	or      	r3, r2
    2d26:	b460      	st.w      	r3, (r4, 0)
        else
        {
         (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 2<<GPIO_Pin;    
        }
    }
}
    2d28:	1491      	pop      	r4, r15
        case 2:data_temp=0xfffff0ff;GPIO_Pin=8;break;
    2d2a:	3108      	movi      	r1, 8
    2d2c:	1274      	lrw      	r3, 0xfffff0ff	// 2e7c <GPIO_DriveStrength_DIS+0x8>
    2d2e:	07f5      	br      	0x2d18	// 2d18 <GPIO_Init+0x20>
        case 3:data_temp=0xffff0fff;GPIO_Pin=12;break;
    2d30:	310c      	movi      	r1, 12
    2d32:	1274      	lrw      	r3, 0xffff0fff	// 2e80 <GPIO_DriveStrength_DIS+0xc>
    2d34:	07f2      	br      	0x2d18	// 2d18 <GPIO_Init+0x20>
        case 4:data_temp=0xfff0ffff;GPIO_Pin=16;break;
    2d36:	3110      	movi      	r1, 16
    2d38:	1273      	lrw      	r3, 0xfff10000	// 2e84 <GPIO_DriveStrength_DIS+0x10>
        case 6:data_temp=0xf0ffffff;GPIO_Pin=24;break;
    2d3a:	2b00      	subi      	r3, 1
    2d3c:	07ee      	br      	0x2d18	// 2d18 <GPIO_Init+0x20>
        case 5:data_temp=0xff0fffff;GPIO_Pin=20;break;
    2d3e:	3114      	movi      	r1, 20
    2d40:	1272      	lrw      	r3, 0xff100000	// 2e88 <GPIO_DriveStrength_DIS+0x14>
    2d42:	07fc      	br      	0x2d3a	// 2d3a <GPIO_Init+0x42>
        case 6:data_temp=0xf0ffffff;GPIO_Pin=24;break;
    2d44:	33f1      	movi      	r3, 241
    2d46:	3118      	movi      	r1, 24
    2d48:	4378      	lsli      	r3, r3, 24
    2d4a:	07f8      	br      	0x2d3a	// 2d3a <GPIO_Init+0x42>
        case 7:data_temp=0x0fffffff;GPIO_Pin=28;break;
    2d4c:	311c      	movi      	r1, 28
    2d4e:	1270      	lrw      	r3, 0xfffffff	// 2e8c <GPIO_DriveStrength_DIS+0x18>
    2d50:	07e4      	br      	0x2d18	// 2d18 <GPIO_Init+0x20>
        case 0:data_temp=0xfffffff0;GPIO_Pin=0;break;
    2d52:	3300      	movi      	r3, 0
    2d54:	3100      	movi      	r1, 0
    2d56:	2b0f      	subi      	r3, 16
    2d58:	07e0      	br      	0x2d18	// 2d18 <GPIO_Init+0x20>
         (GPIOx)->CONLR = ((GPIOx)->CONLR & data_temp) | 2<<GPIO_Pin; 
    2d5a:	3202      	movi      	r2, 2
    2d5c:	07e3      	br      	0x2d22	// 2d22 <GPIO_Init+0x2a>
    else if (PinNum<16)
    2d5e:	390f      	cmphsi      	r1, 16
    2d60:	0be4      	bt      	0x2d28	// 2d28 <GPIO_Init+0x30>
        switch (PinNum)
    2d62:	2908      	subi      	r1, 9
    2d64:	3906      	cmphsi      	r1, 7
    2d66:	6c07      	mov      	r0, r1
    2d68:	0827      	bt      	0x2db6	// 2db6 <GPIO_Init+0xbe>
    2d6a:	e000129b 	bsr      	0x52a0	// 52a0 <___gnu_csky_case_uqi>
    2d6e:	1004      	.short	0x1004
    2d70:	1d1a1613 	.long	0x1d1a1613
    2d74:	0021      	.short	0x0021
        case 9:data_temp=0xffffff0f;GPIO_Pin=4;break;
    2d76:	3300      	movi      	r3, 0
    2d78:	3104      	movi      	r1, 4
    2d7a:	2bf0      	subi      	r3, 241
      if (Dir)
    2d7c:	3a40      	cmpnei      	r2, 0
        (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 1<<GPIO_Pin;  
    2d7e:	9441      	ld.w      	r2, (r4, 0x4)
    2d80:	68c8      	and      	r3, r2
      if (Dir)
    2d82:	0c1e      	bf      	0x2dbe	// 2dbe <GPIO_Init+0xc6>
        (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 1<<GPIO_Pin;  
    2d84:	3201      	movi      	r2, 1
         (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 2<<GPIO_Pin;    
    2d86:	7084      	lsl      	r2, r1
    2d88:	6cc8      	or      	r3, r2
    2d8a:	b461      	st.w      	r3, (r4, 0x4)
}
    2d8c:	07ce      	br      	0x2d28	// 2d28 <GPIO_Init+0x30>
        case 10:data_temp=0xfffff0ff;GPIO_Pin=8;break;
    2d8e:	3108      	movi      	r1, 8
    2d90:	117b      	lrw      	r3, 0xfffff0ff	// 2e7c <GPIO_DriveStrength_DIS+0x8>
    2d92:	07f5      	br      	0x2d7c	// 2d7c <GPIO_Init+0x84>
        case 11:data_temp=0xffff0fff;GPIO_Pin=12;break;
    2d94:	310c      	movi      	r1, 12
    2d96:	117b      	lrw      	r3, 0xffff0fff	// 2e80 <GPIO_DriveStrength_DIS+0xc>
    2d98:	07f2      	br      	0x2d7c	// 2d7c <GPIO_Init+0x84>
        case 12:data_temp=0xfff0ffff;GPIO_Pin=16;break;
    2d9a:	3110      	movi      	r1, 16
    2d9c:	117a      	lrw      	r3, 0xfff10000	// 2e84 <GPIO_DriveStrength_DIS+0x10>
        case 14:data_temp=0xf0ffffff;GPIO_Pin=24;break;
    2d9e:	2b00      	subi      	r3, 1
    2da0:	07ee      	br      	0x2d7c	// 2d7c <GPIO_Init+0x84>
        case 13:data_temp=0xff0fffff;GPIO_Pin=20;break;
    2da2:	3114      	movi      	r1, 20
    2da4:	1179      	lrw      	r3, 0xff100000	// 2e88 <GPIO_DriveStrength_DIS+0x14>
    2da6:	07fc      	br      	0x2d9e	// 2d9e <GPIO_Init+0xa6>
        case 14:data_temp=0xf0ffffff;GPIO_Pin=24;break;
    2da8:	33f1      	movi      	r3, 241
    2daa:	3118      	movi      	r1, 24
    2dac:	4378      	lsli      	r3, r3, 24
    2dae:	07f8      	br      	0x2d9e	// 2d9e <GPIO_Init+0xa6>
        case 15:data_temp=0x0fffffff;GPIO_Pin=28;break;
    2db0:	311c      	movi      	r1, 28
    2db2:	1177      	lrw      	r3, 0xfffffff	// 2e8c <GPIO_DriveStrength_DIS+0x18>
    2db4:	07e4      	br      	0x2d7c	// 2d7c <GPIO_Init+0x84>
        case 8:data_temp=0xfffffff0;GPIO_Pin=0;break;
    2db6:	3300      	movi      	r3, 0
    2db8:	3100      	movi      	r1, 0
    2dba:	2b0f      	subi      	r3, 16
    2dbc:	07e0      	br      	0x2d7c	// 2d7c <GPIO_Init+0x84>
         (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 2<<GPIO_Pin;    
    2dbe:	3202      	movi      	r2, 2
    2dc0:	07e3      	br      	0x2d86	// 2d86 <GPIO_Init+0x8e>

00002dc2 <GPIO_Init2>:
//val=0x22222222 all IO as output
//ReturnValue:NONE
/*************************************************************/  
void GPIO_Init2(CSP_GPIO_T *GPIOx,GPIO_byte_TypeDef byte,uint32_t val)
{
    if (byte==0)
    2dc2:	3940      	cmpnei      	r1, 0
    2dc4:	0803      	bt      	0x2dca	// 2dca <GPIO_Init2+0x8>
    {
        (GPIOx)->CONLR=val;
    2dc6:	b040      	st.w      	r2, (r0, 0)
    }
    else if(byte==1)
    {
        (GPIOx)->CONHR=val;
    }
}
    2dc8:	783c      	rts
    else if(byte==1)
    2dca:	3941      	cmpnei      	r1, 1
    2dcc:	0bfe      	bt      	0x2dc8	// 2dc8 <GPIO_Init2+0x6>
        (GPIOx)->CONHR=val;
    2dce:	b041      	st.w      	r2, (r0, 0x4)
}
    2dd0:	07fc      	br      	0x2dc8	// 2dc8 <GPIO_Init2+0x6>

00002dd2 <GPIO_MODE_Init>:
//IO_MODE:IECR(IO INT ENABLE)
//IO_MODE:IGRP(IO INT GROUP)
//ReturnValue:NONE
/*************************************************************/  
void GPIO_MODE_Init(CSP_GPIO_T *GPIOx,GPIO_Mode_TypeDef IO_MODE,uint32_t val)
{
    2dd2:	14d0      	push      	r15
        switch (IO_MODE)
    2dd4:	3907      	cmphsi      	r1, 8
{
    2dd6:	6cc3      	mov      	r3, r0
        switch (IO_MODE)
    2dd8:	0809      	bt      	0x2dea	// 2dea <GPIO_MODE_Init+0x18>
    2dda:	6c07      	mov      	r0, r1
    2ddc:	e0001262 	bsr      	0x52a0	// 52a0 <___gnu_csky_case_uqi>
    2de0:	0a080604 	.long	0x0a080604
    2de4:	14100e0c 	.long	0x14100e0c
        {
            case 0:(GPIOx)->PUDR  = val;break;               
    2de8:	b348      	st.w      	r2, (r3, 0x20)
			case 4:(GPIOx)->IEER  = val;break;
			case 5:(GPIOx)->IEDR  = val;break;
            case 6:EXIGRP->IGRPL  = val;break;
			case 7:EXIGRP->IGRPH  = val;break;
        }
}
    2dea:	1490      	pop      	r15
            case 1:(GPIOx)->DSCR  = val;break;
    2dec:	b349      	st.w      	r2, (r3, 0x24)
    2dee:	07fe      	br      	0x2dea	// 2dea <GPIO_MODE_Init+0x18>
            case 2:(GPIOx)->OMCR  = val;break;
    2df0:	b34a      	st.w      	r2, (r3, 0x28)
    2df2:	07fc      	br      	0x2dea	// 2dea <GPIO_MODE_Init+0x18>
            case 3:(GPIOx)->IECR  = val;break;
    2df4:	b34b      	st.w      	r2, (r3, 0x2c)
    2df6:	07fa      	br      	0x2dea	// 2dea <GPIO_MODE_Init+0x18>
			case 4:(GPIOx)->IEER  = val;break;
    2df8:	b34c      	st.w      	r2, (r3, 0x30)
    2dfa:	07f8      	br      	0x2dea	// 2dea <GPIO_MODE_Init+0x18>
			case 5:(GPIOx)->IEDR  = val;break;
    2dfc:	b34d      	st.w      	r2, (r3, 0x34)
    2dfe:	07f6      	br      	0x2dea	// 2dea <GPIO_MODE_Init+0x18>
            case 6:EXIGRP->IGRPL  = val;break;
    2e00:	1164      	lrw      	r3, 0x2000003c	// 2e90 <GPIO_DriveStrength_DIS+0x1c>
    2e02:	9360      	ld.w      	r3, (r3, 0)
    2e04:	b340      	st.w      	r2, (r3, 0)
    2e06:	07f2      	br      	0x2dea	// 2dea <GPIO_MODE_Init+0x18>
			case 7:EXIGRP->IGRPH  = val;break;
    2e08:	1162      	lrw      	r3, 0x2000003c	// 2e90 <GPIO_DriveStrength_DIS+0x1c>
    2e0a:	9360      	ld.w      	r3, (r3, 0)
    2e0c:	b341      	st.w      	r2, (r3, 0x4)
}
    2e0e:	07ee      	br      	0x2dea	// 2dea <GPIO_MODE_Init+0x18>

00002e10 <GPIO_PullHigh_Init>:
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_PullHigh_Init(CSP_GPIO_T *GPIOx,U8_T bit)
{
	(GPIOx)->PUDR  = (((GPIOx)->PUDR) & ~(0x03<<(bit*2))) | (0x01<<(bit*2));
    2e10:	4121      	lsli      	r1, r1, 1
    2e12:	3303      	movi      	r3, 3
    2e14:	70c4      	lsl      	r3, r1
    2e16:	9048      	ld.w      	r2, (r0, 0x20)
    2e18:	6cce      	nor      	r3, r3
    2e1a:	68c8      	and      	r3, r2
    2e1c:	3201      	movi      	r2, 1
    2e1e:	7084      	lsl      	r2, r1
    2e20:	6cc8      	or      	r3, r2
    2e22:	b068      	st.w      	r3, (r0, 0x20)
}
    2e24:	783c      	rts

00002e26 <GPIO_PullLow_Init>:
void GPIO_PullLow_Init(CSP_GPIO_T *GPIOx,U8_T bit)
{
	(GPIOx)->PUDR  = (((GPIOx)->PUDR) & ~(0x03<<(bit*2))) | (0x02<<(bit*2));
    2e26:	4121      	lsli      	r1, r1, 1
    2e28:	3303      	movi      	r3, 3
    2e2a:	70c4      	lsl      	r3, r1
    2e2c:	9048      	ld.w      	r2, (r0, 0x20)
    2e2e:	6cce      	nor      	r3, r3
    2e30:	68c8      	and      	r3, r2
    2e32:	3202      	movi      	r2, 2
    2e34:	7084      	lsl      	r2, r1
    2e36:	6cc8      	or      	r3, r2
    2e38:	b068      	st.w      	r3, (r0, 0x20)
}
    2e3a:	783c      	rts

00002e3c <GPIO_PullHighLow_DIS>:
void GPIO_PullHighLow_DIS(CSP_GPIO_T *GPIOx,U8_T bit)
{
	(GPIOx)->PUDR  = ((GPIOx)->PUDR) & ~(0x03<<(bit*2));
    2e3c:	4121      	lsli      	r1, r1, 1
    2e3e:	3303      	movi      	r3, 3
    2e40:	70c4      	lsl      	r3, r1
    2e42:	9048      	ld.w      	r2, (r0, 0x20)
    2e44:	6cce      	nor      	r3, r3
    2e46:	68c8      	and      	r3, r2
    2e48:	b068      	st.w      	r3, (r0, 0x20)
}
    2e4a:	783c      	rts

00002e4c <GPIO_OpenDrain_EN>:
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_OpenDrain_EN(CSP_GPIO_T *GPIOx,U8_T bit)
{
	(GPIOx)->OMCR  = ((GPIOx)->OMCR) | (0x01<<bit);
    2e4c:	3301      	movi      	r3, 1
    2e4e:	904a      	ld.w      	r2, (r0, 0x28)
    2e50:	70c4      	lsl      	r3, r1
    2e52:	6cc8      	or      	r3, r2
    2e54:	b06a      	st.w      	r3, (r0, 0x28)
}
    2e56:	783c      	rts

00002e58 <GPIO_OpenDrain_DIS>:
void GPIO_OpenDrain_DIS(CSP_GPIO_T *GPIOx,U8_T bit)
{
	(GPIOx)->OMCR  = ((GPIOx)->OMCR) & ~(0x01<<bit);
    2e58:	3300      	movi      	r3, 0
    2e5a:	2b01      	subi      	r3, 2
    2e5c:	904a      	ld.w      	r2, (r0, 0x28)
    2e5e:	70c7      	rotl      	r3, r1
    2e60:	68c8      	and      	r3, r2
    2e62:	b06a      	st.w      	r3, (r0, 0x28)
}
    2e64:	783c      	rts

00002e66 <GPIO_DriveStrength_EN>:
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_DriveStrength_EN(CSP_GPIO_T *GPIOx,U8_T bit)
{
	(GPIOx)->DSCR  = ((GPIOx)->DSCR) | (0x03<<(bit*2));
    2e66:	4121      	lsli      	r1, r1, 1
    2e68:	3303      	movi      	r3, 3
    2e6a:	9049      	ld.w      	r2, (r0, 0x24)
    2e6c:	70c4      	lsl      	r3, r1
    2e6e:	6cc8      	or      	r3, r2
    2e70:	b069      	st.w      	r3, (r0, 0x24)
}
    2e72:	783c      	rts

00002e74 <GPIO_DriveStrength_DIS>:
void GPIO_DriveStrength_DIS(CSP_GPIO_T *GPIOx,U8_T bit)
{
    2e74:	0410      	br      	0x2e94	// 2e94 <GPIO_DriveStrength_DIS+0x20>
    2e76:	0000      	bkpt
    2e78:	20000050 	.long	0x20000050
    2e7c:	fffff0ff 	.long	0xfffff0ff
    2e80:	ffff0fff 	.long	0xffff0fff
    2e84:	fff10000 	.long	0xfff10000
    2e88:	ff100000 	.long	0xff100000
    2e8c:	0fffffff 	.long	0x0fffffff
    2e90:	2000003c 	.long	0x2000003c
	(GPIOx)->DSCR  = ((GPIOx)->DSCR) & ~(0x03<<(bit*2));
    2e94:	4121      	lsli      	r1, r1, 1
    2e96:	3303      	movi      	r3, 3
    2e98:	70c4      	lsl      	r3, r1
    2e9a:	9049      	ld.w      	r2, (r0, 0x24)
    2e9c:	6cce      	nor      	r3, r3
    2e9e:	68c8      	and      	r3, r2
    2ea0:	b069      	st.w      	r3, (r0, 0x24)
}
    2ea2:	783c      	rts

00002ea4 <GPIO_IntGroup_Set>:
//EntryParameter:
//IO_MODE:IGRP(IO INT GROUP)
//ReturnValue:NONE
/*************************************************************/  
void GPIO_IntGroup_Set(GPIO_Group_TypeDef IO_MODE)
{
    2ea4:	14d0      	push      	r15
        switch (IO_MODE)
    2ea6:	3804      	cmphsi      	r0, 5
    2ea8:	080b      	bt      	0x2ebe	// 2ebe <GPIO_IntGroup_Set+0x1a>
    2eaa:	1361      	lrw      	r3, 0x2000003c	// 302c <GPIOA0_EXI_Init+0xf2>
        {
            case 0:EXIGRP->IGRPL  = 0X00000000;EXIGRP->IGRPH  = 0X00000000;break;               
            case 1:EXIGRP->IGRPL  = 0X11111111;EXIGRP->IGRPH  = 0X11111111;break;
            case 2:EXIGRP->IGRPL  = 0X22222222;EXIGRP->IGRPH  = 0X22222222;break;
            case 3:EXIGRP->IGRPL  = 0X33333333;EXIGRP->IGRPH  = 0X33333333;break;
			case 4:EXIGRP->IGRPL  = 0X44444444;EXIGRP->IGRPH  = 0X44444444;break;
    2eac:	9360      	ld.w      	r3, (r3, 0)
        switch (IO_MODE)
    2eae:	e00011f9 	bsr      	0x52a0	// 52a0 <___gnu_csky_case_uqi>
    2eb2:	0703      	.short	0x0703
    2eb4:	000d0b09 	.long	0x000d0b09
            case 0:EXIGRP->IGRPL  = 0X00000000;EXIGRP->IGRPH  = 0X00000000;break;               
    2eb8:	3200      	movi      	r2, 0
			case 4:EXIGRP->IGRPL  = 0X44444444;EXIGRP->IGRPH  = 0X44444444;break;
    2eba:	b340      	st.w      	r2, (r3, 0)
    2ebc:	b341      	st.w      	r2, (r3, 0x4)
        }
}
    2ebe:	1490      	pop      	r15
            case 1:EXIGRP->IGRPL  = 0X11111111;EXIGRP->IGRPH  = 0X11111111;break;
    2ec0:	125c      	lrw      	r2, 0x11111111	// 3030 <GPIOA0_EXI_Init+0xf6>
    2ec2:	07fc      	br      	0x2eba	// 2eba <GPIO_IntGroup_Set+0x16>
            case 2:EXIGRP->IGRPL  = 0X22222222;EXIGRP->IGRPH  = 0X22222222;break;
    2ec4:	125c      	lrw      	r2, 0x22222222	// 3034 <GPIOA0_EXI_Init+0xfa>
    2ec6:	07fa      	br      	0x2eba	// 2eba <GPIO_IntGroup_Set+0x16>
            case 3:EXIGRP->IGRPL  = 0X33333333;EXIGRP->IGRPH  = 0X33333333;break;
    2ec8:	125c      	lrw      	r2, 0x33333333	// 3038 <GPIOA0_EXI_Init+0xfe>
    2eca:	07f8      	br      	0x2eba	// 2eba <GPIO_IntGroup_Set+0x16>
			case 4:EXIGRP->IGRPL  = 0X44444444;EXIGRP->IGRPH  = 0X44444444;break;
    2ecc:	125c      	lrw      	r2, 0x44444444	// 303c <GPIOA0_EXI_Init+0x102>
    2ece:	07f6      	br      	0x2eba	// 2eba <GPIO_IntGroup_Set+0x16>

00002ed0 <GPIO_IntGroup_Set_1>:
//GPIOx:GPIOA0,GPIOA1,GPIOB0,GPIOC0,GPIOD0
//bit:0~15
//ReturnValue:NONE
/*************************************************************/  
void GPIO_IntGroup_Set_1(CSP_GPIO_T *GPIOx,U32_T bit)
{
    2ed0:	14c1      	push      	r4
	U8_T Intbank =0;
	U8_T IntGroup = bit;
	U8_T maskshift;
	U32_T rwmask;
	switch((U32_T)GPIOx){
    2ed2:	125c      	lrw      	r2, 0x40041000	// 3040 <GPIOA0_EXI_Init+0x106>
    2ed4:	6482      	cmpne      	r0, r2
	U8_T IntGroup = bit;
    2ed6:	74c4      	zextb      	r3, r1
	switch((U32_T)GPIOx){
    2ed8:	0c20      	bf      	0x2f18	// 2f18 <GPIO_IntGroup_Set_1+0x48>
    2eda:	6408      	cmphs      	r2, r0
    2edc:	0c06      	bf      	0x2ee8	// 2ee8 <GPIO_IntGroup_Set_1+0x18>
    2ede:	125a      	lrw      	r2, 0x40040100	// 3044 <GPIOA0_EXI_Init+0x10a>
    2ee0:	6482      	cmpne      	r0, r2
    2ee2:	0c0b      	bf      	0x2ef8	// 2ef8 <GPIO_IntGroup_Set_1+0x28>
	U8_T Intbank =0;
    2ee4:	3200      	movi      	r2, 0
    2ee6:	040a      	br      	0x2efa	// 2efa <GPIO_IntGroup_Set_1+0x2a>
	switch((U32_T)GPIOx){
    2ee8:	1258      	lrw      	r2, 0x40042000	// 3048 <GPIOA0_EXI_Init+0x10e>
    2eea:	6482      	cmpne      	r0, r2
    2eec:	0c18      	bf      	0x2f1c	// 2f1c <GPIO_IntGroup_Set_1+0x4c>
    2eee:	1258      	lrw      	r2, 0x40043000	// 304c <GPIOA0_EXI_Init+0x112>
    2ef0:	6482      	cmpne      	r0, r2
    2ef2:	0bf9      	bt      	0x2ee4	// 2ee4 <GPIO_IntGroup_Set_1+0x14>
		break;
		case APB_GPIOC0Base:
			Intbank = 3;
		break;
		case APB_GPIOD0Base:
			Intbank = 4;
    2ef4:	3204      	movi      	r2, 4
		break;
    2ef6:	0402      	br      	0x2efa	// 2efa <GPIO_IntGroup_Set_1+0x2a>
			Intbank = 1;
    2ef8:	3201      	movi      	r2, 1
		default:
		break;
	}		
	if(bit < 8){
    2efa:	3907      	cmphsi      	r1, 8
    2efc:	120c      	lrw      	r0, 0x2000003c	// 302c <GPIOA0_EXI_Init+0xf2>
    2efe:	0811      	bt      	0x2f20	// 2f20 <GPIO_IntGroup_Set_1+0x50>
		maskshift = IntGroup<<2 ;
    2f00:	4362      	lsli      	r3, r3, 2
		rwmask = ~(0xF << maskshift);
    2f02:	744c      	zextb      	r1, r3
    2f04:	330f      	movi      	r3, 15
		EXIGRP ->IGRPL = ((EXIGRP ->IGRPL) & rwmask) | (Intbank << maskshift);
    2f06:	9000      	ld.w      	r0, (r0, 0)
		rwmask = ~(0xF << maskshift);
    2f08:	70c4      	lsl      	r3, r1
		EXIGRP ->IGRPL = ((EXIGRP ->IGRPL) & rwmask) | (Intbank << maskshift);
    2f0a:	9080      	ld.w      	r4, (r0, 0)
		rwmask = ~(0xF << maskshift);
    2f0c:	6cce      	nor      	r3, r3
		EXIGRP ->IGRPL = ((EXIGRP ->IGRPL) & rwmask) | (Intbank << maskshift);
    2f0e:	68d0      	and      	r3, r4
    2f10:	7084      	lsl      	r2, r1
    2f12:	6c8c      	or      	r2, r3
    2f14:	b040      	st.w      	r2, (r0, 0)
	else{
		maskshift = (IntGroup-8)<<2 ;
		rwmask = ~(0xF << maskshift);
		EXIGRP ->IGRPH = ((EXIGRP ->IGRPH) & rwmask) | (Intbank << maskshift);
	}		
}
    2f16:	1481      	pop      	r4
			Intbank = 2;
    2f18:	3202      	movi      	r2, 2
		break;
    2f1a:	07f0      	br      	0x2efa	// 2efa <GPIO_IntGroup_Set_1+0x2a>
			Intbank = 3;
    2f1c:	3203      	movi      	r2, 3
		break;
    2f1e:	07ee      	br      	0x2efa	// 2efa <GPIO_IntGroup_Set_1+0x2a>
		maskshift = (IntGroup-8)<<2 ;
    2f20:	2b07      	subi      	r3, 8
    2f22:	4362      	lsli      	r3, r3, 2
		rwmask = ~(0xF << maskshift);
    2f24:	74cc      	zextb      	r3, r3
    2f26:	310f      	movi      	r1, 15
		EXIGRP ->IGRPH = ((EXIGRP ->IGRPH) & rwmask) | (Intbank << maskshift);
    2f28:	9000      	ld.w      	r0, (r0, 0)
		rwmask = ~(0xF << maskshift);
    2f2a:	704c      	lsl      	r1, r3
		EXIGRP ->IGRPH = ((EXIGRP ->IGRPH) & rwmask) | (Intbank << maskshift);
    2f2c:	9081      	ld.w      	r4, (r0, 0x4)
		rwmask = ~(0xF << maskshift);
    2f2e:	6c46      	nor      	r1, r1
		EXIGRP ->IGRPH = ((EXIGRP ->IGRPH) & rwmask) | (Intbank << maskshift);
    2f30:	6850      	and      	r1, r4
    2f32:	708c      	lsl      	r2, r3
    2f34:	6c84      	or      	r2, r1
    2f36:	b041      	st.w      	r2, (r0, 0x4)
}
    2f38:	07ef      	br      	0x2f16	// 2f16 <GPIO_IntGroup_Set_1+0x46>

00002f3a <GPIOA0_EXI_Init>:
//IO EXI SET 
//EntryParameter:EXI_IO(EXI0~EXI13)
//ReturnValue:NONE
/*************************************************************/  
void GPIOA0_EXI_Init(GPIO_EXI_TypeDef EXI_IO)
{
    2f3a:	14d0      	push      	r15
    switch (EXI_IO)
    2f3c:	380f      	cmphsi      	r0, 16
    2f3e:	0812      	bt      	0x2f62	// 2f62 <GPIOA0_EXI_Init+0x28>
    2f40:	1264      	lrw      	r3, 0x20000050	// 3050 <GPIOA0_EXI_Init+0x116>
    2f42:	e00011af 	bsr      	0x52a0	// 52a0 <___gnu_csky_case_uqi>
    2f46:	0f08      	.short	0x0f08
    2f48:	2b241d15 	.long	0x2b241d15
    2f4c:	463f3932 	.long	0x463f3932
    2f50:	625b544c 	.long	0x625b544c
    2f54:	6e69      	.short	0x6e69
    {
        case 0:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0X00000001;break;
    2f56:	9340      	ld.w      	r2, (r3, 0)
    2f58:	9260      	ld.w      	r3, (r2, 0)
    2f5a:	310f      	movi      	r1, 15
    2f5c:	68c5      	andn      	r3, r1
    2f5e:	3ba0      	bseti      	r3, r3, 0
        case 1:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0X00000010;break;
    2f60:	b260      	st.w      	r3, (r2, 0)
        case 12:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0X00010000;break;
        case 13:GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0X00100000;break;
		case 14:GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0X00100000;break;
		case 15:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0X00100000;break;
    }
}
    2f62:	1490      	pop      	r15
        case 1:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0X00000010;break;
    2f64:	9340      	ld.w      	r2, (r3, 0)
    2f66:	9260      	ld.w      	r3, (r2, 0)
    2f68:	31f0      	movi      	r1, 240
    2f6a:	68c5      	andn      	r3, r1
    2f6c:	3ba4      	bseti      	r3, r3, 4
    2f6e:	07f9      	br      	0x2f60	// 2f60 <GPIOA0_EXI_Init+0x26>
        case 2:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000100;break;
    2f70:	9320      	ld.w      	r1, (r3, 0)
    2f72:	32f0      	movi      	r2, 240
    2f74:	9160      	ld.w      	r3, (r1, 0)
    2f76:	4244      	lsli      	r2, r2, 4
    2f78:	68c9      	andn      	r3, r2
    2f7a:	3ba8      	bseti      	r3, r3, 8
        case 6:GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0X01000000;break;
    2f7c:	b160      	st.w      	r3, (r1, 0)
    2f7e:	07f2      	br      	0x2f62	// 2f62 <GPIOA0_EXI_Init+0x28>
        case 3:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0X00001000;break;
    2f80:	9320      	ld.w      	r1, (r3, 0)
    2f82:	32f0      	movi      	r2, 240
    2f84:	9160      	ld.w      	r3, (r1, 0)
    2f86:	4248      	lsli      	r2, r2, 8
    2f88:	68c9      	andn      	r3, r2
    2f8a:	3bac      	bseti      	r3, r3, 12
    2f8c:	07f8      	br      	0x2f7c	// 2f7c <GPIOA0_EXI_Init+0x42>
        case 4:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0X00010000;break;
    2f8e:	9320      	ld.w      	r1, (r3, 0)
    2f90:	32f0      	movi      	r2, 240
    2f92:	9160      	ld.w      	r3, (r1, 0)
    2f94:	424c      	lsli      	r2, r2, 12
    2f96:	68c9      	andn      	r3, r2
    2f98:	3bb0      	bseti      	r3, r3, 16
    2f9a:	07f1      	br      	0x2f7c	// 2f7c <GPIOA0_EXI_Init+0x42>
        case 5:GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0X00100000;break;
    2f9c:	9320      	ld.w      	r1, (r3, 0)
    2f9e:	32f0      	movi      	r2, 240
    2fa0:	9160      	ld.w      	r3, (r1, 0)
    2fa2:	4250      	lsli      	r2, r2, 16
    2fa4:	68c9      	andn      	r3, r2
    2fa6:	3bb4      	bseti      	r3, r3, 20
    2fa8:	07ea      	br      	0x2f7c	// 2f7c <GPIOA0_EXI_Init+0x42>
        case 6:GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0X01000000;break;
    2faa:	9320      	ld.w      	r1, (r3, 0)
    2fac:	32f0      	movi      	r2, 240
    2fae:	9160      	ld.w      	r3, (r1, 0)
    2fb0:	4254      	lsli      	r2, r2, 20
    2fb2:	68c9      	andn      	r3, r2
    2fb4:	3bb8      	bseti      	r3, r3, 24
    2fb6:	07e3      	br      	0x2f7c	// 2f7c <GPIOA0_EXI_Init+0x42>
        case 7:GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0X10000000;break;
    2fb8:	9340      	ld.w      	r2, (r3, 0)
    2fba:	9260      	ld.w      	r3, (r2, 0)
    2fbc:	4364      	lsli      	r3, r3, 4
    2fbe:	4b64      	lsri      	r3, r3, 4
    2fc0:	3bbc      	bseti      	r3, r3, 28
    2fc2:	07cf      	br      	0x2f60	// 2f60 <GPIOA0_EXI_Init+0x26>
        case 8:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0X00000001;break;
    2fc4:	9340      	ld.w      	r2, (r3, 0)
    2fc6:	9261      	ld.w      	r3, (r2, 0x4)
    2fc8:	310f      	movi      	r1, 15
    2fca:	68c5      	andn      	r3, r1
    2fcc:	3ba0      	bseti      	r3, r3, 0
		case 15:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0X00100000;break;
    2fce:	b261      	st.w      	r3, (r2, 0x4)
}
    2fd0:	07c9      	br      	0x2f62	// 2f62 <GPIOA0_EXI_Init+0x28>
        case 9:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F) | 0X00000010;break;
    2fd2:	9340      	ld.w      	r2, (r3, 0)
    2fd4:	9261      	ld.w      	r3, (r2, 0x4)
    2fd6:	31f0      	movi      	r1, 240
    2fd8:	68c5      	andn      	r3, r1
    2fda:	3ba4      	bseti      	r3, r3, 4
    2fdc:	07f9      	br      	0x2fce	// 2fce <GPIOA0_EXI_Init+0x94>
        case 10:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF) | 0X00000100;break;
    2fde:	9320      	ld.w      	r1, (r3, 0)
    2fe0:	32f0      	movi      	r2, 240
    2fe2:	9161      	ld.w      	r3, (r1, 0x4)
    2fe4:	4244      	lsli      	r2, r2, 4
    2fe6:	68c9      	andn      	r3, r2
    2fe8:	3ba8      	bseti      	r3, r3, 8
		case 14:GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0X00100000;break;
    2fea:	b161      	st.w      	r3, (r1, 0x4)
    2fec:	07bb      	br      	0x2f62	// 2f62 <GPIOA0_EXI_Init+0x28>
        case 11:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF) | 0X00001000;break;
    2fee:	9320      	ld.w      	r1, (r3, 0)
    2ff0:	32f0      	movi      	r2, 240
    2ff2:	9161      	ld.w      	r3, (r1, 0x4)
    2ff4:	4248      	lsli      	r2, r2, 8
    2ff6:	68c9      	andn      	r3, r2
    2ff8:	3bac      	bseti      	r3, r3, 12
    2ffa:	07f8      	br      	0x2fea	// 2fea <GPIOA0_EXI_Init+0xb0>
        case 12:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0X00010000;break;
    2ffc:	9320      	ld.w      	r1, (r3, 0)
    2ffe:	32f0      	movi      	r2, 240
    3000:	9161      	ld.w      	r3, (r1, 0x4)
    3002:	424c      	lsli      	r2, r2, 12
    3004:	68c9      	andn      	r3, r2
    3006:	3bb0      	bseti      	r3, r3, 16
    3008:	07f1      	br      	0x2fea	// 2fea <GPIOA0_EXI_Init+0xb0>
        case 13:GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0X00100000;break;
    300a:	9320      	ld.w      	r1, (r3, 0)
    300c:	32f0      	movi      	r2, 240
    300e:	9161      	ld.w      	r3, (r1, 0x4)
    3010:	4250      	lsli      	r2, r2, 16
		case 14:GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0X00100000;break;
    3012:	68c9      	andn      	r3, r2
    3014:	3bb4      	bseti      	r3, r3, 20
    3016:	07ea      	br      	0x2fea	// 2fea <GPIOA0_EXI_Init+0xb0>
    3018:	9320      	ld.w      	r1, (r3, 0)
    301a:	32f1      	movi      	r2, 241
    301c:	9161      	ld.w      	r3, (r1, 0x4)
    301e:	4254      	lsli      	r2, r2, 20
    3020:	07f9      	br      	0x3012	// 3012 <GPIOA0_EXI_Init+0xd8>
		case 15:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0X00100000;break;
    3022:	9340      	ld.w      	r2, (r3, 0)
    3024:	9261      	ld.w      	r3, (r2, 0x4)
    3026:	3bb4      	bseti      	r3, r3, 20
    3028:	07d3      	br      	0x2fce	// 2fce <GPIOA0_EXI_Init+0x94>
    302a:	0000      	bkpt
    302c:	2000003c 	.long	0x2000003c
    3030:	11111111 	.long	0x11111111
    3034:	22222222 	.long	0x22222222
    3038:	33333333 	.long	0x33333333
    303c:	44444444 	.long	0x44444444
    3040:	40041000 	.long	0x40041000
    3044:	40040100 	.long	0x40040100
    3048:	40042000 	.long	0x40042000
    304c:	40043000 	.long	0x40043000
    3050:	20000050 	.long	0x20000050

00003054 <GPIOA1_EXI_Init>:
void GPIOA1_EXI_Init(GPIO_EXI_TypeDef EXI_IO)
{
    3054:	14d0      	push      	r15
    switch (EXI_IO)
    3056:	3805      	cmphsi      	r0, 6
    3058:	080f      	bt      	0x3076	// 3076 <GPIOA1_EXI_Init+0x22>
    305a:	1274      	lrw      	r3, 0x20000050	// 31a8 <GPIOA00_Set_ResetPin+0x14>
    305c:	1254      	lrw      	r2, 0x2000004c	// 31ac <GPIOA00_Set_ResetPin+0x18>
        case 0:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0X00000001;break;
        case 1:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0X00000010;break;
        case 2:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000100;break;
        case 3:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0X00001000;break;
        case 4:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0X00010000;break;
        case 5:GPIOA1->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0X00100000;break;
    305e:	9360      	ld.w      	r3, (r3, 0)
    3060:	9220      	ld.w      	r1, (r2, 0)
    3062:	9360      	ld.w      	r3, (r3, 0)
    switch (EXI_IO)
    3064:	e000111e 	bsr      	0x52a0	// 52a0 <___gnu_csky_case_uqi>
    3068:	110c0803 	.long	0x110c0803
    306c:	1b16      	.short	0x1b16
        case 0:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0X00000001;break;
    306e:	320f      	movi      	r2, 15
    3070:	68c9      	andn      	r3, r2
    3072:	3ba0      	bseti      	r3, r3, 0
        case 5:GPIOA1->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0X00100000;break;
    3074:	b160      	st.w      	r3, (r1, 0)
		default:break;
    }
}
    3076:	1490      	pop      	r15
        case 1:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0X00000010;break;
    3078:	32f0      	movi      	r2, 240
    307a:	68c9      	andn      	r3, r2
    307c:	3ba4      	bseti      	r3, r3, 4
    307e:	07fb      	br      	0x3074	// 3074 <GPIOA1_EXI_Init+0x20>
        case 2:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000100;break;
    3080:	32f0      	movi      	r2, 240
    3082:	4244      	lsli      	r2, r2, 4
    3084:	68c9      	andn      	r3, r2
    3086:	3ba8      	bseti      	r3, r3, 8
    3088:	07f6      	br      	0x3074	// 3074 <GPIOA1_EXI_Init+0x20>
        case 3:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0X00001000;break;
    308a:	32f0      	movi      	r2, 240
    308c:	4248      	lsli      	r2, r2, 8
    308e:	68c9      	andn      	r3, r2
    3090:	3bac      	bseti      	r3, r3, 12
    3092:	07f1      	br      	0x3074	// 3074 <GPIOA1_EXI_Init+0x20>
        case 4:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0X00010000;break;
    3094:	32f0      	movi      	r2, 240
    3096:	424c      	lsli      	r2, r2, 12
    3098:	68c9      	andn      	r3, r2
    309a:	3bb0      	bseti      	r3, r3, 16
    309c:	07ec      	br      	0x3074	// 3074 <GPIOA1_EXI_Init+0x20>
        case 5:GPIOA1->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0X00100000;break;
    309e:	32f0      	movi      	r2, 240
    30a0:	4250      	lsli      	r2, r2, 16
    30a2:	68c9      	andn      	r3, r2
    30a4:	3bb4      	bseti      	r3, r3, 20
    30a6:	07e7      	br      	0x3074	// 3074 <GPIOA1_EXI_Init+0x20>

000030a8 <GPIOB0_EXI_Init>:
void GPIOB0_EXI_Init(GPIO_EXI_TypeDef EXI_IO)
{
    switch (EXI_IO)
    30a8:	3840      	cmpnei      	r0, 0
    30aa:	0c04      	bf      	0x30b2	// 30b2 <GPIOB0_EXI_Init+0xa>
    30ac:	3841      	cmpnei      	r0, 1
    30ae:	0c0a      	bf      	0x30c2	// 30c2 <GPIOB0_EXI_Init+0x1a>
    {
        case 0:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0X00000001;break;
        case 1:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0X00000010;break;
        default:break;
    }
}
    30b0:	783c      	rts
        case 0:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0X00000001;break;
    30b2:	1260      	lrw      	r3, 0x20000048	// 31b0 <GPIOA00_Set_ResetPin+0x1c>
    30b4:	310f      	movi      	r1, 15
    30b6:	9340      	ld.w      	r2, (r3, 0)
    30b8:	9260      	ld.w      	r3, (r2, 0)
    30ba:	68c5      	andn      	r3, r1
    30bc:	3ba0      	bseti      	r3, r3, 0
        case 1:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0X00000010;break;
    30be:	b260      	st.w      	r3, (r2, 0)
}
    30c0:	07f8      	br      	0x30b0	// 30b0 <GPIOB0_EXI_Init+0x8>
        case 1:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0X00000010;break;
    30c2:	117c      	lrw      	r3, 0x20000048	// 31b0 <GPIOA00_Set_ResetPin+0x1c>
    30c4:	31f0      	movi      	r1, 240
    30c6:	9340      	ld.w      	r2, (r3, 0)
    30c8:	9260      	ld.w      	r3, (r2, 0)
    30ca:	68c5      	andn      	r3, r1
    30cc:	3ba4      	bseti      	r3, r3, 4
    30ce:	07f8      	br      	0x30be	// 30be <GPIOB0_EXI_Init+0x16>

000030d0 <GPIOC0_EXI_Init>:
void GPIOC0_EXI_Init(GPIO_EXI_TypeDef EXI_IO)
{
    30d0:	14d0      	push      	r15
    switch (EXI_IO)
    30d2:	3803      	cmphsi      	r0, 4
    30d4:	080c      	bt      	0x30ec	// 30ec <GPIOC0_EXI_Init+0x1c>
    30d6:	1178      	lrw      	r3, 0x20000044	// 31b4 <GPIOA00_Set_ResetPin+0x20>
    30d8:	e00010e4 	bsr      	0x52a0	// 52a0 <___gnu_csky_case_uqi>
    30dc:	170f0902 	.long	0x170f0902
    {
        case 0:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFFFFF0) | 0X00000001;break;
    30e0:	9340      	ld.w      	r2, (r3, 0)
    30e2:	9260      	ld.w      	r3, (r2, 0)
    30e4:	310f      	movi      	r1, 15
    30e6:	68c5      	andn      	r3, r1
    30e8:	3ba0      	bseti      	r3, r3, 0
        case 1:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFFFF0F) | 0X00000010;break;
    30ea:	b260      	st.w      	r3, (r2, 0)
        case 2:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFFF0FF) | 0X00000100;break;
        case 3:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFF0FFF) | 0X00001000;break;
        default:break;
    }
}
    30ec:	1490      	pop      	r15
        case 1:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFFFF0F) | 0X00000010;break;
    30ee:	9340      	ld.w      	r2, (r3, 0)
    30f0:	9260      	ld.w      	r3, (r2, 0)
    30f2:	31f0      	movi      	r1, 240
    30f4:	68c5      	andn      	r3, r1
    30f6:	3ba4      	bseti      	r3, r3, 4
    30f8:	07f9      	br      	0x30ea	// 30ea <GPIOC0_EXI_Init+0x1a>
        case 2:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFFF0FF) | 0X00000100;break;
    30fa:	9320      	ld.w      	r1, (r3, 0)
    30fc:	32f0      	movi      	r2, 240
    30fe:	9160      	ld.w      	r3, (r1, 0)
    3100:	4244      	lsli      	r2, r2, 4
    3102:	68c9      	andn      	r3, r2
    3104:	3ba8      	bseti      	r3, r3, 8
        case 3:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFF0FFF) | 0X00001000;break;
    3106:	b160      	st.w      	r3, (r1, 0)
}
    3108:	07f2      	br      	0x30ec	// 30ec <GPIOC0_EXI_Init+0x1c>
        case 3:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFF0FFF) | 0X00001000;break;
    310a:	9320      	ld.w      	r1, (r3, 0)
    310c:	32f0      	movi      	r2, 240
    310e:	9160      	ld.w      	r3, (r1, 0)
    3110:	4248      	lsli      	r2, r2, 8
    3112:	68c9      	andn      	r3, r2
    3114:	3bac      	bseti      	r3, r3, 12
    3116:	07f8      	br      	0x3106	// 3106 <GPIOC0_EXI_Init+0x36>

00003118 <GPIO_EXI_EN>:
void GPIO_EXI_EN(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO)
{
    (GPIOx)->IECR  |= 1<<EXI_IO;
    3118:	3301      	movi      	r3, 1
    311a:	904b      	ld.w      	r2, (r0, 0x2c)
    311c:	70c4      	lsl      	r3, r1
    311e:	6cc8      	or      	r3, r2
    3120:	b06b      	st.w      	r3, (r0, 0x2c)
}
    3122:	783c      	rts

00003124 <GPIO_EXI_ENSet>:
void GPIO_EXI_ENSet(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO)
{
    (GPIOx)->IEER  |= 1<<EXI_IO;
    3124:	3301      	movi      	r3, 1
    3126:	904c      	ld.w      	r2, (r0, 0x30)
    3128:	70c4      	lsl      	r3, r1
    312a:	6cc8      	or      	r3, r2
    312c:	b06c      	st.w      	r3, (r0, 0x30)
}
    312e:	783c      	rts

00003130 <GPIO_EXI_DISSet>:
void GPIO_EXI_DISSet(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO)
{
    (GPIOx)->IEDR  |= 1<<EXI_IO;
    3130:	3301      	movi      	r3, 1
    3132:	904d      	ld.w      	r2, (r0, 0x34)
    3134:	70c4      	lsl      	r3, r1
    3136:	6cc8      	or      	r3, r2
    3138:	b06d      	st.w      	r3, (r0, 0x34)
}
    313a:	783c      	rts

0000313c <GPIO_Write_High>:
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_Write_High(CSP_GPIO_T *GPIOx,U8_T bit)
{
        (GPIOx)->SODR = (1ul<<bit);
    313c:	3301      	movi      	r3, 1
    313e:	70c4      	lsl      	r3, r1
    3140:	b063      	st.w      	r3, (r0, 0xc)
}
    3142:	783c      	rts

00003144 <GPIO_Write_Low>:
void GPIO_Write_Low(CSP_GPIO_T *GPIOx,U8_T bit)
{
        (GPIOx)->CODR = (1ul<<bit);
    3144:	3301      	movi      	r3, 1
    3146:	70c4      	lsl      	r3, r1
    3148:	b064      	st.w      	r3, (r0, 0x10)
}
    314a:	783c      	rts

0000314c <GPIO_Set_Value>:
//bitposi:0~15 bitval:0~1 0=low 1=high
//ReturnValue:VALUE
/*************************************************************/
void GPIO_Set_Value(CSP_GPIO_T *GPIOx,U8_T bitposi,U8_T bitval)
{
    if (bitval==1)
    314c:	3a41      	cmpnei      	r2, 1
    314e:	0804      	bt      	0x3156	// 3156 <GPIO_Set_Value+0xa>
    {
        (GPIOx)->SODR = (1ul<<bitposi);
    3150:	7084      	lsl      	r2, r1
    3152:	b043      	st.w      	r2, (r0, 0xc)
    }
    else if ((bitval==0))
    {
        (GPIOx)->CODR = (1ul<<bitposi);
    }
}
    3154:	783c      	rts
    else if ((bitval==0))
    3156:	3a40      	cmpnei      	r2, 0
    3158:	0bfe      	bt      	0x3154	// 3154 <GPIO_Set_Value+0x8>
        (GPIOx)->CODR = (1ul<<bitposi);
    315a:	3301      	movi      	r3, 1
    315c:	70c4      	lsl      	r3, r1
    315e:	b064      	st.w      	r3, (r0, 0x10)
}
    3160:	07fa      	br      	0x3154	// 3154 <GPIO_Set_Value+0x8>

00003162 <GPIO_Reverse>:
//ReturnValue:VALUE
/*************************************************************/
void GPIO_Reverse(CSP_GPIO_T *GPIOx,U8_T bit)
{
     uint32_t dat = 0;
     dat=((GPIOx)->ODSR>>bit)&1ul;
    3162:	9045      	ld.w      	r2, (r0, 0x14)
    3164:	3301      	movi      	r3, 1
    3166:	7085      	lsr      	r2, r1
    3168:	688c      	and      	r2, r3
     {
       if (dat==1)  
    316a:	3a40      	cmpnei      	r2, 0
    316c:	70c4      	lsl      	r3, r1
    316e:	0c03      	bf      	0x3174	// 3174 <GPIO_Reverse+0x12>
       {
           (GPIOx)->CODR = (1ul<<bit);
    3170:	b064      	st.w      	r3, (r0, 0x10)
       {
           (GPIOx)->SODR = (1ul<<bit);
           return;
       }
     }
}
    3172:	783c      	rts
           (GPIOx)->SODR = (1ul<<bit);
    3174:	b063      	st.w      	r3, (r0, 0xc)
           return;
    3176:	07fe      	br      	0x3172	// 3172 <GPIO_Reverse+0x10>

00003178 <GPIO_Read_Status>:
/*************************************************************/
uint8_t GPIO_Read_Status(CSP_GPIO_T *GPIOx,U8_T bit)
{
    uint8_t value = 0;
    uint32_t dat = 0;
    dat=((GPIOx)->PSDR)&(1<<bit);
    3178:	3301      	movi      	r3, 1
    317a:	9046      	ld.w      	r2, (r0, 0x18)
    317c:	70c4      	lsl      	r3, r1
    317e:	688c      	and      	r2, r3
    if (dat == (1<<bit))								
    3180:	64ca      	cmpne      	r2, r3
	{
	    value = 1;
	} 
    return value;
    3182:	6403      	mvcv      	r0
}
    3184:	783c      	rts

00003186 <GPIO_Read_Output>:
/*************************************************************/
uint8_t GPIO_Read_Output(CSP_GPIO_T *GPIOx,U8_T bit)
{
    uint8_t value = 0;
    uint32_t dat = 0;
    dat=((GPIOx)->ODSR)&(1<<bit);
    3186:	3301      	movi      	r3, 1
    3188:	9045      	ld.w      	r2, (r0, 0x14)
    318a:	70c4      	lsl      	r3, r1
    318c:	688c      	and      	r2, r3
    if (dat == (1<<bit))								
    318e:	64ca      	cmpne      	r2, r3
	{
	    value = 1;
	} 
    return value;
    3190:	6403      	mvcv      	r0
}
    3192:	783c      	rts

00003194 <GPIOA00_Set_ResetPin>:
//EntryParameter:NONE
//ReturnValue:VALUE
/*************************************************************/
void GPIOA00_Set_ResetPin()
{
    GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000006; 
    3194:	1065      	lrw      	r3, 0x20000050	// 31a8 <GPIOA00_Set_ResetPin+0x14>
    3196:	310f      	movi      	r1, 15
    3198:	9340      	ld.w      	r2, (r3, 0)
    319a:	9260      	ld.w      	r3, (r2, 0)
    319c:	68c5      	andn      	r3, r1
    319e:	3ba1      	bseti      	r3, r3, 1
    31a0:	3ba2      	bseti      	r3, r3, 2
    31a2:	b260      	st.w      	r3, (r2, 0)
}
    31a4:	783c      	rts
    31a6:	0000      	bkpt
    31a8:	20000050 	.long	0x20000050
    31ac:	2000004c 	.long	0x2000004c
    31b0:	20000048 	.long	0x20000048
    31b4:	20000044 	.long	0x20000044

000031b8 <I2C_DeInit>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_DeInit(void)
{
    I2C0->ECR   = I2C_RESET_VALUE;
    31b8:	1067      	lrw      	r3, 0x20000008	// 31d4 <I2C_DeInit+0x1c>
    31ba:	3200      	movi      	r2, 0
    31bc:	9360      	ld.w      	r3, (r3, 0)
    31be:	b354      	st.w      	r2, (r3, 0x50)
    I2C0->DCR   = I2C_RESET_VALUE;
    31c0:	b355      	st.w      	r2, (r3, 0x54)
    I2C0->CR    = I2C_RESET_VALUE;
    31c2:	b358      	st.w      	r2, (r3, 0x60)
    I2C0->MR    = I2C_RESET_VALUE;
    31c4:	b359      	st.w      	r2, (r3, 0x64)
    I2C0->IER   = I2C_RESET_VALUE;
    31c6:	b35d      	st.w      	r2, (r3, 0x74)
    I2C0->IDR   = I2C_RESET_VALUE;
    31c8:	b35e      	st.w      	r2, (r3, 0x78)
    I2C0->DAT   = I2C_RESET_VALUE;
    31ca:	237f      	addi      	r3, 128
    31cc:	b340      	st.w      	r2, (r3, 0)
    I2C0->ADR   = I2C_RESET_VALUE;
    31ce:	b341      	st.w      	r2, (r3, 0x4)
    I2C0->THOLD = I2C_RESET_VALUE;
    31d0:	b342      	st.w      	r2, (r3, 0x8)
}  
    31d2:	783c      	rts
    31d4:	20000008 	.long	0x20000008

000031d8 <I2C_Master_Init>:
//MR_u32：Frequency/（MR_u32+4）=I2C clk
//thold_u32：hold/setup time=thold_u32*PCLK
//ReturnValue:NONE
/*************************************************************/
void I2C_Master_Init(I2C_IO_TypeDef I2C_IO, I2C_MODE_TypeDef I2C_MDOE,U16_T MR_u32, U8_T thold_u32)
{
    31d8:	14c2      	push      	r4-r5
    if (I2C_IO==I2C_G0)
    31da:	3840      	cmpnei      	r0, 0
    31dc:	0821      	bt      	0x321e	// 321e <I2C_Master_Init+0x46>
    {
    GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF00)  | 0x00000055;            //PA0.9->SDA, PA0.8->SCL
    31de:	1305      	lrw      	r0, 0x20000050	// 3370 <I2C_AcknowledgeConfig+0x10>
    31e0:	35ff      	movi      	r5, 255
    31e2:	9080      	ld.w      	r4, (r0, 0)
    31e4:	9401      	ld.w      	r0, (r4, 0x4)
    31e6:	6815      	andn      	r0, r5
    31e8:	3555      	movi      	r5, 85
    31ea:	6c14      	or      	r0, r5
    31ec:	b401      	st.w      	r0, (r4, 0x4)
    }
    else if(I2C_IO==I2C_G2)
    {
    GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFF00F)  | 0x00000770;            //PA1.1->SDA, PA1.2->SCL   
    }
    I2C0->ECR = I2C_I2C;                                                //Enable I2C clock
    31ee:	1302      	lrw      	r0, 0x20000008	// 3374 <I2C_AcknowledgeConfig+0x14>
    31f0:	3402      	movi      	r4, 2
    31f2:	9000      	ld.w      	r0, (r0, 0)
    31f4:	b094      	st.w      	r4, (r0, 0x50)
	I2C0->CR = I2C_SWRST;                                               //I2C Generate a software reset
    if (I2C_MDOE==FAST_MODE)
    31f6:	3941      	cmpnei      	r1, 1
	I2C0->CR = I2C_SWRST;                                               //I2C Generate a software reset
    31f8:	3401      	movi      	r4, 1
    31fa:	b098      	st.w      	r4, (r0, 0x60)
    if (I2C_MDOE==FAST_MODE)
    31fc:	0804      	bt      	0x3204	// 3204 <I2C_Master_Init+0x2c>
    {    
    I2C0->MR = MR_u32+0X1000;                                           //76KHz @PCLK 24MHz  e.g:24000000/(0x138+4)=76000   MR_u32=0x138            
    31fe:	3180      	movi      	r1, 128
    3200:	4125      	lsli      	r1, r1, 5
    3202:	6084      	addu      	r2, r1
    }                                                                   //I2C pre-scalar，and ，mode select
    else I2C0->MR = MR_u32;
    3204:	b059      	st.w      	r2, (r0, 0x64)
    I2C0->THOLD = thold_u32;                                            //I2C Hold/Setup delays
    3206:	3280      	movi      	r2, 128
    3208:	6080      	addu      	r2, r0
    320a:	b262      	st.w      	r3, (r2, 0x8)
    I2C0->IER = I2C_IER_MASK;                                           //Enable Si interrupt
    320c:	3310      	movi      	r3, 16
    320e:	b07d      	st.w      	r3, (r0, 0x74)
	I2C0->CR = I2C_ENA;                                                 //Enable I2C
    3210:	3380      	movi      	r3, 128
    3212:	4361      	lsli      	r3, r3, 1
    3214:	b078      	st.w      	r3, (r0, 0x60)
	I2CMode=1;
    3216:	3201      	movi      	r2, 1
    3218:	1278      	lrw      	r3, 0x20000181	// 3378 <I2C_AcknowledgeConfig+0x18>
    321a:	a340      	st.b      	r2, (r3, 0)
}
    321c:	1482      	pop      	r4-r5
    else if(I2C_IO==I2C_G1)
    321e:	3841      	cmpnei      	r0, 1
    3220:	080c      	bt      	0x3238	// 3238 <I2C_Master_Init+0x60>
    GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF00FFF)  | 0x00066000;            //PA0.4->SDA, PA0.3->SCL
    3222:	1214      	lrw      	r0, 0x20000050	// 3370 <I2C_AcknowledgeConfig+0x10>
    3224:	34ff      	movi      	r4, 255
    3226:	90a0      	ld.w      	r5, (r0, 0)
    3228:	448c      	lsli      	r4, r4, 12
    322a:	9500      	ld.w      	r0, (r5, 0)
    322c:	6811      	andn      	r0, r4
    322e:	34cc      	movi      	r4, 204
    3230:	448b      	lsli      	r4, r4, 11
    GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFF00F)  | 0x00000770;            //PA1.1->SDA, PA1.2->SCL   
    3232:	6c10      	or      	r0, r4
    3234:	b500      	st.w      	r0, (r5, 0)
    3236:	07dc      	br      	0x31ee	// 31ee <I2C_Master_Init+0x16>
    else if(I2C_IO==I2C_G2)
    3238:	3842      	cmpnei      	r0, 2
    323a:	0bda      	bt      	0x31ee	// 31ee <I2C_Master_Init+0x16>
    GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFF00F)  | 0x00000770;            //PA1.1->SDA, PA1.2->SCL   
    323c:	1210      	lrw      	r0, 0x2000004c	// 337c <I2C_AcknowledgeConfig+0x1c>
    323e:	34ff      	movi      	r4, 255
    3240:	90a0      	ld.w      	r5, (r0, 0)
    3242:	4484      	lsli      	r4, r4, 4
    3244:	9500      	ld.w      	r0, (r5, 0)
    3246:	6811      	andn      	r0, r4
    3248:	34ee      	movi      	r4, 238
    324a:	4483      	lsli      	r4, r4, 3
    324c:	07f3      	br      	0x3232	// 3232 <I2C_Master_Init+0x5a>

0000324e <I2C_Slave_Init>:
//thold_u32：hold/setup time=thold_u32*PCLK
//adr_u8：slave address （bit1~bit7）
//ReturnValue:NONE
/*************************************************************/
void I2C_Slave_Init(I2C_IO_TypeDef I2C_IO,I2C_MODE_TypeDef I2C_MDOE, U16_T MR_u32, U8_T thold_u32,U8_T adr_u8)
{
    324e:	14c3      	push      	r4-r6
     if (I2C_IO==I2C_G0)
    3250:	3840      	cmpnei      	r0, 0
{
    3252:	d88e000c 	ld.b      	r4, (sp, 0xc)
     if (I2C_IO==I2C_G0)
    3256:	0827      	bt      	0x32a4	// 32a4 <I2C_Slave_Init+0x56>
    {
    GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF00)  | 0x00000055;            //PA0.9->SDA, PA0.8->SCL
    3258:	1206      	lrw      	r0, 0x20000050	// 3370 <I2C_AcknowledgeConfig+0x10>
    325a:	36ff      	movi      	r6, 255
    325c:	90a0      	ld.w      	r5, (r0, 0)
    325e:	9501      	ld.w      	r0, (r5, 0x4)
    3260:	6819      	andn      	r0, r6
    3262:	3655      	movi      	r6, 85
    3264:	6c18      	or      	r0, r6
    3266:	b501      	st.w      	r0, (r5, 0x4)
    }
    else if(I2C_IO==I2C_G2)
    {
    GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFF00F)  | 0x00000770;            //PA1.1->SDA, PA1.2->SCL   
    }
    I2C0->ECR = I2C_I2C;                                //Enable I2C clock
    3268:	1203      	lrw      	r0, 0x20000008	// 3374 <I2C_AcknowledgeConfig+0x14>
    326a:	3502      	movi      	r5, 2
    326c:	9000      	ld.w      	r0, (r0, 0)
    326e:	b0b4      	st.w      	r5, (r0, 0x50)
	I2C0->CR = I2C_SWRST;                               //I2C Generate a software reset
     if (I2C_MDOE==FAST_MODE)
    3270:	3941      	cmpnei      	r1, 1
	I2C0->CR = I2C_SWRST;                               //I2C Generate a software reset
    3272:	3501      	movi      	r5, 1
    3274:	b0b8      	st.w      	r5, (r0, 0x60)
     if (I2C_MDOE==FAST_MODE)
    3276:	0804      	bt      	0x327e	// 327e <I2C_Slave_Init+0x30>
    {    
    I2C0->MR = MR_u32+0X1000;                           //76KHz @PCLK 20MHz  e.g:20000000/(MR_u32+4)=76000   MR_u32=0x103         
    3278:	3180      	movi      	r1, 128
    327a:	4125      	lsli      	r1, r1, 5
    327c:	6084      	addu      	r2, r1
    }                                                   //I2C pre-scalar，and ，mode select
    else I2C0->MR = MR_u32;
    327e:	b059      	st.w      	r2, (r0, 0x64)
    I2C0->THOLD = thold_u32;                            //I2C Hold/Setup delays
    3280:	3280      	movi      	r2, 128
    3282:	6080      	addu      	r2, r0
    3284:	b262      	st.w      	r3, (r2, 0x8)
    I2C0->ADR = adr_u8;
    I2C0->IER = I2C_IER_MASK;                           //Enable Si interrupt
    3286:	3310      	movi      	r3, 16
    I2C0->ADR = adr_u8;
    3288:	b281      	st.w      	r4, (r2, 0x4)
    I2C0->IER = I2C_IER_MASK;                           //Enable Si interrupt
    328a:	b07d      	st.w      	r3, (r0, 0x74)
    I2C0->CR = I2C0->CR | I2C_STA_SLAVE;                //I2C as Slave
    328c:	9078      	ld.w      	r3, (r0, 0x60)
    328e:	b078      	st.w      	r3, (r0, 0x60)
	I2C0->CR = I2C0->CR | I2C_ENA;                      //Enable I2C
    3290:	9078      	ld.w      	r3, (r0, 0x60)
    3292:	3ba8      	bseti      	r3, r3, 8
    3294:	b078      	st.w      	r3, (r0, 0x60)
    I2C0->CR = I2C0->CR | I2C_AA;
    3296:	9078      	ld.w      	r3, (r0, 0x60)
    3298:	3ba1      	bseti      	r3, r3, 1
    329a:	b078      	st.w      	r3, (r0, 0x60)
	I2CMode=0;
    329c:	3200      	movi      	r2, 0
    329e:	1177      	lrw      	r3, 0x20000181	// 3378 <I2C_AcknowledgeConfig+0x18>
    32a0:	a340      	st.b      	r2, (r3, 0)
}
    32a2:	1483      	pop      	r4-r6
    else if(I2C_IO==I2C_G1)
    32a4:	3841      	cmpnei      	r0, 1
    32a6:	080c      	bt      	0x32be	// 32be <I2C_Slave_Init+0x70>
    GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF00FFF)  | 0x00066000;            //PA0.4->SDA, PA0.3->SCL
    32a8:	1112      	lrw      	r0, 0x20000050	// 3370 <I2C_AcknowledgeConfig+0x10>
    32aa:	36ff      	movi      	r6, 255
    32ac:	90a0      	ld.w      	r5, (r0, 0)
    32ae:	46cc      	lsli      	r6, r6, 12
    32b0:	9500      	ld.w      	r0, (r5, 0)
    32b2:	6819      	andn      	r0, r6
    32b4:	36cc      	movi      	r6, 204
    32b6:	46cb      	lsli      	r6, r6, 11
    GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFF00F)  | 0x00000770;            //PA1.1->SDA, PA1.2->SCL   
    32b8:	6c18      	or      	r0, r6
    32ba:	b500      	st.w      	r0, (r5, 0)
    32bc:	07d6      	br      	0x3268	// 3268 <I2C_Slave_Init+0x1a>
    else if(I2C_IO==I2C_G2)
    32be:	3842      	cmpnei      	r0, 2
    32c0:	0bd4      	bt      	0x3268	// 3268 <I2C_Slave_Init+0x1a>
    GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFF00F)  | 0x00000770;            //PA1.1->SDA, PA1.2->SCL   
    32c2:	110f      	lrw      	r0, 0x2000004c	// 337c <I2C_AcknowledgeConfig+0x1c>
    32c4:	36ff      	movi      	r6, 255
    32c6:	90a0      	ld.w      	r5, (r0, 0)
    32c8:	46c4      	lsli      	r6, r6, 4
    32ca:	9500      	ld.w      	r0, (r5, 0)
    32cc:	6819      	andn      	r0, r6
    32ce:	36ee      	movi      	r6, 238
    32d0:	46c3      	lsli      	r6, r6, 3
    32d2:	07f3      	br      	0x32b8	// 32b8 <I2C_Slave_Init+0x6a>

000032d4 <I2C_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_Enable(void)
{
    I2C0->CR = I2C0->CR | I2C_ENABLE;
    32d4:	1168      	lrw      	r3, 0x20000008	// 3374 <I2C_AcknowledgeConfig+0x14>
    32d6:	9340      	ld.w      	r2, (r3, 0)
    32d8:	9278      	ld.w      	r3, (r2, 0x60)
    32da:	3ba8      	bseti      	r3, r3, 8
    32dc:	b278      	st.w      	r3, (r2, 0x60)
}
    32de:	783c      	rts

000032e0 <I2C_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_Disable(void)
{
    I2C0->CR = I2C0->CR | I2C_DISABLE;
    32e0:	1165      	lrw      	r3, 0x20000008	// 3374 <I2C_AcknowledgeConfig+0x14>
    32e2:	9360      	ld.w      	r3, (r3, 0)
    32e4:	9358      	ld.w      	r2, (r3, 0x60)
    32e6:	b358      	st.w      	r2, (r3, 0x60)
}
    32e8:	783c      	rts

000032ea <I2C_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_Int_Enable(void)
{
    I2C0->CR = I2C0->CR & (~I2C_SI);					//clear I2C INT status
    32ea:	1163      	lrw      	r3, 0x20000008	// 3374 <I2C_AcknowledgeConfig+0x14>
    32ec:	9340      	ld.w      	r2, (r3, 0)
    32ee:	9278      	ld.w      	r3, (r2, 0x60)
    32f0:	3b84      	bclri      	r3, r3, 4
    32f2:	b278      	st.w      	r3, (r2, 0x60)
	INTC_ISER_WRITE(I2C_INT);                             //Enable I2C interrupt
    32f4:	3280      	movi      	r2, 128
    32f6:	1163      	lrw      	r3, 0x20000064	// 3380 <I2C_AcknowledgeConfig+0x20>
    32f8:	424a      	lsli      	r2, r2, 10
    32fa:	9360      	ld.w      	r3, (r3, 0)
    32fc:	23ff      	addi      	r3, 256
    32fe:	b340      	st.w      	r2, (r3, 0)
}
    3300:	783c      	rts

00003302 <I2C_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_Int_Disable(void)
{
    INTC_ICER_WRITE(I2C_INT);                             //Disable I2C interrupt
    3302:	1160      	lrw      	r3, 0x20000064	// 3380 <I2C_AcknowledgeConfig+0x20>
    3304:	32c0      	movi      	r2, 192
    3306:	9360      	ld.w      	r3, (r3, 0)
    3308:	4241      	lsli      	r2, r2, 1
    330a:	60c8      	addu      	r3, r2
    330c:	3280      	movi      	r2, 128
    330e:	424a      	lsli      	r2, r2, 10
    3310:	b340      	st.w      	r2, (r3, 0)
}
    3312:	783c      	rts

00003314 <I2C_WakeUp_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_WakeUp_Enable(void)
{
    INTC_IWER_WRITE(I2C_INT);                             //Enable I2C wake up
    3314:	107b      	lrw      	r3, 0x20000064	// 3380 <I2C_AcknowledgeConfig+0x20>
    3316:	3280      	movi      	r2, 128
    3318:	9360      	ld.w      	r3, (r3, 0)
    331a:	23ff      	addi      	r3, 256
    331c:	424a      	lsli      	r2, r2, 10
    331e:	b350      	st.w      	r2, (r3, 0x40)
}
    3320:	783c      	rts

00003322 <I2C_WakeUp_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_WakeUp_Disable(void)
{
    INTC_IWDR_WRITE(I2C_INT);                             //Disable I2C wake up
    3322:	1078      	lrw      	r3, 0x20000064	// 3380 <I2C_AcknowledgeConfig+0x20>
    3324:	32e0      	movi      	r2, 224
    3326:	9360      	ld.w      	r3, (r3, 0)
    3328:	4241      	lsli      	r2, r2, 1
    332a:	60c8      	addu      	r3, r2
    332c:	3280      	movi      	r2, 128
    332e:	424a      	lsli      	r2, r2, 10
    3330:	b340      	st.w      	r2, (r3, 0)
}
    3332:	783c      	rts

00003334 <I2C_GenerateSTART>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_GenerateSTART(void)
{
    I2C0->CR = I2C0->CR | I2C_STA;
    3334:	1070      	lrw      	r3, 0x20000008	// 3374 <I2C_AcknowledgeConfig+0x14>
    3336:	9340      	ld.w      	r2, (r3, 0)
    3338:	9278      	ld.w      	r3, (r2, 0x60)
    333a:	3ba3      	bseti      	r3, r3, 3
    333c:	b278      	st.w      	r3, (r2, 0x60)
}
    333e:	783c      	rts

00003340 <I2C_GenerateSTOP>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_GenerateSTOP(void)
{
    I2C0->CR = I2C0->CR | I2C_STO;
    3340:	106d      	lrw      	r3, 0x20000008	// 3374 <I2C_AcknowledgeConfig+0x14>
    3342:	9340      	ld.w      	r2, (r3, 0)
    3344:	9278      	ld.w      	r3, (r2, 0x60)
    3346:	3ba2      	bseti      	r3, r3, 2
    3348:	b278      	st.w      	r3, (r2, 0x60)
}
    334a:	783c      	rts

0000334c <I2C_SoftwareResetCmd>:
//I2C ENABLE/DISABLE software reset
//EntryParameter:SWRST_EN/SWRST_DIS
//ReturnValue:NONE
/*************************************************************/
void I2C_SoftwareResetCmd(I2C_EN_DIS_TypeDef EN_DIS)
{
    334c:	106a      	lrw      	r3, 0x20000008	// 3374 <I2C_AcknowledgeConfig+0x14>
  if (EN_DIS==SWRST_DIS)
    334e:	3840      	cmpnei      	r0, 0
  {
    I2C0->CR |= I2C_SWRST;
    3350:	9340      	ld.w      	r2, (r3, 0)
    3352:	9278      	ld.w      	r3, (r2, 0x60)
  if (EN_DIS==SWRST_DIS)
    3354:	0804      	bt      	0x335c	// 335c <I2C_SoftwareResetCmd+0x10>
    I2C0->CR |= I2C_SWRST;
    3356:	3ba0      	bseti      	r3, r3, 0
  }
  else
  {
    I2C0->CR &= (~I2C_SWRST);
    3358:	b278      	st.w      	r3, (r2, 0x60)
  }
}
    335a:	783c      	rts
    I2C0->CR &= (~I2C_SWRST);
    335c:	3b80      	bclri      	r3, r3, 0
    335e:	07fd      	br      	0x3358	// 3358 <I2C_SoftwareResetCmd+0xc>

00003360 <I2C_AcknowledgeConfig>:
//ReturnValue:NONE
/*************************************************************/
void I2C_AcknowledgeConfig(I2C_Ack_TypeDef Ack)
{

  if (Ack == I2C_ACK_NONE)
    3360:	3840      	cmpnei      	r0, 0
    3362:	1065      	lrw      	r3, 0x20000008	// 3374 <I2C_AcknowledgeConfig+0x14>
    3364:	0810      	bt      	0x3384	// 3384 <I2C_AcknowledgeConfig+0x24>
  {
    /* Disable the acknowledgement */
    I2C0->CR &= I2C_AA_NO;
    3366:	9360      	ld.w      	r3, (r3, 0)
    3368:	9358      	ld.w      	r2, (r3, 0x60)
    336a:	3200      	movi      	r2, 0
    336c:	b358      	st.w      	r2, (r3, 0x60)
  else
  {
    /* Enable the acknowledgement */
    I2C0->CR |= I2C_AA;
  }
}
    336e:	783c      	rts
    3370:	20000050 	.long	0x20000050
    3374:	20000008 	.long	0x20000008
    3378:	20000181 	.long	0x20000181
    337c:	2000004c 	.long	0x2000004c
    3380:	20000064 	.long	0x20000064
    I2C0->CR |= I2C_AA;
    3384:	9340      	ld.w      	r2, (r3, 0)
    3386:	9278      	ld.w      	r3, (r2, 0x60)
    3388:	3ba1      	bseti      	r3, r3, 1
    338a:	b278      	st.w      	r3, (r2, 0x60)
}
    338c:	07f1      	br      	0x336e	// 336e <I2C_AcknowledgeConfig+0xe>

0000338e <I2C_ReceiveData>:
//ReturnValue:I2C0->DAT
/*************************************************************/
U8_T I2C_ReceiveData(void)
{
  /* Return the data present in the DR register */
  return I2C0->DAT;
    338e:	1361      	lrw      	r3, 0x20000008	// 3510 <I2C_ReadByte+0x34>
    3390:	9360      	ld.w      	r3, (r3, 0)
    3392:	237f      	addi      	r3, 128
    3394:	9300      	ld.w      	r0, (r3, 0)
    3396:	7400      	zextb      	r0, r0
}
    3398:	783c      	rts

0000339a <I2C_SendData>:
//ReturnValue:NONE
/*************************************************************/
void I2C_SendData(uint8_t Data)
{
  /* Write in the DR register the data to be sent */
  I2C0->DAT = Data;
    339a:	127e      	lrw      	r3, 0x20000008	// 3510 <I2C_ReadByte+0x34>
    339c:	9360      	ld.w      	r3, (r3, 0)
    339e:	237f      	addi      	r3, 128
    33a0:	b300      	st.w      	r0, (r3, 0)
}
    33a2:	783c      	rts

000033a4 <I2C_Send7bitAddress>:
void I2C_Send7bitAddress(uint8_t Address, I2C_Direction_TypeDef Direction)
{
  /* Clear bit0 (direction) just in case */
  Address &= 0xFE;
  /* Send the Address + Direction */
  I2C0->DAT= Address | Direction;
    33a4:	127b      	lrw      	r3, 0x20000008	// 3510 <I2C_ReadByte+0x34>
  Address &= 0xFE;
    33a6:	3880      	bclri      	r0, r0, 0
  I2C0->DAT= Address | Direction;
    33a8:	9360      	ld.w      	r3, (r3, 0)
    33aa:	6c40      	or      	r1, r0
    33ac:	237f      	addi      	r3, 128
    33ae:	b320      	st.w      	r1, (r3, 0)
}
    33b0:	783c      	rts

000033b2 <I2C_WriteByte>:
//I2C Write byte
//EntryParameter:U8_T addr ,U8_T data
//ReturnValue:NONE
/*************************************************************/
void I2C_WriteByte(U8_T addr, U8_T data)
{
    33b2:	14c2      	push      	r4-r5
	// Write Byte
	I2C0->CR = I2C0->CR | I2C_STA;
    33b4:	1277      	lrw      	r3, 0x20000008	// 3510 <I2C_ReadByte+0x34>
	while((CSP_I2C_GET_SR(I2C0) & I2C_MTX_START) != I2C_MTX_START );
    33b6:	3408      	movi      	r4, 8
	I2C0->CR = I2C0->CR | I2C_STA;
    33b8:	9360      	ld.w      	r3, (r3, 0)
    33ba:	9358      	ld.w      	r2, (r3, 0x60)
    33bc:	3aa3      	bseti      	r2, r2, 3
    33be:	b358      	st.w      	r2, (r3, 0x60)
	while((CSP_I2C_GET_SR(I2C0) & I2C_MTX_START) != I2C_MTX_START );
    33c0:	935c      	ld.w      	r2, (r3, 0x70)
    33c2:	6890      	and      	r2, r4
    33c4:	3a40      	cmpnei      	r2, 0
    33c6:	0ffd      	bf      	0x33c0	// 33c0 <I2C_WriteByte+0xe>
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    33c8:	3410      	movi      	r4, 16
    33ca:	9358      	ld.w      	r2, (r3, 0x60)
    33cc:	6890      	and      	r2, r4
    33ce:	3a40      	cmpnei      	r2, 0
    33d0:	0ffd      	bf      	0x33ca	// 33ca <I2C_WriteByte+0x18>

	I2C0->CR = I2C0->CR & (~I2C_SI);
    33d2:	9358      	ld.w      	r2, (r3, 0x60)
    33d4:	3a84      	bclri      	r2, r2, 4
    33d6:	b358      	st.w      	r2, (r3, 0x60)
	I2C0->DAT = I2C_Address<<1;//0xA2;									// Device ID, Write
    33d8:	3280      	movi      	r2, 128
    33da:	608c      	addu      	r2, r3
    33dc:	34ac      	movi      	r4, 172
    33de:	b280      	st.w      	r4, (r2, 0)
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    33e0:	3510      	movi      	r5, 16
    33e2:	9398      	ld.w      	r4, (r3, 0x60)
    33e4:	6914      	and      	r4, r5
    33e6:	3c40      	cmpnei      	r4, 0
    33e8:	0ffd      	bf      	0x33e2	// 33e2 <I2C_WriteByte+0x30>

	I2C0->CR = I2C0->CR & (~I2C_SI);
    33ea:	9398      	ld.w      	r4, (r3, 0x60)
    33ec:	3c84      	bclri      	r4, r4, 4
    33ee:	b398      	st.w      	r4, (r3, 0x60)
	I2C0->DAT = addr;									// Address
    33f0:	b200      	st.w      	r0, (r2, 0)
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    33f2:	3410      	movi      	r4, 16
    33f4:	9318      	ld.w      	r0, (r3, 0x60)
    33f6:	6810      	and      	r0, r4
    33f8:	3840      	cmpnei      	r0, 0
    33fa:	0ffd      	bf      	0x33f4	// 33f4 <I2C_WriteByte+0x42>

	I2C0->CR = I2C0->CR & (~I2C_SI);
    33fc:	9318      	ld.w      	r0, (r3, 0x60)
    33fe:	3884      	bclri      	r0, r0, 4
    3400:	b318      	st.w      	r0, (r3, 0x60)
	I2C0->DAT = data;								// Data
    3402:	b220      	st.w      	r1, (r2, 0)
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    3404:	3110      	movi      	r1, 16
    3406:	9358      	ld.w      	r2, (r3, 0x60)
    3408:	6884      	and      	r2, r1
    340a:	3a40      	cmpnei      	r2, 0
    340c:	0ffd      	bf      	0x3406	// 3406 <I2C_WriteByte+0x54>
	I2C0->CR = I2C0->CR & (~I2C_SI);
    340e:	9358      	ld.w      	r2, (r3, 0x60)
    3410:	3a84      	bclri      	r2, r2, 4
    3412:	b358      	st.w      	r2, (r3, 0x60)
                
	I2C0->CR = I2C0->CR | I2C_STO;
    3414:	9358      	ld.w      	r2, (r3, 0x60)
    3416:	3aa2      	bseti      	r2, r2, 2
    3418:	b358      	st.w      	r2, (r3, 0x60)
}
    341a:	1482      	pop      	r4-r5

0000341c <I2C_Write_More_Byte>:
//I2C Write MORE byte
//EntryParameter:U8_T addr ,U8_T data,NumByteToWrite(defined by slave )
//ReturnValue:NONE
/*************************************************************/
void I2C_Write_More_Byte(U8_T addr, U8_T *data,U8_T NumByteToWrite)
{
    341c:	14c3      	push      	r4-r6
// Write Byte
	I2C0->CR = I2C0->CR | I2C_STA;
    341e:	117d      	lrw      	r3, 0x20000008	// 3510 <I2C_ReadByte+0x34>
	while((CSP_I2C_GET_SR(I2C0) & I2C_MTX_START) != I2C_MTX_START );
    3420:	3508      	movi      	r5, 8
	I2C0->CR = I2C0->CR | I2C_STA;
    3422:	9360      	ld.w      	r3, (r3, 0)
    3424:	9398      	ld.w      	r4, (r3, 0x60)
    3426:	3ca3      	bseti      	r4, r4, 3
    3428:	b398      	st.w      	r4, (r3, 0x60)
	while((CSP_I2C_GET_SR(I2C0) & I2C_MTX_START) != I2C_MTX_START );
    342a:	939c      	ld.w      	r4, (r3, 0x70)
    342c:	6914      	and      	r4, r5
    342e:	3c40      	cmpnei      	r4, 0
    3430:	0ffd      	bf      	0x342a	// 342a <I2C_Write_More_Byte+0xe>
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    3432:	3510      	movi      	r5, 16
    3434:	9398      	ld.w      	r4, (r3, 0x60)
    3436:	6914      	and      	r4, r5
    3438:	3c40      	cmpnei      	r4, 0
    343a:	0ffd      	bf      	0x3434	// 3434 <I2C_Write_More_Byte+0x18>

	I2C0->CR = I2C0->CR & (~I2C_SI);
    343c:	9398      	ld.w      	r4, (r3, 0x60)
    343e:	3c84      	bclri      	r4, r4, 4
    3440:	b398      	st.w      	r4, (r3, 0x60)
	I2C0->DAT = I2C_Address<<1;//0xA2;									// Device ID, Write
    3442:	3480      	movi      	r4, 128
    3444:	610c      	addu      	r4, r3
    3446:	35ac      	movi      	r5, 172
    3448:	b4a0      	st.w      	r5, (r4, 0)
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    344a:	3610      	movi      	r6, 16
    344c:	93b8      	ld.w      	r5, (r3, 0x60)
    344e:	6958      	and      	r5, r6
    3450:	3d40      	cmpnei      	r5, 0
    3452:	0ffd      	bf      	0x344c	// 344c <I2C_Write_More_Byte+0x30>

	I2C0->CR = I2C0->CR & (~I2C_SI);
    3454:	93b8      	ld.w      	r5, (r3, 0x60)
    3456:	3d84      	bclri      	r5, r5, 4
    3458:	b3b8      	st.w      	r5, (r3, 0x60)
	I2C0->DAT = addr;									// Address
    345a:	b400      	st.w      	r0, (r4, 0)
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    345c:	3510      	movi      	r5, 16
    345e:	9318      	ld.w      	r0, (r3, 0x60)
    3460:	6814      	and      	r0, r5
    3462:	3840      	cmpnei      	r0, 0
    3464:	0ffd      	bf      	0x345e	// 345e <I2C_Write_More_Byte+0x42>
	I2C0->CR = I2C0->CR & (~I2C_SI);
    3466:	9318      	ld.w      	r0, (r3, 0x60)
    3468:	3884      	bclri      	r0, r0, 4
    346a:	b318      	st.w      	r0, (r3, 0x60)
	while(NumByteToWrite!=0)
    346c:	3a40      	cmpnei      	r2, 0
    346e:	080d      	bt      	0x3488	// 3488 <I2C_Write_More_Byte+0x6c>
		
	I2C0->DAT = *data;
	data++;// Data
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    3470:	3110      	movi      	r1, 16
    3472:	9358      	ld.w      	r2, (r3, 0x60)
    3474:	6884      	and      	r2, r1
    3476:	3a40      	cmpnei      	r2, 0
    3478:	0ffd      	bf      	0x3472	// 3472 <I2C_Write_More_Byte+0x56>
	I2C0->CR = I2C0->CR & (~I2C_SI);
    347a:	9358      	ld.w      	r2, (r3, 0x60)
    347c:	3a84      	bclri      	r2, r2, 4
    347e:	b358      	st.w      	r2, (r3, 0x60)
	NumByteToWrite--;               
	I2C0->CR = I2C0->CR | I2C_STO;
    3480:	9358      	ld.w      	r2, (r3, 0x60)
    3482:	3aa2      	bseti      	r2, r2, 2
    3484:	b358      	st.w      	r2, (r3, 0x60)
}
    3486:	1483      	pop      	r4-r6
	I2C0->DAT = *data;
    3488:	8100      	ld.b      	r0, (r1, 0)
    348a:	b400      	st.w      	r0, (r4, 0)
    348c:	07f0      	br      	0x346c	// 346c <I2C_Write_More_Byte+0x50>

0000348e <I2C_WriteByte_Int>:
//I2C Write byte in interruption
//EntryParameter:U8_T addr ,U8_T data
//ReturnValue:NONE
/*************************************************************/
void I2C_WriteByte_Int(U8_T addr, U8_T data)
{
    348e:	14c2      	push      	r4-r5

	I2C_INTFlag=0;
    3490:	3200      	movi      	r2, 0
    3492:	1161      	lrw      	r3, 0x20000080	// 3514 <I2C_ReadByte+0x38>
    3494:	a340      	st.b      	r2, (r3, 0)

// Write Byte
	I2C0->CR = I2C0->CR | I2C_STA;
    3496:	105f      	lrw      	r2, 0x20000008	// 3510 <I2C_ReadByte+0x34>
    3498:	9280      	ld.w      	r4, (r2, 0)
    349a:	9458      	ld.w      	r2, (r4, 0x60)
    349c:	3aa3      	bseti      	r2, r2, 3
    349e:	b458      	st.w      	r2, (r4, 0x60)
//	while((CSP_I2C_GET_SR(I2C0) & I2C_MTX_START) != I2C_MTX_START );
	while(I2C_INTFlag!=1);
    34a0:	8340      	ld.b      	r2, (r3, 0)
    34a2:	3a41      	cmpnei      	r2, 1
    34a4:	0bfe      	bt      	0x34a0	// 34a0 <I2C_WriteByte_Int+0x12>
	I2C_INTFlag=0;
    34a6:	3200      	movi      	r2, 0
    34a8:	a340      	st.b      	r2, (r3, 0)

//	I2C0->CR = I2C0->CR & (~I2C_SI);
	I2C0->DAT = I2C_Address<<1;//0xA2;									// Device ID, Write
    34aa:	3280      	movi      	r2, 128
    34ac:	6090      	addu      	r2, r4
    34ae:	35ac      	movi      	r5, 172
    34b0:	b2a0      	st.w      	r5, (r2, 0)
	while(!I2C_INTFlag);
    34b2:	83a0      	ld.b      	r5, (r3, 0)
    34b4:	3d40      	cmpnei      	r5, 0
    34b6:	0ffe      	bf      	0x34b2	// 34b2 <I2C_WriteByte_Int+0x24>
	I2C_INTFlag=0;
    34b8:	3500      	movi      	r5, 0
    34ba:	a3a0      	st.b      	r5, (r3, 0)

//	I2C0->CR = I2C0->CR & (~I2C_SI);
	I2C0->DAT = addr;									// Address
    34bc:	b200      	st.w      	r0, (r2, 0)
	while(!I2C_INTFlag);
    34be:	8300      	ld.b      	r0, (r3, 0)
    34c0:	3840      	cmpnei      	r0, 0
    34c2:	0ffe      	bf      	0x34be	// 34be <I2C_WriteByte_Int+0x30>
	I2C_INTFlag=0;
    34c4:	3000      	movi      	r0, 0
    34c6:	a300      	st.b      	r0, (r3, 0)

//	I2C0->CR = I2C0->CR & (~I2C_SI);
	I2C0->DAT = data;									// Data
    34c8:	b220      	st.w      	r1, (r2, 0)
	while(!I2C_INTFlag);
    34ca:	8340      	ld.b      	r2, (r3, 0)
    34cc:	3a40      	cmpnei      	r2, 0
    34ce:	0ffe      	bf      	0x34ca	// 34ca <I2C_WriteByte_Int+0x3c>
	I2C_INTFlag=0;
    34d0:	3200      	movi      	r2, 0
    34d2:	a340      	st.b      	r2, (r3, 0)

//	I2C0->CR = I2C0->CR & (~I2C_SI);
	I2C0->CR = I2C0->CR | I2C_STO;
    34d4:	9478      	ld.w      	r3, (r4, 0x60)
    34d6:	3ba2      	bseti      	r3, r3, 2
    34d8:	b478      	st.w      	r3, (r4, 0x60)
}
    34da:	1482      	pop      	r4-r5

000034dc <I2C_ReadByte>:
//I2C Read byte
//EntryParameter:U8_T addr
//ReturnValue:I2C0->DAT
/*************************************************************/
U8_T I2C_ReadByte(U8_T addr)
{
    34dc:	14c1      	push      	r4

	// Verify
	I2C0->CR = I2C0->CR | I2C_STA;
    34de:	106d      	lrw      	r3, 0x20000008	// 3510 <I2C_ReadByte+0x34>
	while((CSP_I2C_GET_SR(I2C0) & I2C_MTX_START) != I2C_MTX_START );
    34e0:	3108      	movi      	r1, 8
	I2C0->CR = I2C0->CR | I2C_STA;
    34e2:	9360      	ld.w      	r3, (r3, 0)
    34e4:	9358      	ld.w      	r2, (r3, 0x60)
    34e6:	3aa3      	bseti      	r2, r2, 3
    34e8:	b358      	st.w      	r2, (r3, 0x60)
	while((CSP_I2C_GET_SR(I2C0) & I2C_MTX_START) != I2C_MTX_START );
    34ea:	935c      	ld.w      	r2, (r3, 0x70)
    34ec:	6884      	and      	r2, r1
    34ee:	3a40      	cmpnei      	r2, 0
    34f0:	0ffd      	bf      	0x34ea	// 34ea <I2C_ReadByte+0xe>
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    34f2:	3110      	movi      	r1, 16
    34f4:	9358      	ld.w      	r2, (r3, 0x60)
    34f6:	6884      	and      	r2, r1
    34f8:	3a40      	cmpnei      	r2, 0
    34fa:	0ffd      	bf      	0x34f4	// 34f4 <I2C_ReadByte+0x18>
	I2C0->CR = I2C0->CR & (~I2C_SI);
    34fc:	9358      	ld.w      	r2, (r3, 0x60)
    34fe:	3a84      	bclri      	r2, r2, 4

	I2C0->DAT = I2C_Address<<1;//0xA2;									// Device ID, Write
    3500:	3180      	movi      	r1, 128
	I2C0->CR = I2C0->CR & (~I2C_SI);
    3502:	b358      	st.w      	r2, (r3, 0x60)
	I2C0->DAT = I2C_Address<<1;//0xA2;									// Device ID, Write
    3504:	604c      	addu      	r1, r3
    3506:	32ac      	movi      	r2, 172
    3508:	b140      	st.w      	r2, (r1, 0)
//	I2C0->CR = I2C0->CR & (~I2C_SI);
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    350a:	3410      	movi      	r4, 16
    350c:	0406      	br      	0x3518	// 3518 <I2C_ReadByte+0x3c>
    350e:	0000      	bkpt
    3510:	20000008 	.long	0x20000008
    3514:	20000080 	.long	0x20000080
    3518:	9358      	ld.w      	r2, (r3, 0x60)
    351a:	6890      	and      	r2, r4
    351c:	3a40      	cmpnei      	r2, 0
    351e:	0ffd      	bf      	0x3518	// 3518 <I2C_ReadByte+0x3c>

	I2C0->DAT = addr;									// Address
    3520:	b100      	st.w      	r0, (r1, 0)
	I2C0->CR = (I2C0->CR & (~I2C_SI));
    3522:	9358      	ld.w      	r2, (r3, 0x60)
    3524:	3a84      	bclri      	r2, r2, 4
    3526:	b358      	st.w      	r2, (r3, 0x60)
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    3528:	3010      	movi      	r0, 16
    352a:	9358      	ld.w      	r2, (r3, 0x60)
    352c:	6880      	and      	r2, r0
    352e:	3a40      	cmpnei      	r2, 0
    3530:	0ffd      	bf      	0x352a	// 352a <I2C_ReadByte+0x4e>


	I2C0->CR = (I2C0->CR & (~I2C_SI)) | I2C_STA;		// re-start
    3532:	9358      	ld.w      	r2, (r3, 0x60)
    3534:	3a83      	bclri      	r2, r2, 3
    3536:	3a84      	bclri      	r2, r2, 4
    3538:	3aa3      	bseti      	r2, r2, 3
    353a:	b358      	st.w      	r2, (r3, 0x60)
//	while((CSP_I2C_GET_SR(I2C0) & I2C_MTX_START) != I2C_MTX_START );
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    353c:	3010      	movi      	r0, 16
    353e:	9358      	ld.w      	r2, (r3, 0x60)
    3540:	6880      	and      	r2, r0
    3542:	3a40      	cmpnei      	r2, 0
    3544:	0ffd      	bf      	0x353e	// 353e <I2C_ReadByte+0x62>


	I2C0->DAT = (I2C_Address<<1)+1;//0xA3;									// Device ID, Read
    3546:	32ad      	movi      	r2, 173
    3548:	b140      	st.w      	r2, (r1, 0)
	I2C0->CR = I2C0->CR & (~I2C_SI);
    354a:	9358      	ld.w      	r2, (r3, 0x60)
    354c:	3a84      	bclri      	r2, r2, 4
    354e:	b358      	st.w      	r2, (r3, 0x60)
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    3550:	3010      	movi      	r0, 16
    3552:	9358      	ld.w      	r2, (r3, 0x60)
    3554:	6880      	and      	r2, r0
    3556:	3a40      	cmpnei      	r2, 0
    3558:	0ffd      	bf      	0x3552	// 3552 <I2C_ReadByte+0x76>

	I2C0->CR = (I2C0->CR & (~I2C_SI));
    355a:	9358      	ld.w      	r2, (r3, 0x60)
    355c:	3a84      	bclri      	r2, r2, 4
    355e:	b358      	st.w      	r2, (r3, 0x60)
	while((CSP_I2C_GET_CR(I2C0) & I2C_SI) != I2C_SI);
    3560:	3010      	movi      	r0, 16
    3562:	9358      	ld.w      	r2, (r3, 0x60)
    3564:	6880      	and      	r2, r0
    3566:	3a40      	cmpnei      	r2, 0
    3568:	0ffd      	bf      	0x3562	// 3562 <I2C_ReadByte+0x86>

	I2C0->CR = (I2C0->CR & (~I2C_SI)) | I2C_STO;
    356a:	9358      	ld.w      	r2, (r3, 0x60)
    356c:	3a82      	bclri      	r2, r2, 2
    356e:	3a84      	bclri      	r2, r2, 4
    3570:	3aa2      	bseti      	r2, r2, 2
    3572:	b358      	st.w      	r2, (r3, 0x60)

	return I2C0->DAT;
    3574:	9100      	ld.w      	r0, (r1, 0)
    3576:	7400      	zextb      	r0, r0
}
    3578:	1481      	pop      	r4

0000357a <I2C_ReadByte_Int>:
//I2C Read byte in interruption
//EntryParameter:U8_T addr
//ReturnValue:i2c_received_data
/*************************************************************/
U8_T I2C_ReadByte_Int(U8_T addr)
{
    357a:	14c1      	push      	r4

	I2C_INTFlag=0;
    357c:	3200      	movi      	r2, 0
    357e:	1363      	lrw      	r3, 0x20000080	// 3708 <I2C_Slave_Receive+0x124>
    3580:	a340      	st.b      	r2, (r3, 0)
	U8_T i2c_received_data;

	// Verify
	I2C0->CR = I2C0->CR | I2C_STA;
    3582:	1343      	lrw      	r2, 0x20000008	// 370c <I2C_Slave_Receive+0x128>
    3584:	9240      	ld.w      	r2, (r2, 0)
    3586:	9238      	ld.w      	r1, (r2, 0x60)
    3588:	39a3      	bseti      	r1, r1, 3
    358a:	b238      	st.w      	r1, (r2, 0x60)
//	while((CSP_I2C_GET_SR(I2C0) & I2C_MTX_START) != I2C_MTX_START );
	while(!I2C_INTFlag);
    358c:	8320      	ld.b      	r1, (r3, 0)
    358e:	3940      	cmpnei      	r1, 0
    3590:	0ffe      	bf      	0x358c	// 358c <I2C_ReadByte_Int+0x12>

	I2C0->DAT = I2C_Address<<1;//0xA2;									// Device ID, Write
    3592:	3180      	movi      	r1, 128
    3594:	34ac      	movi      	r4, 172
    3596:	6048      	addu      	r1, r2
    3598:	b180      	st.w      	r4, (r1, 0)
	I2C_INTFlag=0;
    359a:	3400      	movi      	r4, 0
    359c:	a380      	st.b      	r4, (r3, 0)
	while(!I2C_INTFlag);
    359e:	8380      	ld.b      	r4, (r3, 0)
    35a0:	3c40      	cmpnei      	r4, 0
    35a2:	0ffe      	bf      	0x359e	// 359e <I2C_ReadByte_Int+0x24>

	I2C0->DAT = addr;									// Address
    35a4:	b100      	st.w      	r0, (r1, 0)
	I2C_INTFlag=0;
    35a6:	3000      	movi      	r0, 0
    35a8:	a300      	st.b      	r0, (r3, 0)
	restart=1;
    35aa:	3401      	movi      	r4, 1
    35ac:	1219      	lrw      	r0, 0x20000184	// 3710 <I2C_Slave_Receive+0x12c>
    35ae:	a080      	st.b      	r4, (r0, 0)
	while(!I2C_INTFlag);
    35b0:	8300      	ld.b      	r0, (r3, 0)
    35b2:	3840      	cmpnei      	r0, 0
    35b4:	0ffe      	bf      	0x35b0	// 35b0 <I2C_ReadByte_Int+0x36>

//	I2C0->CR = I2C0->CR | I2C_STA;						// re-start
	I2C_INTFlag=0;
    35b6:	3000      	movi      	r0, 0
    35b8:	a300      	st.b      	r0, (r3, 0)
	while(!I2C_INTFlag);
    35ba:	8300      	ld.b      	r0, (r3, 0)
    35bc:	3840      	cmpnei      	r0, 0
    35be:	0ffe      	bf      	0x35ba	// 35ba <I2C_ReadByte_Int+0x40>

	I2C0->DAT = (I2C_Address<<1)+1;//0xA3;									// Device ID, Read
    35c0:	30ad      	movi      	r0, 173
    35c2:	b100      	st.w      	r0, (r1, 0)
	I2C_INTFlag=0;
    35c4:	3000      	movi      	r0, 0
    35c6:	a300      	st.b      	r0, (r3, 0)
	while(!I2C_INTFlag);
    35c8:	8300      	ld.b      	r0, (r3, 0)
    35ca:	3840      	cmpnei      	r0, 0
    35cc:	0ffe      	bf      	0x35c8	// 35c8 <I2C_ReadByte_Int+0x4e>

	I2C_INTFlag=0;
    35ce:	3000      	movi      	r0, 0
    35d0:	a300      	st.b      	r0, (r3, 0)
	while(!I2C_INTFlag);
    35d2:	8300      	ld.b      	r0, (r3, 0)
    35d4:	3840      	cmpnei      	r0, 0
    35d6:	0ffe      	bf      	0x35d2	// 35d2 <I2C_ReadByte_Int+0x58>

	i2c_received_data = I2C0->DAT;
    35d8:	9100      	ld.w      	r0, (r1, 0)

	I2C0->CR = I2C0->CR | I2C_STO;
    35da:	9278      	ld.w      	r3, (r2, 0x60)
    35dc:	3ba2      	bseti      	r3, r3, 2

//	return I2C0->DAT;
	return i2c_received_data;
    35de:	7400      	zextb      	r0, r0
	I2C0->CR = I2C0->CR | I2C_STO;
    35e0:	b278      	st.w      	r3, (r2, 0x60)
}
    35e2:	1481      	pop      	r4

000035e4 <I2C_Slave_Receive>:
//I2C slave Receive
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_Slave_Receive(void)
{
    35e4:	14d1      	push      	r4, r15
    uint8_t SR_Value;
	SR_Value=I2C0->SR;
    35e6:	120a      	lrw      	r0, 0x20000008	// 370c <I2C_Slave_Receive+0x128>
    switch(SR_Value)
    35e8:	31a0      	movi      	r1, 160
	SR_Value=I2C0->SR;
    35ea:	9060      	ld.w      	r3, (r0, 0)
    35ec:	935c      	ld.w      	r2, (r3, 0x70)
    switch(SR_Value)
    35ee:	7488      	zextb      	r2, r2
    35f0:	644a      	cmpne      	r2, r1
    35f2:	6d03      	mov      	r4, r0
    35f4:	0cac      	bf      	0x374c	// 374c <I2C_Slave_Receive+0x168>
    35f6:	6484      	cmphs      	r1, r2
    35f8:	0c32      	bf      	0x365c	// 365c <I2C_Slave_Receive+0x78>
    35fa:	3168      	movi      	r1, 104
    35fc:	644a      	cmpne      	r2, r1
    35fe:	0c6b      	bf      	0x36d4	// 36d4 <I2C_Slave_Receive+0xf0>
    3600:	6484      	cmphs      	r1, r2
    3602:	0c0b      	bf      	0x3618	// 3618 <I2C_Slave_Receive+0x34>
    3604:	3160      	movi      	r1, 96
    3606:	644a      	cmpne      	r2, r1
    3608:	0c66      	bf      	0x36d4	// 36d4 <I2C_Slave_Receive+0xf0>
		I2C0->CR = I2C0->CR & (~I2C_SI);
		I2CSlaveState = I2C_IDLE;
		break;

		default:
		I2C_SLAVE_CONFIG();                                     //if error，reset I2C
    360a:	e00008dc 	bsr      	0x47c2	// 47c2 <I2C_SLAVE_CONFIG>
		I2C0->CR = I2C0->CR & (~I2C_SI);
    360e:	9440      	ld.w      	r2, (r4, 0)
    3610:	9278      	ld.w      	r3, (r2, 0x60)
    3612:	3b84      	bclri      	r3, r3, 4
    3614:	b278      	st.w      	r3, (r2, 0x60)
    }
	return;
    3616:	046a      	br      	0x36ea	// 36ea <I2C_Slave_Receive+0x106>
    switch(SR_Value)
    3618:	3180      	movi      	r1, 128
    361a:	644a      	cmpne      	r2, r1
    361c:	0c04      	bf      	0x3624	// 3624 <I2C_Slave_Receive+0x40>
    361e:	3190      	movi      	r1, 144
    3620:	644a      	cmpne      	r2, r1
    3622:	0bf4      	bt      	0x360a	// 360a <I2C_Slave_Receive+0x26>
        if ( I2CSlaveState == I2C_WR_STARTED )
    3624:	113c      	lrw      	r1, 0x20000071	// 3714 <I2C_Slave_Receive+0x130>
    3626:	8141      	ld.b      	r2, (r1, 0x1)
    3628:	3a46      	cmpnei      	r2, 6
    362a:	0886      	bt      	0x3736	// 3736 <I2C_Slave_Receive+0x152>
			if(RdIndex==0)
    362c:	8140      	ld.b      	r2, (r1, 0)
    362e:	3a40      	cmpnei      	r2, 0
    3630:	115a      	lrw      	r2, 0x20000182	// 3718 <I2C_Slave_Receive+0x134>
    3632:	085d      	bt      	0x36ec	// 36ec <I2C_Slave_Receive+0x108>
				I2C_Data_Adress=I2C0->DAT;
    3634:	3080      	movi      	r0, 128
    3636:	600c      	addu      	r0, r3
    3638:	9000      	ld.w      	r0, (r0, 0)
    363a:	7400      	zextb      	r0, r0
    363c:	a200      	st.b      	r0, (r2, 0)
				I2C_St_Adress=I2C_Data_Adress;
    363e:	8240      	ld.b      	r2, (r2, 0)
    3640:	7488      	zextb      	r2, r2
    3642:	1117      	lrw      	r0, 0x20000081	// 371c <I2C_Slave_Receive+0x138>
    3644:	a040      	st.b      	r2, (r0, 0)
				RdIndex++;
    3646:	8140      	ld.b      	r2, (r1, 0)
    3648:	2200      	addi      	r2, 1
    364a:	7488      	zextb      	r2, r2
    364c:	a140      	st.b      	r2, (r1, 0)
				I2C0->CR = I2C0->CR | I2C_AA;
    364e:	9358      	ld.w      	r2, (r3, 0x60)
    3650:	3aa1      	bseti      	r2, r2, 1
             I2C0->CR = I2C0->CR | I2C_AA_NO;
    3652:	b358      	st.w      	r2, (r3, 0x60)
		I2C0->CR = I2C0->CR & (~I2C_SI);
    3654:	9358      	ld.w      	r2, (r3, 0x60)
    3656:	3a84      	bclri      	r2, r2, 4
    3658:	b358      	st.w      	r2, (r3, 0x60)
		break;
    365a:	0448      	br      	0x36ea	// 36ea <I2C_Slave_Receive+0x106>
    switch(SR_Value)
    365c:	31b8      	movi      	r1, 184
    365e:	644a      	cmpne      	r2, r1
    3660:	0c25      	bf      	0x36aa	// 36aa <I2C_Slave_Receive+0xc6>
    3662:	6484      	cmphs      	r1, r2
    3664:	0c1d      	bf      	0x369e	// 369e <I2C_Slave_Receive+0xba>
    3666:	31a8      	movi      	r1, 168
    3668:	644a      	cmpne      	r2, r1
    366a:	0c04      	bf      	0x3672	// 3672 <I2C_Slave_Receive+0x8e>
    366c:	31b0      	movi      	r1, 176
    366e:	644a      	cmpne      	r2, r1
    3670:	0bcd      	bt      	0x360a	// 360a <I2C_Slave_Receive+0x26>
		RdIndex=0;
    3672:	1149      	lrw      	r2, 0x20000071	// 3714 <I2C_Slave_Receive+0x130>
    3674:	3100      	movi      	r1, 0
    3676:	a220      	st.b      	r1, (r2, 0)
		I2CSlaveState = I2C_RD_STARTED;
    3678:	3107      	movi      	r1, 7
    367a:	a221      	st.b      	r1, (r2, 0x1)
		WrIndex = I2C_St_Adress;
    367c:	1128      	lrw      	r1, 0x20000081	// 371c <I2C_Slave_Receive+0x138>
    367e:	8120      	ld.b      	r1, (r1, 0)
    3680:	7444      	zextb      	r1, r1
    3682:	a222      	st.b      	r1, (r2, 0x2)
		if(WrIndex<BUFSIZE)
    3684:	8202      	ld.b      	r0, (r2, 0x2)
    3686:	31ff      	movi      	r1, 255
    3688:	6442      	cmpne      	r0, r1
    368a:	0fe2      	bf      	0x364e	// 364e <I2C_Slave_Receive+0x6a>
			I2C0->DAT= I2CWrBuffer[WrIndex];
    368c:	8242      	ld.b      	r2, (r2, 0x2)
    368e:	1125      	lrw      	r1, 0x20000082	// 3720 <I2C_Slave_Receive+0x13c>
    3690:	6084      	addu      	r2, r1
    3692:	8240      	ld.b      	r2, (r2, 0)
    3694:	3180      	movi      	r1, 128
    3696:	7488      	zextb      	r2, r2
    3698:	604c      	addu      	r1, r3
    369a:	b140      	st.w      	r2, (r1, 0)
    369c:	07d9      	br      	0x364e	// 364e <I2C_Slave_Receive+0x6a>
    switch(SR_Value)
    369e:	31c0      	movi      	r1, 192
    36a0:	644a      	cmpne      	r2, r1
    36a2:	0c4c      	bf      	0x373a	// 373a <I2C_Slave_Receive+0x156>
    36a4:	31c8      	movi      	r1, 200
    36a6:	644a      	cmpne      	r2, r1
    36a8:	0bb1      	bt      	0x360a	// 360a <I2C_Slave_Receive+0x26>
		if ( I2CSlaveState == I2C_RD_STARTED )
    36aa:	105b      	lrw      	r2, 0x20000071	// 3714 <I2C_Slave_Receive+0x130>
    36ac:	8221      	ld.b      	r1, (r2, 0x1)
    36ae:	3947      	cmpnei      	r1, 7
    36b0:	0843      	bt      	0x3736	// 3736 <I2C_Slave_Receive+0x152>
			if(WrIndex+1<BUFSIZE)
    36b2:	8202      	ld.b      	r0, (r2, 0x2)
    36b4:	31fd      	movi      	r1, 253
    36b6:	6405      	cmplt      	r1, r0
    36b8:	0809      	bt      	0x36ca	// 36ca <I2C_Slave_Receive+0xe6>
				 I2C0->DAT= I2CWrBuffer[WrIndex+1];
    36ba:	8222      	ld.b      	r1, (r2, 0x2)
    36bc:	101a      	lrw      	r0, 0x20000083	// 3724 <I2C_Slave_Receive+0x140>
    36be:	6040      	addu      	r1, r0
    36c0:	8120      	ld.b      	r1, (r1, 0)
    36c2:	3080      	movi      	r0, 128
    36c4:	7444      	zextb      	r1, r1
    36c6:	600c      	addu      	r0, r3
    36c8:	b020      	st.w      	r1, (r0, 0)
            WrIndex++;
    36ca:	8222      	ld.b      	r1, (r2, 0x2)
    36cc:	2100      	addi      	r1, 1
    36ce:	7444      	zextb      	r1, r1
    36d0:	a222      	st.b      	r1, (r2, 0x2)
    36d2:	07be      	br      	0x364e	// 364e <I2C_Slave_Receive+0x6a>
        RdIndex=0;
    36d4:	1030      	lrw      	r1, 0x20000071	// 3714 <I2C_Slave_Receive+0x130>
    36d6:	3200      	movi      	r2, 0
    36d8:	a140      	st.b      	r2, (r1, 0)
		I2C0->CR = I2C0->CR | I2C_AA;
    36da:	9358      	ld.w      	r2, (r3, 0x60)
    36dc:	3aa1      	bseti      	r2, r2, 1
    36de:	b358      	st.w      	r2, (r3, 0x60)
		I2C0->CR = I2C0->CR & (~I2C_SI);
    36e0:	9358      	ld.w      	r2, (r3, 0x60)
    36e2:	3a84      	bclri      	r2, r2, 4
    36e4:	b358      	st.w      	r2, (r3, 0x60)
        I2CSlaveState = I2C_WR_STARTED;
    36e6:	3306      	movi      	r3, 6
    36e8:	a161      	st.b      	r3, (r1, 0x1)
}
    36ea:	1491      	pop      	r4, r15
				if(I2C_Data_Adress<BUFSIZE)
    36ec:	8200      	ld.b      	r0, (r2, 0)
    36ee:	31ff      	movi      	r1, 255
    36f0:	6442      	cmpne      	r0, r1
    36f2:	0c1d      	bf      	0x372c	// 372c <I2C_Slave_Receive+0x148>
					I2CRdBuffer[I2C_Data_Adress]= I2C0->DAT;
    36f4:	3080      	movi      	r0, 128
    36f6:	600c      	addu      	r0, r3
    36f8:	8220      	ld.b      	r1, (r2, 0)
    36fa:	108c      	lrw      	r4, 0x20000185	// 3728 <I2C_Slave_Receive+0x144>
    36fc:	6050      	addu      	r1, r4
    36fe:	9000      	ld.w      	r0, (r0, 0)
    3700:	7400      	zextb      	r0, r0
    3702:	a100      	st.b      	r0, (r1, 0)
    3704:	0414      	br      	0x372c	// 372c <I2C_Slave_Receive+0x148>
    3706:	0000      	bkpt
    3708:	20000080 	.long	0x20000080
    370c:	20000008 	.long	0x20000008
    3710:	20000184 	.long	0x20000184
    3714:	20000071 	.long	0x20000071
    3718:	20000182 	.long	0x20000182
    371c:	20000081 	.long	0x20000081
    3720:	20000082 	.long	0x20000082
    3724:	20000083 	.long	0x20000083
    3728:	20000185 	.long	0x20000185
				I2C_Data_Adress++;
    372c:	8220      	ld.b      	r1, (r2, 0)
    372e:	2100      	addi      	r1, 1
    3730:	7444      	zextb      	r1, r1
    3732:	a220      	st.b      	r1, (r2, 0)
    3734:	078d      	br      	0x364e	// 364e <I2C_Slave_Receive+0x6a>
             I2C0->CR = I2C0->CR | I2C_AA_NO;
    3736:	9358      	ld.w      	r2, (r3, 0x60)
    3738:	078d      	br      	0x3652	// 3652 <I2C_Slave_Receive+0x6e>
		I2C0->CR = I2C0->CR | I2C_AA_NO;
    373a:	9358      	ld.w      	r2, (r3, 0x60)
    373c:	b358      	st.w      	r2, (r3, 0x60)
		I2C0->CR = I2C0->CR & (~I2C_SI);
    373e:	9358      	ld.w      	r2, (r3, 0x60)
    3740:	3a84      	bclri      	r2, r2, 4
    3742:	b358      	st.w      	r2, (r3, 0x60)
		I2CSlaveState = DATA_NACK;
    3744:	3205      	movi      	r2, 5
    3746:	1067      	lrw      	r3, 0x20000071	// 3760 <I2C_Slave_Receive+0x17c>
		I2CSlaveState = I2C_IDLE;
    3748:	a341      	st.b      	r2, (r3, 0x1)
		break;
    374a:	07d0      	br      	0x36ea	// 36ea <I2C_Slave_Receive+0x106>
		I2C0->CR = I2C0->CR | I2C_AA;
    374c:	9358      	ld.w      	r2, (r3, 0x60)
    374e:	3aa1      	bseti      	r2, r2, 1
    3750:	b358      	st.w      	r2, (r3, 0x60)
		I2C0->CR = I2C0->CR & (~I2C_SI);
    3752:	9358      	ld.w      	r2, (r3, 0x60)
    3754:	3a84      	bclri      	r2, r2, 4
    3756:	b358      	st.w      	r2, (r3, 0x60)
		I2CSlaveState = I2C_IDLE;
    3758:	3200      	movi      	r2, 0
    375a:	1062      	lrw      	r3, 0x20000071	// 3760 <I2C_Slave_Receive+0x17c>
    375c:	07f6      	br      	0x3748	// 3748 <I2C_Slave_Receive+0x164>
    375e:	0000      	bkpt
    3760:	20000071 	.long	0x20000071

00003764 <UART_DeInit>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART_DeInit(void)
{
    UART1->DATA = UART_RESET_VALUE;
    3764:	1065      	lrw      	r3, 0x20000010	// 3778 <UART_DeInit+0x14>
    3766:	3200      	movi      	r2, 0
    3768:	9360      	ld.w      	r3, (r3, 0)
    376a:	b340      	st.w      	r2, (r3, 0)
    UART1->SR   = UART_RESET_VALUE;
    376c:	b341      	st.w      	r2, (r3, 0x4)
    UART1->CTRL = UART_RESET_VALUE;
    376e:	b342      	st.w      	r2, (r3, 0x8)
    UART1->ISR  = UART_RESET_VALUE;
    3770:	b343      	st.w      	r2, (r3, 0xc)
    UART1->BRDIV =UART_RESET_VALUE;
    3772:	b344      	st.w      	r2, (r3, 0x10)
}
    3774:	783c      	rts
    3776:	0000      	bkpt
    3778:	20000010 	.long	0x20000010

0000377c <UART1_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_Int_Enable(void)
{
    UART1->ISR=0x0F;									//clear UART1 INT status
    377c:	1267      	lrw      	r3, 0x20000010	// 3898 <UARTReceive+0x32>
    377e:	320f      	movi      	r2, 15
    3780:	9360      	ld.w      	r3, (r3, 0)
    3782:	b343      	st.w      	r2, (r3, 0xc)
	INTC_ISER_WRITE(UART1_INT);							//INT Vector Enable UART0/1 Interrupt in CK802
    3784:	3280      	movi      	r2, 128
    3786:	1266      	lrw      	r3, 0x20000064	// 389c <UARTReceive+0x36>
    3788:	4247      	lsli      	r2, r2, 7
    378a:	9360      	ld.w      	r3, (r3, 0)
    378c:	23ff      	addi      	r3, 256
    378e:	b340      	st.w      	r2, (r3, 0)
}
    3790:	783c      	rts

00003792 <UART1_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_Int_Disable(void)
{
    INTC_ICER_WRITE(UART1_INT);							//INT Vector Enable UART0/1 Interrupt in CK802
    3792:	1263      	lrw      	r3, 0x20000064	// 389c <UARTReceive+0x36>
    3794:	32c0      	movi      	r2, 192
    3796:	9360      	ld.w      	r3, (r3, 0)
    3798:	4241      	lsli      	r2, r2, 1
    379a:	60c8      	addu      	r3, r2
    379c:	3280      	movi      	r2, 128
    379e:	4247      	lsli      	r2, r2, 7
    37a0:	b340      	st.w      	r2, (r3, 0)
}
    37a2:	783c      	rts

000037a4 <UART1_WakeUp_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_WakeUp_Enable(void)
{
    INTC_IWER_WRITE(UART1_INT);    
    37a4:	117e      	lrw      	r3, 0x20000064	// 389c <UARTReceive+0x36>
    37a6:	3280      	movi      	r2, 128
    37a8:	9360      	ld.w      	r3, (r3, 0)
    37aa:	23ff      	addi      	r3, 256
    37ac:	4247      	lsli      	r2, r2, 7
    37ae:	b350      	st.w      	r2, (r3, 0x40)
}
    37b0:	783c      	rts

000037b2 <UART1_WakeUp_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_WakeUp_Disable(void)
{
    INTC_IWDR_WRITE(UART1_INT);    
    37b2:	117b      	lrw      	r3, 0x20000064	// 389c <UARTReceive+0x36>
    37b4:	32e0      	movi      	r2, 224
    37b6:	9360      	ld.w      	r3, (r3, 0)
    37b8:	4241      	lsli      	r2, r2, 1
    37ba:	60c8      	addu      	r3, r2
    37bc:	3280      	movi      	r2, 128
    37be:	4247      	lsli      	r2, r2, 7
    37c0:	b340      	st.w      	r2, (r3, 0)
}
    37c2:	783c      	rts

000037c4 <UART_IO_Init>:
//UART_IO_G:0 1
//ReturnValue:NONE
/*************************************************************/
void UART_IO_Init(UART_NUM_TypeDef UART_IO_G)
{
    if (UART_IO_G==IO_PD0)
    37c4:	3840      	cmpnei      	r0, 0
    37c6:	080a      	bt      	0x37da	// 37da <UART_IO_Init+0x16>
    {
		GPIOD0->CONLR = (GPIOD0->CONLR&0XFFFFFF00)  | 0x00000055;       //PD0.1->RXD0, PD0.0->TXD0
    37c8:	1176      	lrw      	r3, 0x20000040	// 38a0 <UARTReceive+0x3a>
    37ca:	31ff      	movi      	r1, 255
    37cc:	9340      	ld.w      	r2, (r3, 0)
    37ce:	9260      	ld.w      	r3, (r2, 0)
    37d0:	68c5      	andn      	r3, r1
    37d2:	3155      	movi      	r1, 85
    37d4:	6cc4      	or      	r3, r1
    37d6:	b260      	st.w      	r3, (r2, 0)
    }
     if (UART_IO_G==IO_PA1)
    {
		GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFF00F)  | 0x00000660;       //PA1.2->RXD1, PA1.1->TXD1
    }
}
    37d8:	783c      	rts
     if (UART_IO_G==IO_PA1)
    37da:	3841      	cmpnei      	r0, 1
    37dc:	0bfe      	bt      	0x37d8	// 37d8 <UART_IO_Init+0x14>
		GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFF00F)  | 0x00000660;       //PA1.2->RXD1, PA1.1->TXD1
    37de:	1172      	lrw      	r3, 0x2000004c	// 38a4 <UARTReceive+0x3e>
    37e0:	32ff      	movi      	r2, 255
    37e2:	9320      	ld.w      	r1, (r3, 0)
    37e4:	9160      	ld.w      	r3, (r1, 0)
    37e6:	4244      	lsli      	r2, r2, 4
    37e8:	68c9      	andn      	r3, r2
    37ea:	32cc      	movi      	r2, 204
    37ec:	4243      	lsli      	r2, r2, 3
    37ee:	6cc8      	or      	r3, r2
    37f0:	b160      	st.w      	r3, (r1, 0)
}
    37f2:	07f3      	br      	0x37d8	// 37d8 <UART_IO_Init+0x14>

000037f4 <UARTInit>:
//ReturnValue:NONE
/*************************************************************/
void UARTInit(CSP_UART_T *uart,U32_T baudrate_u16)
{
   // Set Transmitter Enable
   CSP_UART_SET_CTRL(uart, UART_TX | UART_RX);
    37f4:	3303      	movi      	r3, 3
    37f6:	b062      	st.w      	r3, (r0, 0x8)
   // Set Baudrate
   CSP_UART_SET_BRDIV(uart, baudrate_u16);
    37f8:	b024      	st.w      	r1, (r0, 0x10)

}
    37fa:	783c      	rts

000037fc <UARTInitRxTxIntEn>:
    37fc:	330b      	movi      	r3, 11
    37fe:	b062      	st.w      	r3, (r0, 0x8)
    3800:	b024      	st.w      	r1, (r0, 0x10)
    3802:	9062      	ld.w      	r3, (r0, 0x8)
    3804:	6c8c      	or      	r2, r3
    3806:	b042      	st.w      	r2, (r0, 0x8)
    3808:	783c      	rts

0000380a <UARTInitRxIntEn>:
//ReturnValue:NONE
/*************************************************************/
void UARTInitRxIntEn(CSP_UART_T *uart,U32_T baudrate_u16,UART_PAR_TypeDef PAR_DAT)
{
   // Set Transmitter Enable
   CSP_UART_SET_CTRL(uart, UART_TX | UART_RX | UART_RX_INT);
    380a:	330b      	movi      	r3, 11
    380c:	b062      	st.w      	r3, (r0, 0x8)
   // Set Baudrate
   CSP_UART_SET_BRDIV(uart, baudrate_u16);
    380e:	b024      	st.w      	r1, (r0, 0x10)
   
   uart->CTRL|=PAR_DAT;
    3810:	9062      	ld.w      	r3, (r0, 0x8)
    3812:	6c8c      	or      	r2, r3
    3814:	b042      	st.w      	r2, (r0, 0x8)
}
    3816:	783c      	rts

00003818 <UARTClose>:
//ReturnValue:NONE
/*************************************************************/
void UARTClose(CSP_UART_T *uart)
{
	// Set Transmitter Disable
	CSP_UART_SET_CTRL(uart, 0x00);
    3818:	3300      	movi      	r3, 0
    381a:	b062      	st.w      	r3, (r0, 0x8)
}
    381c:	783c      	rts

0000381e <UARTTxByte>:
/*************************************************************/
void UARTTxByte(CSP_UART_T *uart,U8_T txdata_u8)
{
	unsigned int  DataI;
	// Write the transmit buffer
	CSP_UART_SET_DATA(uart,txdata_u8);
    381e:	b020      	st.w      	r1, (r0, 0)
	do
	{
		DataI = CSP_UART_GET_SR(uart);
		DataI = DataI & UART_TX_FULL;
    3820:	3201      	movi      	r2, 1
		DataI = CSP_UART_GET_SR(uart);
    3822:	9061      	ld.w      	r3, (r0, 0x4)
		DataI = DataI & UART_TX_FULL;
    3824:	68c8      	and      	r3, r2
	}
	while(DataI == UART_TX_FULL);    //Loop  when tx is full
    3826:	3b40      	cmpnei      	r3, 0
    3828:	0bfd      	bt      	0x3822	// 3822 <UARTTxByte+0x4>
	// Wait for the transmit done
	while ( (CSP_UART_GET_ISR(uart) & UART_TX_INT_S) != UART_TX_INT_S ) {}

	// Clear status bit for the next transmit
	CSP_UART_SET_ISR(uart, UART_TX_INT_S);*/
}
    382a:	783c      	rts

0000382c <UARTTransmit>:
//UART Transmit 
//EntryParameter:UART1,sourceAddress_u16,length_u16
//ReturnValue:NONE
/*************************************************************/
void UARTTransmit(CSP_UART_T *uart,U8_T *sourceAddress_u16,U16_T length_u16)
{
    382c:	14c2      	push      	r4-r5
	unsigned int  DataI,DataJ;
	for(DataJ = 0;DataJ < length_u16 ;DataJ ++)
    382e:	6cc7      	mov      	r3, r1
	{
		CSP_UART_SET_DATA(uart,*sourceAddress_u16++);
		do{
			DataI = CSP_UART_GET_SR(uart);
			DataI = DataI & UART_TX_FULL;
    3830:	3501      	movi      	r5, 1
	for(DataJ = 0;DataJ < length_u16 ;DataJ ++)
    3832:	5b85      	subu      	r4, r3, r1
    3834:	6490      	cmphs      	r4, r2
    3836:	0c02      	bf      	0x383a	// 383a <UARTTransmit+0xe>
		}while(DataI == UART_TX_FULL);    //Loop  when tx is full
	}
}
    3838:	1482      	pop      	r4-r5
		CSP_UART_SET_DATA(uart,*sourceAddress_u16++);
    383a:	8380      	ld.b      	r4, (r3, 0)
    383c:	b080      	st.w      	r4, (r0, 0)
			DataI = CSP_UART_GET_SR(uart);
    383e:	9081      	ld.w      	r4, (r0, 0x4)
			DataI = DataI & UART_TX_FULL;
    3840:	6914      	and      	r4, r5
		}while(DataI == UART_TX_FULL);    //Loop  when tx is full
    3842:	3c40      	cmpnei      	r4, 0
    3844:	0bfd      	bt      	0x383e	// 383e <UARTTransmit+0x12>
    3846:	2300      	addi      	r3, 1
    3848:	07f5      	br      	0x3832	// 3832 <UARTTransmit+0x6>

0000384a <UARTRxByte>:
/*************************************************************/
U16_T UARTRxByte(CSP_UART_T *uart,U8_T *Rxdata_u16)
{
	unsigned int  DataI;

	DataI = CSP_UART_GET_SR(uart);
    384a:	9061      	ld.w      	r3, (r0, 0x4)
	DataI = DataI & UART_RX_FULL;
    384c:	3202      	movi      	r2, 2
    384e:	68c8      	and      	r3, r2
	if(DataI != UART_RX_FULL)    //Loop  when rx is not full
    3850:	3b40      	cmpnei      	r3, 0
    3852:	0c05      	bf      	0x385c	// 385c <UARTRxByte+0x12>
		return FALSE;
	else
	{
		*Rxdata_u16 = CSP_UART_GET_DATA(uart);
    3854:	9060      	ld.w      	r3, (r0, 0)
    3856:	a160      	st.b      	r3, (r1, 0)
	    return TRUE;
    3858:	3001      	movi      	r0, 1
	}
}
    385a:	783c      	rts
		return FALSE;
    385c:	3000      	movi      	r0, 0
    385e:	07fe      	br      	0x385a	// 385a <UARTRxByte+0x10>

00003860 <UART_ReturnRxByte>:
//EntryParameter:UART1
//ReturnValue:(uart)->DATA
/*************************************************************/
U8_T UART_ReturnRxByte(CSP_UART_T *uart)
{
	return CSP_UART_GET_DATA(uart);
    3860:	9000      	ld.w      	r0, (r0, 0)
    3862:	7400      	zextb      	r0, r0
}
    3864:	783c      	rts

00003866 <UARTReceive>:
//UART Receive
//EntryParameter:UART1，destAddress_u16，length_u16
//ReturnValue:FALSE/TRUE
/*************************************************************/
U16_T UARTReceive(CSP_UART_T *uart,U8_T *destAddress_u16,U16_T length_u16)
{
    3866:	14c4      	push      	r4-r7
	unsigned int  DataI,DataJ,LoopTime;

	DataJ = 0;
	LoopTime = 0;
    3868:	3500      	movi      	r5, 0
	DataJ = 0;
    386a:	3300      	movi      	r3, 0
	do{
		DataI = CSP_UART_GET_SR(uart);
		DataI = DataI & UART_RX_FULL;
    386c:	3602      	movi      	r6, 2
		{
			*destAddress_u16++ = CSP_UART_GET_DATA(uart);
			DataJ++;
			LoopTime = 0;
		}
		if(LoopTime ++ >= 0xfff0)
    386e:	10ef      	lrw      	r7, 0xffef	// 38a8 <UARTReceive+0x42>
		DataI = CSP_UART_GET_SR(uart);
    3870:	9081      	ld.w      	r4, (r0, 0x4)
		DataI = DataI & UART_RX_FULL;
    3872:	6918      	and      	r4, r6
		if(DataI == UART_RX_FULL)    //Loop  when rx is full
    3874:	3c40      	cmpnei      	r4, 0
    3876:	0c0d      	bf      	0x3890	// 3890 <UARTReceive+0x2a>
			*destAddress_u16++ = CSP_UART_GET_DATA(uart);
    3878:	9080      	ld.w      	r4, (r0, 0)
    387a:	a180      	st.b      	r4, (r1, 0)
			DataJ++;
    387c:	2300      	addi      	r3, 1
			*destAddress_u16++ = CSP_UART_GET_DATA(uart);
    387e:	2100      	addi      	r1, 1
			LoopTime = 0;
    3880:	3400      	movi      	r4, 0
		if(LoopTime ++ >= 0xfff0)
    3882:	651c      	cmphs      	r7, r4
    3884:	5ca2      	addi      	r5, r4, 1
    3886:	0c07      	bf      	0x3894	// 3894 <UARTReceive+0x2e>
			return FALSE;
	}while(DataJ < length_u16);
    3888:	648c      	cmphs      	r3, r2
    388a:	0ff3      	bf      	0x3870	// 3870 <UARTReceive+0xa>
	return TRUE;
    388c:	3001      	movi      	r0, 1
}
    388e:	1484      	pop      	r4-r7
    3890:	6d17      	mov      	r4, r5
    3892:	07f8      	br      	0x3882	// 3882 <UARTReceive+0x1c>
			return FALSE;
    3894:	3000      	movi      	r0, 0
    3896:	07fc      	br      	0x388e	// 388e <UARTReceive+0x28>
    3898:	20000010 	.long	0x20000010
    389c:	20000064 	.long	0x20000064
    38a0:	20000040 	.long	0x20000040
    38a4:	2000004c 	.long	0x2000004c
    38a8:	0000ffef 	.long	0x0000ffef

000038ac <USART_DeInit>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void USART_DeInit(void)
{
	USART0->IDR   	= USART_IDR_RST;
    38ac:	106c      	lrw      	r3, 0x20000014	// 38dc <USART_DeInit+0x30>
    38ae:	104d      	lrw      	r2, 0x11001b	// 38e0 <USART_DeInit+0x34>
    38b0:	9360      	ld.w      	r3, (r3, 0)
    38b2:	b340      	st.w      	r2, (r3, 0)
	USART0->CEDR   	= USART_CEDR_RST;
    38b4:	3200      	movi      	r2, 0
    38b6:	b341      	st.w      	r2, (r3, 0x4)
	USART0->SRR 	= USART_SRR_RST;
    38b8:	b342      	st.w      	r2, (r3, 0x8)
	USART0->CR 		= USART_CR_RST;
    38ba:	b343      	st.w      	r2, (r3, 0xc)
	USART0->MR   	= USART_MR_RST;
    38bc:	b344      	st.w      	r2, (r3, 0x10)
	USART0->IMSCR   = USART_IMSCR_RST;
    38be:	b345      	st.w      	r2, (r3, 0x14)
	USART0->RISR  	= USART_RISR_RST;
    38c0:	b346      	st.w      	r2, (r3, 0x18)
	USART0->MISR   	= USART_MISR_RST;
    38c2:	b347      	st.w      	r2, (r3, 0x1c)
	USART0->ICR   	= USART_ICR_RST;
    38c4:	b348      	st.w      	r2, (r3, 0x20)
	USART0->SR   	= USART_SR_RST;
    38c6:	3280      	movi      	r2, 128
    38c8:	4244      	lsli      	r2, r2, 4
    38ca:	b349      	st.w      	r2, (r3, 0x24)
	USART0->RHR   	= USART_RHR_RST;
    38cc:	3200      	movi      	r2, 0
    38ce:	b34a      	st.w      	r2, (r3, 0x28)
	USART0->THR   	= USART_THR_RST;
    38d0:	b34b      	st.w      	r2, (r3, 0x2c)
	USART0->BRGR   	= USART_BRGR_RST;
    38d2:	b34c      	st.w      	r2, (r3, 0x30)
	USART0->RTOR   	= USART_RTOR_RST;
    38d4:	b34d      	st.w      	r2, (r3, 0x34)
	USART0->TTGR   	= USART_TTGR_RST;
    38d6:	b34e      	st.w      	r2, (r3, 0x38)
}
    38d8:	783c      	rts
    38da:	0000      	bkpt
    38dc:	20000014 	.long	0x20000014
    38e0:	0011001b 	.long	0x0011001b

000038e4 <USART_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void USART_Int_Enable(void)
{
    USART0->ICR=0x7FF;									//clear USART INT status
    38e4:	1364      	lrw      	r3, 0x20000014	// 3a74 <USART_Baudrate_Cal+0x10>
    38e6:	1345      	lrw      	r2, 0x7ff	// 3a78 <USART_Baudrate_Cal+0x14>
    38e8:	9360      	ld.w      	r3, (r3, 0)
    38ea:	b348      	st.w      	r2, (r3, 0x20)
	INTC_ISER_WRITE(USART0_INT);							//INT Vector Enable USART Interrupt
    38ec:	3280      	movi      	r2, 128
    38ee:	1364      	lrw      	r3, 0x20000064	// 3a7c <USART_Baudrate_Cal+0x18>
    38f0:	4246      	lsli      	r2, r2, 6
    38f2:	9360      	ld.w      	r3, (r3, 0)
    38f4:	23ff      	addi      	r3, 256
    38f6:	b340      	st.w      	r2, (r3, 0)
}
    38f8:	783c      	rts

000038fa <USART_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void USART_Int_Disable(void)
{
	INTC_ICER_WRITE(USART0_INT);							//INT Vector Enable USART Interrupt
    38fa:	1361      	lrw      	r3, 0x20000064	// 3a7c <USART_Baudrate_Cal+0x18>
    38fc:	32c0      	movi      	r2, 192
    38fe:	9360      	ld.w      	r3, (r3, 0)
    3900:	4241      	lsli      	r2, r2, 1
    3902:	60c8      	addu      	r3, r2
    3904:	3280      	movi      	r2, 128
    3906:	4246      	lsli      	r2, r2, 6
    3908:	b340      	st.w      	r2, (r3, 0)
}
    390a:	783c      	rts

0000390c <USART_WakeUp_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void USART_WakeUp_Enable(void)
{
    INTC_IWER_WRITE(USART0_INT);    
    390c:	127c      	lrw      	r3, 0x20000064	// 3a7c <USART_Baudrate_Cal+0x18>
    390e:	3280      	movi      	r2, 128
    3910:	9360      	ld.w      	r3, (r3, 0)
    3912:	23ff      	addi      	r3, 256
    3914:	4246      	lsli      	r2, r2, 6
    3916:	b350      	st.w      	r2, (r3, 0x40)
}
    3918:	783c      	rts

0000391a <USART_WakeUp_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void USART_WakeUp_Disable(void)
{
    INTC_IWDR_WRITE(USART0_INT);    
    391a:	1279      	lrw      	r3, 0x20000064	// 3a7c <USART_Baudrate_Cal+0x18>
    391c:	32e0      	movi      	r2, 224
    391e:	9360      	ld.w      	r3, (r3, 0)
    3920:	4241      	lsli      	r2, r2, 1
    3922:	60c8      	addu      	r3, r2
    3924:	3280      	movi      	r2, 128
    3926:	4246      	lsli      	r2, r2, 6
    3928:	b340      	st.w      	r2, (r3, 0)
}
    392a:	783c      	rts

0000392c <USART_IO_Init>:
//USART_IO_G:0 1
//ReturnValue:NONE
/*************************************************************/
void USART_IO_Init(USART_NUM_TypeDef USART_IO_G)
{
    if (USART_IO_G==USART_PB0)
    392c:	3840      	cmpnei      	r0, 0
    392e:	080a      	bt      	0x3942	// 3942 <USART_IO_Init+0x16>
    {
		GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF00)  | 0x00000044;       //PB0.0->RXD0, PB0.1->TXD0
    3930:	1274      	lrw      	r3, 0x20000048	// 3a80 <USART_Baudrate_Cal+0x1c>
    3932:	31ff      	movi      	r1, 255
    3934:	9340      	ld.w      	r2, (r3, 0)
    3936:	9260      	ld.w      	r3, (r2, 0)
    3938:	68c5      	andn      	r3, r1
    393a:	3ba2      	bseti      	r3, r3, 2
    393c:	3ba6      	bseti      	r3, r3, 6
    393e:	b260      	st.w      	r3, (r2, 0)
    }
     if (USART_IO_G==USART_PA0)
    {
		GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF00FFF)  | 0x00055000;       //PA0.3->RXD1, PA0.4->TXD1
    }
}
    3940:	783c      	rts
     if (USART_IO_G==USART_PA0)
    3942:	3841      	cmpnei      	r0, 1
    3944:	0bfe      	bt      	0x3940	// 3940 <USART_IO_Init+0x14>
		GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF00FFF)  | 0x00055000;       //PA0.3->RXD1, PA0.4->TXD1
    3946:	1270      	lrw      	r3, 0x20000050	// 3a84 <USART_Baudrate_Cal+0x20>
    3948:	32ff      	movi      	r2, 255
    394a:	9320      	ld.w      	r1, (r3, 0)
    394c:	9160      	ld.w      	r3, (r1, 0)
    394e:	424c      	lsli      	r2, r2, 12
    3950:	68c9      	andn      	r3, r2
    3952:	32aa      	movi      	r2, 170
    3954:	424b      	lsli      	r2, r2, 11
    3956:	6cc8      	or      	r3, r2
    3958:	b160      	st.w      	r3, (r1, 0)
}
    395a:	07f3      	br      	0x3940	// 3940 <USART_IO_Init+0x14>

0000395c <USART_CLKIO_Init>:
//USART_IO_G:0 1
//ReturnValue:NONE
/*************************************************************/
void USART_CLKIO_Init(USART_CLKNUM_TypeDef USART_CLKIO_G)
{
    if (USART_CLKIO_G==CLK_PA02)
    395c:	3840      	cmpnei      	r0, 0
    395e:	080d      	bt      	0x3978	// 3978 <USART_CLKIO_Init+0x1c>
    {
		GPIOA0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF)  | 0x00000600;       //PA0.2 AS USART CK OUT
    3960:	1269      	lrw      	r3, 0x20000050	// 3a84 <USART_Baudrate_Cal+0x20>
    3962:	32f0      	movi      	r2, 240
    3964:	9320      	ld.w      	r1, (r3, 0)
    3966:	4244      	lsli      	r2, r2, 4
    3968:	1266      	lrw      	r3, 0x20000048	// 3a80 <USART_Baudrate_Cal+0x1c>
    396a:	9360      	ld.w      	r3, (r3, 0)
    396c:	9360      	ld.w      	r3, (r3, 0)
    396e:	68c9      	andn      	r3, r2
    3970:	3ba9      	bseti      	r3, r3, 9
    3972:	3baa      	bseti      	r3, r3, 10
    }
     if (USART_CLKIO_G==CLK_PA05)
    {
		GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF)  | 0x00500000;       //PA0.5 AS USART CK OUT
    3974:	b160      	st.w      	r3, (r1, 0)
    }
}
    3976:	783c      	rts
     if (USART_CLKIO_G==CLK_PA05)
    3978:	3841      	cmpnei      	r0, 1
    397a:	0bfe      	bt      	0x3976	// 3976 <USART_CLKIO_Init+0x1a>
		GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF)  | 0x00500000;       //PA0.5 AS USART CK OUT
    397c:	1262      	lrw      	r3, 0x20000050	// 3a84 <USART_Baudrate_Cal+0x20>
    397e:	32f0      	movi      	r2, 240
    3980:	9320      	ld.w      	r1, (r3, 0)
    3982:	9160      	ld.w      	r3, (r1, 0)
    3984:	4250      	lsli      	r2, r2, 16
    3986:	68c9      	andn      	r3, r2
    3988:	3bb4      	bseti      	r3, r3, 20
    398a:	3bb6      	bseti      	r3, r3, 22
    398c:	07f4      	br      	0x3974	// 3974 <USART_CLKIO_Init+0x18>

0000398e <USART_Software_Reset>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void USART_Software_Reset(void)
{
	USART0->SRR =0x01;
    398e:	117a      	lrw      	r3, 0x20000014	// 3a74 <USART_Baudrate_Cal+0x10>
    3990:	3201      	movi      	r2, 1
    3992:	9360      	ld.w      	r3, (r3, 0)
    3994:	b342      	st.w      	r2, (r3, 0x8)
}
    3996:	783c      	rts

00003998 <USART_CLK_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void USART_CLK_Disable(void)
{
   USART0->CEDR |= 0; 							//Disable USART Clock 
    3998:	1177      	lrw      	r3, 0x20000014	// 3a74 <USART_Baudrate_Cal+0x10>
    399a:	9360      	ld.w      	r3, (r3, 0)
    399c:	9341      	ld.w      	r2, (r3, 0x4)
    399e:	b341      	st.w      	r2, (r3, 0x4)
}
    39a0:	783c      	rts

000039a2 <USART_CLK_Enable>:
//EntryParameter:INT_RegVal
//ReturnValue:NONE
/*************************************************************/
void USART_CLK_Enable(void)
{
   USART0->CEDR |= 1; 							//Disable USART Clock 
    39a2:	1175      	lrw      	r3, 0x20000014	// 3a74 <USART_Baudrate_Cal+0x10>
    39a4:	9340      	ld.w      	r2, (r3, 0)
    39a6:	9261      	ld.w      	r3, (r2, 0x4)
    39a8:	3ba0      	bseti      	r3, r3, 0
    39aa:	b261      	st.w      	r3, (r2, 0x4)
}
    39ac:	783c      	rts

000039ae <USART_INT_Config>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void USART_INT_Config(USART_INT_TypeDef int_type,FunctionalStatus newState)
{
	CSP_USART_SET_ICR(USART0, 0xFFFFFFFF);			// Clear all interrupt
    39ae:	1172      	lrw      	r3, 0x20000014	// 3a74 <USART_Baudrate_Cal+0x10>
    39b0:	3200      	movi      	r2, 0
    39b2:	9360      	ld.w      	r3, (r3, 0)
    39b4:	2a00      	subi      	r2, 1
	if (newState != DISABLE)
    39b6:	3940      	cmpnei      	r1, 0
	CSP_USART_SET_ICR(USART0, 0xFFFFFFFF);			// Clear all interrupt
    39b8:	b348      	st.w      	r2, (r3, 0x20)
	if (newState != DISABLE)
    39ba:	0c07      	bf      	0x39c8	// 39c8 <USART_INT_Config+0x1a>
	{
		USART0->IMSCR |=1<<int_type;					// Interrupt Enable
    39bc:	3201      	movi      	r2, 1
    39be:	9325      	ld.w      	r1, (r3, 0x14)
    39c0:	7080      	lsl      	r2, r0
    39c2:	6c84      	or      	r2, r1
	}
	else
	{
		USART0->IMSCR |=0<<int_type;					// Interrupt Disable
    39c4:	b345      	st.w      	r2, (r3, 0x14)
	}
}
    39c6:	783c      	rts
		USART0->IMSCR |=0<<int_type;					// Interrupt Disable
    39c8:	9345      	ld.w      	r2, (r3, 0x14)
    39ca:	07fd      	br      	0x39c4	// 39c4 <USART_INT_Config+0x16>

000039cc <USART_INT_RegConfig>:
//EntryParameter:INT_RegVal
//ReturnValue:NONE
/*************************************************************/
void USART_INT_RegConfig(U32_T INT_RegVal)
{
	CSP_USART_SET_ICR(USART0, 0xFFFFFFFF);
    39cc:	116a      	lrw      	r3, 0x20000014	// 3a74 <USART_Baudrate_Cal+0x10>
    39ce:	9340      	ld.w      	r2, (r3, 0)
    39d0:	3300      	movi      	r3, 0
    39d2:	2b00      	subi      	r3, 1
    39d4:	b268      	st.w      	r3, (r2, 0x20)
	CSP_USART_SET_IMSCR(USART0, INT_RegVal);
    39d6:	b205      	st.w      	r0, (r2, 0x14)

}
    39d8:	783c      	rts

000039da <USART_MODE_Config>:
//EntryParameter:INT_RegVal
//ReturnValue:NONE
/*************************************************************/
void USART_MODE_Config(USART_SENDTIME_TypeDef SENDTIME_DATA,USART_CLKS_TypeDef CLKS_DATA, USART_CHRL_TypeDef CHRL_DATA,
						USART_SYNC_TypeDef SYNC_DATA,USART_PAR_TypeDef PAR_DAT,USART_NBSTOP_TypeDef NBSTOP_DATA,USART_CHMODE_TypeDef CHMODE_DATA)
{
    39da:	14c4      	push      	r4-r7
    39dc:	1421      	subi      	sp, sp, 4
    39de:	9885      	ld.w      	r4, (sp, 0x14)
    39e0:	6dd3      	mov      	r7, r4
    39e2:	9886      	ld.w      	r4, (sp, 0x18)
    39e4:	b880      	st.w      	r4, (sp, 0)
    39e6:	9887      	ld.w      	r4, (sp, 0x1c)
    39e8:	6d93      	mov      	r6, r4
	USART0->MR |= 0<<17;
    39ea:	1183      	lrw      	r4, 0x20000014	// 3a74 <USART_Baudrate_Cal+0x10>
    39ec:	94a0      	ld.w      	r5, (r4, 0)
    39ee:	9584      	ld.w      	r4, (r5, 0x10)
    39f0:	b584      	st.w      	r4, (r5, 0x10)
	USART0->MR |= SENDTIME_DATA | CLKS_DATA | CHRL_DATA | SYNC_DATA | PAR_DAT| NBSTOP_DATA | CHMODE_DATA;
    39f2:	9584      	ld.w      	r4, (r5, 0x10)
    39f4:	6d18      	or      	r4, r6
    39f6:	98c0      	ld.w      	r6, (sp, 0)
    39f8:	6d18      	or      	r4, r6
    39fa:	6d1c      	or      	r4, r7
    39fc:	6cd0      	or      	r3, r4
    39fe:	6c8c      	or      	r2, r3
    3a00:	6c48      	or      	r1, r2
    3a02:	6c04      	or      	r0, r1
    3a04:	6d9f      	mov      	r6, r7
    3a06:	b504      	st.w      	r0, (r5, 0x10)
}
    3a08:	1401      	addi      	sp, sp, 4
    3a0a:	1484      	pop      	r4-r7

00003a0c <USART_CTRL_Config>:
//EntryParameter:CTRL_DATA, ENABLE/DISABLE
//ReturnValue:NONE
/*************************************************************/
void USART_CTRL_Config(USART_CTRL_TypeDef CTRL_DATA,FunctionalStatus newState)
{
	if (newState!=DISABLE)
    3a0c:	3940      	cmpnei      	r1, 0
    3a0e:	107a      	lrw      	r3, 0x20000014	// 3a74 <USART_Baudrate_Cal+0x10>
    3a10:	0c08      	bf      	0x3a20	// 3a20 <USART_CTRL_Config+0x14>
	{
		USART0->CR  |= 1<<CTRL_DATA;
    3a12:	9340      	ld.w      	r2, (r3, 0)
    3a14:	3301      	movi      	r3, 1
    3a16:	9223      	ld.w      	r1, (r2, 0xc)
    3a18:	70c0      	lsl      	r3, r0
    3a1a:	6cc4      	or      	r3, r1
    3a1c:	b263      	st.w      	r3, (r2, 0xc)
	}
	else
	{
		USART0->CR  |= 0<<CTRL_DATA;
	}
}
    3a1e:	783c      	rts
		USART0->CR  |= 0<<CTRL_DATA;
    3a20:	9360      	ld.w      	r3, (r3, 0)
    3a22:	9343      	ld.w      	r2, (r3, 0xc)
    3a24:	b343      	st.w      	r2, (r3, 0xc)
}
    3a26:	07fc      	br      	0x3a1e	// 3a1e <USART_CTRL_Config+0x12>

00003a28 <USART_DSB_Config>:
//EntryParameter:LSBtoMSB / MSBtoLSB
//ReturnValue:NONE
/*************************************************************/
void USART_DSB_Config(USART_DSB_TypeDef DSB_DATA)
{
	USART0->MR |= DSB_DATA;
    3a28:	1073      	lrw      	r3, 0x20000014	// 3a74 <USART_Baudrate_Cal+0x10>
    3a2a:	9340      	ld.w      	r2, (r3, 0)
    3a2c:	9264      	ld.w      	r3, (r2, 0x10)
    3a2e:	6c0c      	or      	r0, r3
    3a30:	b204      	st.w      	r0, (r2, 0x10)
}
    3a32:	783c      	rts

00003a34 <USART_SAMRTCARD_Config>:
//EntryParameter:DISABLE/ENABLE
//ReturnValue:NONE
/*************************************************************/
void USART_SAMRTCARD_Config(FunctionalStatus newState)
{
	if (newState!=DISABLE)
    3a34:	3840      	cmpnei      	r0, 0
    3a36:	1070      	lrw      	r3, 0x20000014	// 3a74 <USART_Baudrate_Cal+0x10>
    3a38:	0c06      	bf      	0x3a44	// 3a44 <USART_SAMRTCARD_Config+0x10>
	{
		USART0->MR |= 1<<16;
    3a3a:	9340      	ld.w      	r2, (r3, 0)
    3a3c:	9264      	ld.w      	r3, (r2, 0x10)
    3a3e:	3bb0      	bseti      	r3, r3, 16
    3a40:	b264      	st.w      	r3, (r2, 0x10)
	}
	else
	{
		USART0->MR |= 0<<16;
	}
}
    3a42:	783c      	rts
		USART0->MR |= 0<<16;
    3a44:	9360      	ld.w      	r3, (r3, 0)
    3a46:	9344      	ld.w      	r2, (r3, 0x10)
    3a48:	b344      	st.w      	r2, (r3, 0x10)
}
    3a4a:	07fc      	br      	0x3a42	// 3a42 <USART_SAMRTCARD_Config+0xe>

00003a4c <USART_CLKO_Config>:
//EntryParameter:DISABLE/ENABLE
//ReturnValue:NONE
/*************************************************************/
void USART_CLKO_Config(FunctionalStatus newState)
{
	if (newState!=DISABLE)
    3a4c:	3840      	cmpnei      	r0, 0
    3a4e:	106a      	lrw      	r3, 0x20000014	// 3a74 <USART_Baudrate_Cal+0x10>
    3a50:	0c06      	bf      	0x3a5c	// 3a5c <USART_CLKO_Config+0x10>
	{
		USART0->MR |= (1<<18) | (0<<4) ;
    3a52:	9340      	ld.w      	r2, (r3, 0)
    3a54:	9264      	ld.w      	r3, (r2, 0x10)
    3a56:	3bb2      	bseti      	r3, r3, 18
    3a58:	b264      	st.w      	r3, (r2, 0x10)
	}
	else
	{
		USART0->MR |= 0<<18;
	}
}
    3a5a:	783c      	rts
		USART0->MR |= 0<<18;
    3a5c:	9360      	ld.w      	r3, (r3, 0)
    3a5e:	9344      	ld.w      	r2, (r3, 0x10)
    3a60:	b344      	st.w      	r2, (r3, 0x10)
}
    3a62:	07fc      	br      	0x3a5a	// 3a5a <USART_CLKO_Config+0xe>

00003a64 <USART_Baudrate_Cal>:
//USART baudrate calculate
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void USART_Baudrate_Cal(unsigned int rate,unsigned int PCLK_Val,USART_CLKS_TypeDef CLKS_DATA,USART_SYNC_TypeDef SYNC_DATA)
{
    3a64:	14d1      	push      	r4, r15
	unsigned int PCLK_Data=0;
	unsigned int BRGR_Data=0;
	if (CLKS_DATA==PCLK_DIV8)
    3a66:	3a50      	cmpnei      	r2, 16
{
    3a68:	6d03      	mov      	r4, r0
    3a6a:	6c07      	mov      	r0, r1
	if (CLKS_DATA==PCLK_DIV8)
    3a6c:	080e      	bt      	0x3a88	// 3a88 <USART_Baudrate_Cal+0x24>
	{
		PCLK_Data=PCLK_Val/8;
    3a6e:	4903      	lsri      	r0, r1, 3
    3a70:	040c      	br      	0x3a88	// 3a88 <USART_Baudrate_Cal+0x24>
    3a72:	0000      	bkpt
    3a74:	20000014 	.long	0x20000014
    3a78:	000007ff 	.long	0x000007ff
    3a7c:	20000064 	.long	0x20000064
    3a80:	20000048 	.long	0x20000048
    3a84:	20000050 	.long	0x20000050
	}
	else PCLK_Data=PCLK_Val;
	if (SYNC_DATA==SYNC)
    3a88:	3280      	movi      	r2, 128
    3a8a:	4241      	lsli      	r2, r2, 1
    3a8c:	648e      	cmpne      	r3, r2
    3a8e:	0809      	bt      	0x3aa0	// 3aa0 <USART_Baudrate_Cal+0x3c>
	{
		BRGR_Data=PCLK_Data/rate;			//SYNC同步
	}
	else 
	{
		BRGR_Data=PCLK_Data/16/rate;				//ASYNC异步
    3a90:	6c53      	mov      	r1, r4
    3a92:	e0000bd9 	bsr      	0x5244	// 5244 <__udiv32>
	}
	USART0->BRGR = BRGR_Data<<4;
    3a96:	116f      	lrw      	r3, 0x20000014	// 3b50 <USARTReceive+0x38>
    3a98:	4004      	lsli      	r0, r0, 4
    3a9a:	9360      	ld.w      	r3, (r3, 0)
    3a9c:	b30c      	st.w      	r0, (r3, 0x30)
}
    3a9e:	1491      	pop      	r4, r15
		BRGR_Data=PCLK_Data/16/rate;				//ASYNC异步
    3aa0:	4804      	lsri      	r0, r0, 4
    3aa2:	07f7      	br      	0x3a90	// 3a90 <USART_Baudrate_Cal+0x2c>

00003aa4 <USART_TGTO_Config>:
//EntryParameter:INT_RegVal
//ReturnValue:NONE
/*************************************************************/
void USART_TGTO_Config(U8_T timeOut_u8,U8_T timeGuard_u8)
{
    USART0->RTOR=timeOut_u8;					// Set Receiver Time Out
    3aa4:	116b      	lrw      	r3, 0x20000014	// 3b50 <USARTReceive+0x38>
    3aa6:	9360      	ld.w      	r3, (r3, 0)
    3aa8:	b30d      	st.w      	r0, (r3, 0x34)
    USART0->TTGR=timeGuard_u8;					// Set Transmitter Timer Guard
    3aaa:	b32e      	st.w      	r1, (r3, 0x38)
}
    3aac:	783c      	rts

00003aae <USART_TxByte>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void USART_TxByte(U16_T TXdata_u8)
{
	CSP_USART_SET_THR(USART0,TXdata_u8);		// Write the transmit buffer
    3aae:	1169      	lrw      	r3, 0x20000014	// 3b50 <USARTReceive+0x38>
	while ( (CSP_USART_GET_RISR(USART0) & USART_TXRDY) != USART_TXRDY ) {}	// Wait for the transmit done
    3ab0:	3102      	movi      	r1, 2
	CSP_USART_SET_THR(USART0,TXdata_u8);		// Write the transmit buffer
    3ab2:	9360      	ld.w      	r3, (r3, 0)
    3ab4:	b30b      	st.w      	r0, (r3, 0x2c)
	while ( (CSP_USART_GET_RISR(USART0) & USART_TXRDY) != USART_TXRDY ) {}	// Wait for the transmit done
    3ab6:	9346      	ld.w      	r2, (r3, 0x18)
    3ab8:	6884      	and      	r2, r1
    3aba:	3a40      	cmpnei      	r2, 0
    3abc:	0ffd      	bf      	0x3ab6	// 3ab6 <USART_TxByte+0x8>
	CSP_USART_SET_ICR(USART0, USART_TXRDY);		// Clear status bit for the next transmit
    3abe:	3202      	movi      	r2, 2
    3ac0:	b348      	st.w      	r2, (r3, 0x20)
}
    3ac2:	783c      	rts

00003ac4 <USARTTransmit>:
//UART Transmit 
//EntryParameter:UART0,UART1,sourceAddress_u16,length_u16
//ReturnValue:NONE
/*************************************************************/
void USARTTransmit(U16_T *sourceAddress_u16,U16_T length_u16)
{
    3ac4:	14c2      	push      	r4-r5
	unsigned int  DataJ;  //DataI,
	for(DataJ = 0;DataJ < length_u16 ;DataJ ++)
	{
		CSP_USART_SET_THR(USART0,*sourceAddress_u16++);
    3ac6:	1163      	lrw      	r3, 0x20000014	// 3b50 <USARTReceive+0x38>
		/*do{
			DataI = CSP_USART_GET_RHR(USART0);
			DataI = DataI & USART_TXRDY;
		}while(DataI == USART_TXRDY);    //Loop  when tx is full
		*/
		while ( (CSP_USART_GET_RISR(USART0) & USART_TXRDY) != USART_TXRDY ) {}	// Wait for the transmit done
    3ac8:	3502      	movi      	r5, 2
		CSP_USART_SET_THR(USART0,*sourceAddress_u16++);
    3aca:	9340      	ld.w      	r2, (r3, 0)
	for(DataJ = 0;DataJ < length_u16 ;DataJ ++)
    3acc:	3300      	movi      	r3, 0
    3ace:	644c      	cmphs      	r3, r1
    3ad0:	0c02      	bf      	0x3ad4	// 3ad4 <USARTTransmit+0x10>
		CSP_USART_SET_ICR(USART0, USART_TXRDY);		// Clear status bit for the next transmit
	}
}
    3ad2:	1482      	pop      	r4-r5
		CSP_USART_SET_THR(USART0,*sourceAddress_u16++);
    3ad4:	8880      	ld.h      	r4, (r0, 0)
    3ad6:	b28b      	st.w      	r4, (r2, 0x2c)
		while ( (CSP_USART_GET_RISR(USART0) & USART_TXRDY) != USART_TXRDY ) {}	// Wait for the transmit done
    3ad8:	9286      	ld.w      	r4, (r2, 0x18)
    3ada:	6914      	and      	r4, r5
    3adc:	3c40      	cmpnei      	r4, 0
    3ade:	0ffd      	bf      	0x3ad8	// 3ad8 <USARTTransmit+0x14>
		CSP_USART_SET_ICR(USART0, USART_TXRDY);		// Clear status bit for the next transmit
    3ae0:	3402      	movi      	r4, 2
    3ae2:	b288      	st.w      	r4, (r2, 0x20)
	for(DataJ = 0;DataJ < length_u16 ;DataJ ++)
    3ae4:	2300      	addi      	r3, 1
    3ae6:	2001      	addi      	r0, 2
    3ae8:	07f3      	br      	0x3ace	// 3ace <USARTTransmit+0xa>

00003aea <USARTRxByte>:
/*************************************************************/
U16_T USARTRxByte(CSP_UART_T *uart,U16_T *Rxdata_u16)
{
	unsigned int  DataI;

	DataI = CSP_USART_GET_RHR(USART0);
    3aea:	107a      	lrw      	r3, 0x20000014	// 3b50 <USARTReceive+0x38>
	DataI = DataI & USART_RXRDY;
    3aec:	3001      	movi      	r0, 1
	DataI = CSP_USART_GET_RHR(USART0);
    3aee:	9340      	ld.w      	r2, (r3, 0)
    3af0:	926a      	ld.w      	r3, (r2, 0x28)
	DataI = DataI & USART_RXRDY;
    3af2:	68c0      	and      	r3, r0
	if(DataI != USART_RXRDY)    //Loop  when rx is not full
    3af4:	3b40      	cmpnei      	r3, 0
    3af6:	0c04      	bf      	0x3afe	// 3afe <USARTRxByte+0x14>
		return FALSE;
	else
	{
		*Rxdata_u16 = CSP_USART_GET_RHR(USART0);
    3af8:	926a      	ld.w      	r3, (r2, 0x28)
    3afa:	a960      	st.h      	r3, (r1, 0)
	    return TRUE;
	}
}
    3afc:	783c      	rts
		return FALSE;
    3afe:	3000      	movi      	r0, 0
    3b00:	07fe      	br      	0x3afc	// 3afc <USARTRxByte+0x12>

00003b02 <USART_ReturnRxByte>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
U16_T USART_ReturnRxByte(void)
{
	RxDataFlag = FALSE;
    3b02:	1075      	lrw      	r3, 0x20000075	// 3b54 <USARTReceive+0x3c>
    3b04:	3200      	movi      	r2, 0
    3b06:	a340      	st.b      	r2, (r3, 0)
	while(RxDataFlag != TRUE);
    3b08:	8340      	ld.b      	r2, (r3, 0)
    3b0a:	3a41      	cmpnei      	r2, 1
    3b0c:	0bfe      	bt      	0x3b08	// 3b08 <USART_ReturnRxByte+0x6>
	return CSP_USART_GET_RHR(USART0);
    3b0e:	1071      	lrw      	r3, 0x20000014	// 3b50 <USARTReceive+0x38>
    3b10:	9360      	ld.w      	r3, (r3, 0)
    3b12:	930a      	ld.w      	r0, (r3, 0x28)
    3b14:	7401      	zexth      	r0, r0
}
    3b16:	783c      	rts

00003b18 <USARTReceive>:
//USART Receive 
//EntryParameter:destAddress_u16,length_u16
//ReturnValue:NONE
/*************************************************************/
U16_T USARTReceive(U16_T *destAddress_u16,U16_T length_u16)
{
    3b18:	14c4      	push      	r4-r7
	unsigned int  DataI,DataJ,LoopTime;

	DataJ = 0;
	LoopTime = 0;
	do{
		DataI = CSP_USART_GET_RHR(USART0);
    3b1a:	106e      	lrw      	r3, 0x20000014	// 3b50 <USARTReceive+0x38>
	LoopTime = 0;
    3b1c:	3400      	movi      	r4, 0
		DataI = CSP_USART_GET_RHR(USART0);
    3b1e:	93a0      	ld.w      	r5, (r3, 0)
		DataI = DataI & USART_RXRDY;
    3b20:	3601      	movi      	r6, 1
	DataJ = 0;
    3b22:	3300      	movi      	r3, 0
		{
			*destAddress_u16++ = CSP_USART_GET_RHR(USART0);
			DataJ++;
			LoopTime = 0;
		}
		if(LoopTime ++ >= 0xfff0)
    3b24:	10ed      	lrw      	r7, 0xffef	// 3b58 <USARTReceive+0x40>
		DataI = CSP_USART_GET_RHR(USART0);
    3b26:	954a      	ld.w      	r2, (r5, 0x28)
		DataI = DataI & USART_RXRDY;
    3b28:	6898      	and      	r2, r6
		if(DataI == USART_RXRDY)    //Loop  when rx is full
    3b2a:	3a40      	cmpnei      	r2, 0
    3b2c:	0c0d      	bf      	0x3b46	// 3b46 <USARTReceive+0x2e>
			*destAddress_u16++ = CSP_USART_GET_RHR(USART0);
    3b2e:	954a      	ld.w      	r2, (r5, 0x28)
    3b30:	a840      	st.h      	r2, (r0, 0)
			DataJ++;
    3b32:	2300      	addi      	r3, 1
			*destAddress_u16++ = CSP_USART_GET_RHR(USART0);
    3b34:	2001      	addi      	r0, 2
			LoopTime = 0;
    3b36:	3200      	movi      	r2, 0
		if(LoopTime ++ >= 0xfff0)
    3b38:	649c      	cmphs      	r7, r2
    3b3a:	5a82      	addi      	r4, r2, 1
    3b3c:	0c07      	bf      	0x3b4a	// 3b4a <USARTReceive+0x32>
			return FALSE;
	}while(DataJ < length_u16);
    3b3e:	644c      	cmphs      	r3, r1
    3b40:	0ff3      	bf      	0x3b26	// 3b26 <USARTReceive+0xe>
	return TRUE;
    3b42:	3001      	movi      	r0, 1
}
    3b44:	1484      	pop      	r4-r7
    3b46:	6c93      	mov      	r2, r4
    3b48:	07f8      	br      	0x3b38	// 3b38 <USARTReceive+0x20>
			return FALSE;
    3b4a:	3000      	movi      	r0, 0
    3b4c:	07fc      	br      	0x3b44	// 3b44 <USARTReceive+0x2c>
    3b4e:	0000      	bkpt
    3b50:	20000014 	.long	0x20000014
    3b54:	20000075 	.long	0x20000075
    3b58:	0000ffef 	.long	0x0000ffef

00003b5c <SPI_DeInit>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_DeInit(void)
{
    SPI0->CR0   	= SPI_CR0_RST;
    3b5c:	1069      	lrw      	r3, 0x2000000c	// 3b80 <SPI_DeInit+0x24>
    3b5e:	3200      	movi      	r2, 0
    3b60:	9360      	ld.w      	r3, (r3, 0)
    3b62:	b340      	st.w      	r2, (r3, 0)
    SPI0->CR1   	= SPI_CR1_RST;
    3b64:	b341      	st.w      	r2, (r3, 0x4)
    SPI0->DR   	 	= SPI_DR_RST;
    3b66:	b342      	st.w      	r2, (r3, 0x8)
    SPI0->SR   	 	= SPI_SR_RST;
    3b68:	3203      	movi      	r2, 3
    3b6a:	b343      	st.w      	r2, (r3, 0xc)
    SPI0->CPSR   	= SPI_CPSR_RST;
    3b6c:	3200      	movi      	r2, 0
    3b6e:	b344      	st.w      	r2, (r3, 0x10)
    SPI0->IMSCR   	= SPI_IMSCR_RST;
    3b70:	b345      	st.w      	r2, (r3, 0x14)
    SPI0->RISR   	= SPI_RISR_RST;
    3b72:	3208      	movi      	r2, 8
    3b74:	b346      	st.w      	r2, (r3, 0x18)
    SPI0->MISR   	= SPI_MISR_RST;
    3b76:	3200      	movi      	r2, 0
    3b78:	b347      	st.w      	r2, (r3, 0x1c)
    SPI0->ICR	 	= SPI_ICR_RST;
    3b7a:	b348      	st.w      	r2, (r3, 0x20)
}
    3b7c:	783c      	rts
    3b7e:	0000      	bkpt
    3b80:	2000000c 	.long	0x2000000c

00003b84 <SPI_NSS_IO_Init>:
//SPI_NSS_IO_GROUP:0~2
//ReturnValue:NONE
/*************************************************************/
void SPI_NSS_IO_Init(U8_T SPI_NSS_IO_GROUP)
{
	if(SPI_NSS_IO_GROUP==0)
    3b84:	3840      	cmpnei      	r0, 0
    3b86:	0809      	bt      	0x3b98	// 3b98 <SPI_NSS_IO_Init+0x14>
	{
		GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFFFFF0)  | 0x00000004;				//PC0.0
    3b88:	1365      	lrw      	r3, 0x20000044	// 3d1c <SPI_Wakeup_Disable+0x14>
    3b8a:	310f      	movi      	r1, 15
    3b8c:	9340      	ld.w      	r2, (r3, 0)
    3b8e:	9260      	ld.w      	r3, (r2, 0)
    3b90:	68c5      	andn      	r3, r1
    3b92:	3ba2      	bseti      	r3, r3, 2
	{
		GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)  | 0x60000000;				//PA0.7
	}
	else if(SPI_NSS_IO_GROUP==2)
	{
		GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0)  | 0x00000005;				//PB0.0
    3b94:	b260      	st.w      	r3, (r2, 0)
	}
}
    3b96:	783c      	rts
	else if(SPI_NSS_IO_GROUP==1)
    3b98:	3841      	cmpnei      	r0, 1
    3b9a:	0809      	bt      	0x3bac	// 3bac <SPI_NSS_IO_Init+0x28>
		GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)  | 0x60000000;				//PA0.7
    3b9c:	1361      	lrw      	r3, 0x20000050	// 3d20 <SPI_Wakeup_Disable+0x18>
    3b9e:	9340      	ld.w      	r2, (r3, 0)
    3ba0:	9260      	ld.w      	r3, (r2, 0)
    3ba2:	4364      	lsli      	r3, r3, 4
    3ba4:	4b64      	lsri      	r3, r3, 4
    3ba6:	3bbd      	bseti      	r3, r3, 29
    3ba8:	3bbe      	bseti      	r3, r3, 30
    3baa:	07f5      	br      	0x3b94	// 3b94 <SPI_NSS_IO_Init+0x10>
	else if(SPI_NSS_IO_GROUP==2)
    3bac:	3842      	cmpnei      	r0, 2
    3bae:	0bf4      	bt      	0x3b96	// 3b96 <SPI_NSS_IO_Init+0x12>
		GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0)  | 0x00000005;				//PB0.0
    3bb0:	127d      	lrw      	r3, 0x20000048	// 3d24 <SPI_Wakeup_Disable+0x1c>
    3bb2:	310f      	movi      	r1, 15
    3bb4:	9340      	ld.w      	r2, (r3, 0)
    3bb6:	9260      	ld.w      	r3, (r2, 0)
    3bb8:	68c5      	andn      	r3, r1
    3bba:	3ba0      	bseti      	r3, r3, 0
    3bbc:	3ba2      	bseti      	r3, r3, 2
    3bbe:	07eb      	br      	0x3b94	// 3b94 <SPI_NSS_IO_Init+0x10>

00003bc0 <SPI_Master_Init>:
//ReturnValue:NONE
/*************************************************************/
//SPI波特率:FSSPCLK = FPCLK / (CPSDVR × (1 + SCR))
//FPCLK (max) → 2 × FSSPCLKOUT (max)主机	最快波特率
void SPI_Master_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPO_TypeDef SPI_SPO_X , SPI_SPH_TypeDef SPI_SPH_X , SPI_LBM_TypeDef SPI_LBM_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR )
{
    3bc0:	14c4      	push      	r4-r7
    3bc2:	1422      	subi      	sp, sp, 8
    3bc4:	9886      	ld.w      	r4, (sp, 0x18)
    3bc6:	b880      	st.w      	r4, (sp, 0)
    3bc8:	9887      	ld.w      	r4, (sp, 0x1c)
    3bca:	b881      	st.w      	r4, (sp, 0x4)
    3bcc:	1d09      	addi      	r5, sp, 36
    3bce:	1c08      	addi      	r4, sp, 32
	//U16_T rdata=0;
	if (SPI_IO==SPI_G0)
    3bd0:	3840      	cmpnei      	r0, 0
{
    3bd2:	8480      	ld.b      	r4, (r4, 0)
    3bd4:	85a0      	ld.b      	r5, (r5, 0)
	if (SPI_IO==SPI_G0)
    3bd6:	081f      	bt      	0x3c14	// 3c14 <SPI_Master_Init+0x54>
    {
		GPIOA1->CONLR = (GPIOA1->CONLR&0XFF000FFF)  | 0x00444000;            //PA1.3->SPI_SCK,PA1.4->SPI_MISO,PA1.5->SPI_MOSI
    3bd8:	1214      	lrw      	r0, 0x2000004c	// 3d28 <SPI_Wakeup_Disable+0x20>
    3bda:	12f5      	lrw      	r7, 0xfff000	// 3d2c <SPI_Wakeup_Disable+0x24>
    3bdc:	90c0      	ld.w      	r6, (r0, 0)
    3bde:	9600      	ld.w      	r0, (r6, 0)
    3be0:	681d      	andn      	r0, r7
    3be2:	12f4      	lrw      	r7, 0x444000	// 3d30 <SPI_Wakeup_Disable+0x28>
    3be4:	6c1c      	or      	r0, r7
    3be6:	b600      	st.w      	r0, (r6, 0)
    }
    else if(SPI_IO==SPI_G1)
    {
		GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF000)  | 0x00000666;            //PA0.8->SPI_SCK,PA0.9->SPI_MISO,PA0.10->SPI_MOSI
    }
	SPI0->CR0|=SPI_DATA_SIZE_x|(SPI_SPO_X<<6)|(SPI_SPH_X<<7)|(SPI_SCR<<8);
    3be8:	1213      	lrw      	r0, 0x2000000c	// 3d34 <SPI_Wakeup_Disable+0x2c>
    3bea:	4367      	lsli      	r3, r3, 7
    3bec:	9000      	ld.w      	r0, (r0, 0)
    3bee:	90c0      	ld.w      	r6, (r0, 0)
    3bf0:	6cc4      	or      	r3, r1
    3bf2:	6d8c      	or      	r6, r3
    3bf4:	4488      	lsli      	r4, r4, 8
    3bf6:	6d18      	or      	r4, r6
    3bf8:	4246      	lsli      	r2, r2, 6
    3bfa:	6c90      	or      	r2, r4
    3bfc:	b040      	st.w      	r2, (r0, 0)
	SPI0->CPSR=SPI_CPSDVSR;
    3bfe:	b0a4      	st.w      	r5, (r0, 0x10)
	SPI0->CR1|=0X02|SPI_LBM_X|(SPI_RXIFLSEL_X<<4);
    3c00:	9061      	ld.w      	r3, (r0, 0x4)
    3c02:	9840      	ld.w      	r2, (sp, 0)
    3c04:	3ba1      	bseti      	r3, r3, 1
    3c06:	6cc8      	or      	r3, r2
    3c08:	9841      	ld.w      	r2, (sp, 0x4)
    3c0a:	4244      	lsli      	r2, r2, 4
    3c0c:	6cc8      	or      	r3, r2
    3c0e:	b061      	st.w      	r3, (r0, 0x4)
	//rdata=SPI0->DR;
}
    3c10:	1402      	addi      	sp, sp, 8
    3c12:	1484      	pop      	r4-r7
    else if(SPI_IO==SPI_G1)
    3c14:	3841      	cmpnei      	r0, 1
    3c16:	0be9      	bt      	0x3be8	// 3be8 <SPI_Master_Init+0x28>
		GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF000)  | 0x00000666;            //PA0.8->SPI_SCK,PA0.9->SPI_MISO,PA0.10->SPI_MOSI
    3c18:	1202      	lrw      	r0, 0x20000050	// 3d20 <SPI_Wakeup_Disable+0x18>
    3c1a:	12e8      	lrw      	r7, 0xfff	// 3d38 <SPI_Wakeup_Disable+0x30>
    3c1c:	90c0      	ld.w      	r6, (r0, 0)
    3c1e:	9601      	ld.w      	r0, (r6, 0x4)
    3c20:	681d      	andn      	r0, r7
    3c22:	12e7      	lrw      	r7, 0x666	// 3d3c <SPI_Wakeup_Disable+0x34>
    3c24:	6c1c      	or      	r0, r7
    3c26:	b601      	st.w      	r0, (r6, 0x4)
    3c28:	07e0      	br      	0x3be8	// 3be8 <SPI_Master_Init+0x28>

00003c2a <SPI_Slave_Init>:
//ReturnValue:NONE
/*************************************************************/
//SPI波特率:FSSPCLK = FPCLK / (CPSDVR × (1 + SCR))
//FPCLK (max) → 12 × FSSPCLKIN (max)从机	最快波特率
void SPI_Slave_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR)
{
    3c2a:	14c3      	push      	r4-r6
	//U16_T rdata=0;
	if (SPI_IO==SPI_G0)
    3c2c:	3840      	cmpnei      	r0, 0
{
    3c2e:	d88e000c 	ld.b      	r4, (sp, 0xc)
	if (SPI_IO==SPI_G0)
    3c32:	0818      	bt      	0x3c62	// 3c62 <SPI_Slave_Init+0x38>
    {
		GPIOA1->CONLR = (GPIOA1->CONLR&0XFF000FFF)  | 0x00444000;            //PA1.3->SPI_SCK,PA1.4->SPI_MISO,PA1.5->SPI_MOSI
    3c34:	111d      	lrw      	r0, 0x2000004c	// 3d28 <SPI_Wakeup_Disable+0x20>
    3c36:	11de      	lrw      	r6, 0xfff000	// 3d2c <SPI_Wakeup_Disable+0x24>
    3c38:	90a0      	ld.w      	r5, (r0, 0)
    3c3a:	9500      	ld.w      	r0, (r5, 0)
    3c3c:	6819      	andn      	r0, r6
    3c3e:	11dd      	lrw      	r6, 0x444000	// 3d30 <SPI_Wakeup_Disable+0x28>
    3c40:	6c18      	or      	r0, r6
    3c42:	b500      	st.w      	r0, (r5, 0)
    }
    else if(SPI_IO==SPI_G1)
    {
		GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF000)  | 0x00000666;            //PA0.8->SPI_SCK,PA0.9->SPI_MISO,PA0.9->SPI_MOSI
    }
	SPI0->CR0|=SPI_DATA_SIZE_x|(SPI_SCR<<8);
    3c44:	111c      	lrw      	r0, 0x2000000c	// 3d34 <SPI_Wakeup_Disable+0x2c>
    3c46:	4368      	lsli      	r3, r3, 8
    3c48:	9000      	ld.w      	r0, (r0, 0)
    3c4a:	90a0      	ld.w      	r5, (r0, 0)
    3c4c:	6c54      	or      	r1, r5
    3c4e:	6cc4      	or      	r3, r1
    3c50:	b060      	st.w      	r3, (r0, 0)
	SPI0->CPSR=SPI_CPSDVSR;
    3c52:	b084      	st.w      	r4, (r0, 0x10)
	SPI0->CR1|=0X06|(SPI_RXIFLSEL_X<<4);
    3c54:	9061      	ld.w      	r3, (r0, 0x4)
    3c56:	3ba1      	bseti      	r3, r3, 1
    3c58:	3ba2      	bseti      	r3, r3, 2
    3c5a:	4244      	lsli      	r2, r2, 4
    3c5c:	6c8c      	or      	r2, r3
    3c5e:	b041      	st.w      	r2, (r0, 0x4)
	//rdata=SPI0->DR;
}
    3c60:	1483      	pop      	r4-r6
    else if(SPI_IO==SPI_G1)
    3c62:	3841      	cmpnei      	r0, 1
    3c64:	0bf0      	bt      	0x3c44	// 3c44 <SPI_Slave_Init+0x1a>
		GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF000)  | 0x00000666;            //PA0.8->SPI_SCK,PA0.9->SPI_MISO,PA0.9->SPI_MOSI
    3c66:	110f      	lrw      	r0, 0x20000050	// 3d20 <SPI_Wakeup_Disable+0x18>
    3c68:	11d4      	lrw      	r6, 0xfff	// 3d38 <SPI_Wakeup_Disable+0x30>
    3c6a:	90a0      	ld.w      	r5, (r0, 0)
    3c6c:	9501      	ld.w      	r0, (r5, 0x4)
    3c6e:	6819      	andn      	r0, r6
    3c70:	11d3      	lrw      	r6, 0x666	// 3d3c <SPI_Wakeup_Disable+0x34>
    3c72:	6c18      	or      	r0, r6
    3c74:	b501      	st.w      	r0, (r5, 0x4)
    3c76:	07e7      	br      	0x3c44	// 3c44 <SPI_Slave_Init+0x1a>

00003c78 <SPI_WRITE_BYTE>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_WRITE_BYTE(U16_T wdata)
{
	while(((SPI0->SR) & SSP_TNF) != SSP_TNF);	
    3c78:	116f      	lrw      	r3, 0x2000000c	// 3d34 <SPI_Wakeup_Disable+0x2c>
    3c7a:	3102      	movi      	r1, 2
    3c7c:	9340      	ld.w      	r2, (r3, 0)
    3c7e:	9263      	ld.w      	r3, (r2, 0xc)
    3c80:	68c4      	and      	r3, r1
    3c82:	3b40      	cmpnei      	r3, 0
    3c84:	0ffd      	bf      	0x3c7e	// 3c7e <SPI_WRITE_BYTE+0x6>
	SPI0->DR = wdata;
    3c86:	b202      	st.w      	r0, (r2, 0x8)
	while(((SPI0->SR) & SSP_BSY) == SSP_BSY);		//wait for transmition finish
    3c88:	3110      	movi      	r1, 16
    3c8a:	9263      	ld.w      	r3, (r2, 0xc)
    3c8c:	68c4      	and      	r3, r1
    3c8e:	3b40      	cmpnei      	r3, 0
    3c90:	0bfd      	bt      	0x3c8a	// 3c8a <SPI_WRITE_BYTE+0x12>
}
    3c92:	783c      	rts

00003c94 <SPI_READ_BYTE>:

U16_T SPI_READ_BYTE(U16_T wdata)
{
	U16_T rdata=0;
	while(((SPI0->SR) & SSP_TNF) != SSP_TNF);	
    3c94:	1168      	lrw      	r3, 0x2000000c	// 3d34 <SPI_Wakeup_Disable+0x2c>
    3c96:	3102      	movi      	r1, 2
    3c98:	9360      	ld.w      	r3, (r3, 0)
    3c9a:	9343      	ld.w      	r2, (r3, 0xc)
    3c9c:	6884      	and      	r2, r1
    3c9e:	3a40      	cmpnei      	r2, 0
    3ca0:	0ffd      	bf      	0x3c9a	// 3c9a <SPI_READ_BYTE+0x6>
	SPI0->DR = wdata;
    3ca2:	b302      	st.w      	r0, (r3, 0x8)
	while(((SPI0->SR) & SSP_RNE) != SSP_RNE);	
    3ca4:	3104      	movi      	r1, 4
    3ca6:	9343      	ld.w      	r2, (r3, 0xc)
    3ca8:	6884      	and      	r2, r1
    3caa:	3a40      	cmpnei      	r2, 0
    3cac:	0ffd      	bf      	0x3ca6	// 3ca6 <SPI_READ_BYTE+0x12>
	rdata = SPI0->DR;  	//get data from FIFO
    3cae:	9302      	ld.w      	r0, (r3, 0x8)
    3cb0:	7401      	zexth      	r0, r0
	while(((SPI0->SR) & SSP_BSY) == SSP_BSY);		//wait for transmition finish
    3cb2:	3110      	movi      	r1, 16
    3cb4:	9343      	ld.w      	r2, (r3, 0xc)
    3cb6:	6884      	and      	r2, r1
    3cb8:	3a40      	cmpnei      	r2, 0
    3cba:	0bfd      	bt      	0x3cb4	// 3cb4 <SPI_READ_BYTE+0x20>
	return rdata;
}
    3cbc:	783c      	rts

00003cbe <SPI_ConfigInterrupt_CMD>:
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void SPI_ConfigInterrupt_CMD(SPI_IMSCR_TypeDef SPI_IMSCR_X , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
    3cbe:	3940      	cmpnei      	r1, 0
    3cc0:	107d      	lrw      	r3, 0x2000000c	// 3d34 <SPI_Wakeup_Disable+0x2c>
    3cc2:	0c06      	bf      	0x3cce	// 3cce <SPI_ConfigInterrupt_CMD+0x10>
	{
		SPI0->IMSCR  |= SPI_IMSCR_X;						//SET
    3cc4:	9340      	ld.w      	r2, (r3, 0)
    3cc6:	9265      	ld.w      	r3, (r2, 0x14)
    3cc8:	6c0c      	or      	r0, r3
    3cca:	b205      	st.w      	r0, (r2, 0x14)
	}
	else
	{
		SPI0->IMSCR  &= ~SPI_IMSCR_X;					//CLR
	}
}   
    3ccc:	783c      	rts
		SPI0->IMSCR  &= ~SPI_IMSCR_X;					//CLR
    3cce:	9360      	ld.w      	r3, (r3, 0)
    3cd0:	9345      	ld.w      	r2, (r3, 0x14)
    3cd2:	6c02      	nor      	r0, r0
    3cd4:	6808      	and      	r0, r2
    3cd6:	b305      	st.w      	r0, (r3, 0x14)
}   
    3cd8:	07fa      	br      	0x3ccc	// 3ccc <SPI_ConfigInterrupt_CMD+0xe>

00003cda <SPI_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_Int_Enable(void)
{
    INTC_ISER_WRITE(SPI_INT);    
    3cda:	107a      	lrw      	r3, 0x20000064	// 3d40 <SPI_Wakeup_Disable+0x38>
    3cdc:	3280      	movi      	r2, 128
    3cde:	9360      	ld.w      	r3, (r3, 0)
    3ce0:	23ff      	addi      	r3, 256
    3ce2:	424c      	lsli      	r2, r2, 12
    3ce4:	b340      	st.w      	r2, (r3, 0)
}
    3ce6:	783c      	rts

00003ce8 <SPI_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_Int_Disable(void)
{
    INTC_ICER_WRITE(SPI_INT);    
    3ce8:	1076      	lrw      	r3, 0x20000064	// 3d40 <SPI_Wakeup_Disable+0x38>
    3cea:	32c0      	movi      	r2, 192
    3cec:	9360      	ld.w      	r3, (r3, 0)
    3cee:	4241      	lsli      	r2, r2, 1
    3cf0:	60c8      	addu      	r3, r2
    3cf2:	3280      	movi      	r2, 128
    3cf4:	424c      	lsli      	r2, r2, 12
    3cf6:	b340      	st.w      	r2, (r3, 0)
}
    3cf8:	783c      	rts

00003cfa <SPI_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(SPI_INT);    
    3cfa:	1072      	lrw      	r3, 0x20000064	// 3d40 <SPI_Wakeup_Disable+0x38>
    3cfc:	3280      	movi      	r2, 128
    3cfe:	9360      	ld.w      	r3, (r3, 0)
    3d00:	23ff      	addi      	r3, 256
    3d02:	424c      	lsli      	r2, r2, 12
    3d04:	b350      	st.w      	r2, (r3, 0x40)
}
    3d06:	783c      	rts

00003d08 <SPI_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(SPI_INT);    
    3d08:	106e      	lrw      	r3, 0x20000064	// 3d40 <SPI_Wakeup_Disable+0x38>
    3d0a:	32e0      	movi      	r2, 224
    3d0c:	9360      	ld.w      	r3, (r3, 0)
    3d0e:	4241      	lsli      	r2, r2, 1
    3d10:	60c8      	addu      	r3, r2
    3d12:	3280      	movi      	r2, 128
    3d14:	424c      	lsli      	r2, r2, 12
    3d16:	b340      	st.w      	r2, (r3, 0)
}
    3d18:	783c      	rts
    3d1a:	0000      	bkpt
    3d1c:	20000044 	.long	0x20000044
    3d20:	20000050 	.long	0x20000050
    3d24:	20000048 	.long	0x20000048
    3d28:	2000004c 	.long	0x2000004c
    3d2c:	00fff000 	.long	0x00fff000
    3d30:	00444000 	.long	0x00444000
    3d34:	2000000c 	.long	0x2000000c
    3d38:	00000fff 	.long	0x00000fff
    3d3c:	00000666 	.long	0x00000666
    3d40:	20000064 	.long	0x20000064

00003d44 <ADC12_RESET_VALUE>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void ADC12_RESET_VALUE(void)
{
	 ADC0->ECR	=	ADC_ECR_RST;     				/**< ECR  reset value  */
    3d44:	107a      	lrw      	r3, 0x20000054	// 3dac <ADC12_RESET_VALUE+0x68>
    3d46:	3200      	movi      	r2, 0
    3d48:	9360      	ld.w      	r3, (r3, 0)
    3d4a:	b340      	st.w      	r2, (r3, 0)
	 ADC0->DCR	=	ADC_DCR_RST;                  	/**< DCR  reset value  */
    3d4c:	b341      	st.w      	r2, (r3, 0x4)
	 ADC0->PMSR	= 	ADC_PMSR_RST;       		  	/**< PMSR reset value  */
    3d4e:	b342      	st.w      	r2, (r3, 0x8)
	 ADC0->CR	=	ADC_CR_RST;             		/**< CR   reset value  */
    3d50:	1058      	lrw      	r2, 0x80000040	// 3db0 <ADC12_RESET_VALUE+0x6c>
    3d52:	b344      	st.w      	r2, (r3, 0x10)
	 ADC0->MR	=   ADC_MR_RST;                  	/**< MR   reset value  */
    3d54:	3200      	movi      	r2, 0
    3d56:	b345      	st.w      	r2, (r3, 0x14)
	 ADC0->CSR	=   ADC_CSR_RST;                  	/**< CSR  reset value  */
    3d58:	b347      	st.w      	r2, (r3, 0x1c)
	 ADC0->SR 	=	ADC_SR_RST;                   	/**< SR   reset value  */
    3d5a:	b348      	st.w      	r2, (r3, 0x20)
	 ADC0->IER 	=	ADC_IER_RST;                	/**< IER  reset value  */
    3d5c:	b349      	st.w      	r2, (r3, 0x24)
	 ADC0->IDR 	=	ADC_IDR_RST;              		/**< IDR  reset value  */
    3d5e:	b34a      	st.w      	r2, (r3, 0x28)
	 ADC0->IMR  	=	ADC_IMR_RST;               		/**< IMR  reset value  */
    3d60:	b34b      	st.w      	r2, (r3, 0x2c)
	 ADC0->SEQ[0]=	ADC_SEQx_RST;             		/**< SEQ0  reset value */
    3d62:	b34c      	st.w      	r2, (r3, 0x30)
	 ADC0->SEQ[1]=	ADC_SEQx_RST;             		/**< SEQ1  reset value */
    3d64:	b34d      	st.w      	r2, (r3, 0x34)
	 ADC0->SEQ[2]=	ADC_SEQx_RST;             		/**< SEQ2  reset value */
    3d66:	b34e      	st.w      	r2, (r3, 0x38)
	 ADC0->SEQ[3]=	ADC_SEQx_RST;             		/**< SEQ3  reset value */
    3d68:	b34f      	st.w      	r2, (r3, 0x3c)
	 ADC0->SEQ[4]=	ADC_SEQx_RST;             		/**< SEQ4  reset value */
    3d6a:	b350      	st.w      	r2, (r3, 0x40)
	 ADC0->SEQ[5]=	ADC_SEQx_RST;             		/**< SEQ5  reset value */
    3d6c:	b351      	st.w      	r2, (r3, 0x44)
	 ADC0->SEQ[6]=	ADC_SEQx_RST;             		/**< SEQ6  reset value */
    3d6e:	b352      	st.w      	r2, (r3, 0x48)
	 ADC0->SEQ[7]=	ADC_SEQx_RST;             		/**< SEQ7  reset value */
    3d70:	b353      	st.w      	r2, (r3, 0x4c)
	 ADC0->SEQ[8]=	ADC_SEQx_RST;             		/**< SEQ8  reset value */
    3d72:	b354      	st.w      	r2, (r3, 0x50)
	 ADC0->SEQ[9]=	ADC_SEQx_RST;             		/**< SEQ9  reset value */
    3d74:	b355      	st.w      	r2, (r3, 0x54)
	 ADC0->SEQ[10]=	ADC_SEQx_RST;             		/**< SEQ10  reset value */
    3d76:	b356      	st.w      	r2, (r3, 0x58)
	 ADC0->SEQ[11]=	ADC_SEQx_RST;             		/**< SEQ11  reset value */
    3d78:	b357      	st.w      	r2, (r3, 0x5c)
	 ADC0->SEQ[12]=	ADC_SEQx_RST;             		/**< SEQ12  reset value */
    3d7a:	b358      	st.w      	r2, (r3, 0x60)
	 ADC0->SEQ[13]=	ADC_SEQx_RST;             		/**< SEQ13  reset value */
    3d7c:	b359      	st.w      	r2, (r3, 0x64)
	 ADC0->SEQ[14]=	ADC_SEQx_RST;             		/**< SEQ14  reset value */
    3d7e:	b35a      	st.w      	r2, (r3, 0x68)
	 ADC0->SEQ[15]=	ADC_SEQx_RST;             		/**< SEQ15  reset value */
    3d80:	b35b      	st.w      	r2, (r3, 0x6c)
	 ADC0->DR[0]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d82:	23ff      	addi      	r3, 256
    3d84:	b340      	st.w      	r2, (r3, 0)
	 ADC0->DR[1]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d86:	b341      	st.w      	r2, (r3, 0x4)
	 ADC0->DR[2]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d88:	b342      	st.w      	r2, (r3, 0x8)
	 ADC0->DR[3]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d8a:	b343      	st.w      	r2, (r3, 0xc)
	 ADC0->DR[4]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d8c:	b344      	st.w      	r2, (r3, 0x10)
	 ADC0->DR[5]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d8e:	b345      	st.w      	r2, (r3, 0x14)
	 ADC0->DR[6]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d90:	b346      	st.w      	r2, (r3, 0x18)
	 ADC0->DR[7]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d92:	b347      	st.w      	r2, (r3, 0x1c)
	 ADC0->DR[8]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d94:	b348      	st.w      	r2, (r3, 0x20)
	 ADC0->DR[9]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d96:	b349      	st.w      	r2, (r3, 0x24)
	 ADC0->DR[10]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d98:	b34a      	st.w      	r2, (r3, 0x28)
	 ADC0->DR[11]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d9a:	b34b      	st.w      	r2, (r3, 0x2c)
	 ADC0->DR[12]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d9c:	b34c      	st.w      	r2, (r3, 0x30)
	 ADC0->DR[13]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3d9e:	b34d      	st.w      	r2, (r3, 0x34)
	 ADC0->DR[14]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3da0:	b34e      	st.w      	r2, (r3, 0x38)
	 ADC0->DR[15]  =	ADC_DR_RST;                		/**< DR   reset value  */
    3da2:	b34f      	st.w      	r2, (r3, 0x3c)
	 ADC0->CMP0   =	ADC_CMP0_RST;               	/**< CMP1 reset value  */
    3da4:	b350      	st.w      	r2, (r3, 0x40)
	 ADC0->CMP1   =	ADC_CMP1_RST;                	/**< CMP2 reset value  */
    3da6:	b351      	st.w      	r2, (r3, 0x44)
}  
    3da8:	783c      	rts
    3daa:	0000      	bkpt
    3dac:	20000054 	.long	0x20000054
    3db0:	80000040 	.long	0x80000040

00003db4 <ADC12_read_IPIDCODE>:
//EntryParameter:NONE
//ReturnValue:ADC IPIDCODE
/*************************************************************/  
U32_T ADC12_read_IPIDCODE(void)
{
	return (ADC0->PMSR&ADC12_IPIDCODE_MASK);
    3db4:	1366      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3db6:	9360      	ld.w      	r3, (r3, 0)
    3db8:	9302      	ld.w      	r0, (r3, 0x8)
    3dba:	1366      	lrw      	r3, 0x3fffffff	// 3f50 <ADC12_Configure_VREF_FVR+0x6>
    3dbc:	2b0e      	subi      	r3, 15
    3dbe:	680c      	and      	r0, r3
}  
    3dc0:	783c      	rts

00003dc2 <ADC12_Control>:
//ReturnValue:NONE
/*************************************************************/  
  //control:ADC enable/disable ,start/stop,swrst
void ADC12_Control(ADC12_Control_TypeDef ADC12_Control_x )
{
	ADC0->CR |= ADC12_Control_x;							// 
    3dc2:	1363      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3dc4:	9340      	ld.w      	r2, (r3, 0)
    3dc6:	9264      	ld.w      	r3, (r2, 0x10)
    3dc8:	6c0c      	or      	r0, r3
    3dca:	b204      	st.w      	r0, (r2, 0x10)
}
    3dcc:	783c      	rts

00003dce <ADC12_CMD.part.0>:
//ADC12 ENABLE
//EntryParameter:NewState
//NewState:ENABLE , DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void ADC12_CMD(FunctionalStatus NewState)
    3dce:	14d0      	push      	r15
{
	if (NewState != DISABLE)
	{
		ADC12_Control(ADC12_ADCEN);						//ADC12 ENABLE
    3dd0:	3002      	movi      	r0, 2
    3dd2:	e3fffff8 	bsr      	0x3dc2	// 3dc2 <ADC12_Control>
		while(!(ADC0->SR &ADC12_ADCENS));
    3dd6:	127e      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3dd8:	3280      	movi      	r2, 128
    3dda:	9320      	ld.w      	r1, (r3, 0)
    3ddc:	4241      	lsli      	r2, r2, 1
    3dde:	9168      	ld.w      	r3, (r1, 0x20)
    3de0:	68c8      	and      	r3, r2
    3de2:	3b40      	cmpnei      	r3, 0
    3de4:	0ffd      	bf      	0x3dde	// 3dde <ADC12_CMD.part.0+0x10>
	else
	{
		ADC12_Control(ADC12_ADCDIS);					//ADC12 DISABLE
		while(ADC0->SR&ADC12_ADCENS);
	}
}
    3de6:	1490      	pop      	r15

00003de8 <ADC12_ConfigInterrupt_CMD>:
	if (NewState != DISABLE)
    3de8:	3940      	cmpnei      	r1, 0
    3dea:	1279      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3dec:	0c06      	bf      	0x3df8	// 3df8 <ADC12_ConfigInterrupt_CMD+0x10>
		ADC0->IER  |= ADC_IMR_X;						//SET
    3dee:	9340      	ld.w      	r2, (r3, 0)
    3df0:	9269      	ld.w      	r3, (r2, 0x24)
    3df2:	6c0c      	or      	r0, r3
    3df4:	b209      	st.w      	r0, (r2, 0x24)
} 
    3df6:	783c      	rts
		ADC0->IDR  |= ADC_IMR_X;						//CLR
    3df8:	9360      	ld.w      	r3, (r3, 0)
    3dfa:	934a      	ld.w      	r2, (r3, 0x28)
    3dfc:	6c08      	or      	r0, r2
    3dfe:	b30a      	st.w      	r0, (r3, 0x28)
} 
    3e00:	07fb      	br      	0x3df6	// 3df6 <ADC12_ConfigInterrupt_CMD+0xe>

00003e02 <ADC12_Read_IntEnStatus>:
    dat= ADC0->IMR&EnStatus_bit;
    3e02:	1273      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3e04:	9360      	ld.w      	r3, (r3, 0)
    3e06:	936b      	ld.w      	r3, (r3, 0x2c)
    3e08:	68c0      	and      	r3, r0
    if (dat == EnStatus_bit)								
    3e0a:	640e      	cmpne      	r3, r0
    return value;
    3e0c:	6403      	mvcv      	r0
}
    3e0e:	783c      	rts

00003e10 <ADC12_CLK_CMD>:
	if (NewState != DISABLE)
    3e10:	3940      	cmpnei      	r1, 0
    3e12:	126f      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
		ADC0->ECR  |= ADC_CLK_CMD;						//ENABLE
    3e14:	9340      	ld.w      	r2, (r3, 0)
	if (NewState != DISABLE)
    3e16:	0c09      	bf      	0x3e28	// 3e28 <ADC12_CLK_CMD+0x18>
		ADC0->ECR  |= ADC_CLK_CMD;						//ENABLE
    3e18:	9260      	ld.w      	r3, (r2, 0)
    3e1a:	6cc0      	or      	r3, r0
    3e1c:	b260      	st.w      	r3, (r2, 0)
		while(!(ADC0->PMSR&ADC_CLK_CMD));
    3e1e:	9262      	ld.w      	r3, (r2, 0x8)
    3e20:	68c0      	and      	r3, r0
    3e22:	3b40      	cmpnei      	r3, 0
    3e24:	0ffd      	bf      	0x3e1e	// 3e1e <ADC12_CLK_CMD+0xe>
}
    3e26:	783c      	rts
		ADC0->DCR  |= ADC_CLK_CMD;						//DISABLE
    3e28:	9261      	ld.w      	r3, (r2, 0x4)
    3e2a:	6cc0      	or      	r3, r0
    3e2c:	b261      	st.w      	r3, (r2, 0x4)
		while(ADC0->PMSR&ADC_CLK_CMD);
    3e2e:	9262      	ld.w      	r3, (r2, 0x8)
    3e30:	68c0      	and      	r3, r0
    3e32:	3b40      	cmpnei      	r3, 0
    3e34:	0bfd      	bt      	0x3e2e	// 3e2e <ADC12_CLK_CMD+0x1e>
    3e36:	07f8      	br      	0x3e26	// 3e26 <ADC12_CLK_CMD+0x16>

00003e38 <ADC12_Software_Reset>:
{
    3e38:	14d0      	push      	r15
	ADC12_Control(ADC12_SWRST);
    3e3a:	3001      	movi      	r0, 1
    3e3c:	e3ffffc3 	bsr      	0x3dc2	// 3dc2 <ADC12_Control>
}
    3e40:	1490      	pop      	r15

00003e42 <ADC12_CMD>:
{
    3e42:	14d0      	push      	r15
	if (NewState != DISABLE)
    3e44:	3840      	cmpnei      	r0, 0
    3e46:	0c04      	bf      	0x3e4e	// 3e4e <ADC12_CMD+0xc>
    3e48:	e3ffffc3 	bsr      	0x3dce	// 3dce <ADC12_CMD.part.0>
}
    3e4c:	1490      	pop      	r15
		ADC12_Control(ADC12_ADCDIS);					//ADC12 DISABLE
    3e4e:	3004      	movi      	r0, 4
    3e50:	e3ffffb9 	bsr      	0x3dc2	// 3dc2 <ADC12_Control>
		while(ADC0->SR&ADC12_ADCENS);
    3e54:	117e      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3e56:	3280      	movi      	r2, 128
    3e58:	9320      	ld.w      	r1, (r3, 0)
    3e5a:	4241      	lsli      	r2, r2, 1
    3e5c:	9168      	ld.w      	r3, (r1, 0x20)
    3e5e:	68c8      	and      	r3, r2
    3e60:	3b40      	cmpnei      	r3, 0
    3e62:	0bfd      	bt      	0x3e5c	// 3e5c <ADC12_CMD+0x1a>
    3e64:	07f4      	br      	0x3e4c	// 3e4c <ADC12_CMD+0xa>

00003e66 <ADC12_ready_wait>:
//EntryParameter:NONE
//ReturnValue:ADC12 READ FLAG
/*************************************************************/ 
void ADC12_ready_wait(void)  
{
	while(!(ADC0->SR&ADC12_READY));   					// Waiting for ADC0 Ready
    3e66:	117a      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3e68:	3202      	movi      	r2, 2
    3e6a:	9320      	ld.w      	r1, (r3, 0)
    3e6c:	9168      	ld.w      	r3, (r1, 0x20)
    3e6e:	68c8      	and      	r3, r2
    3e70:	3b40      	cmpnei      	r3, 0
    3e72:	0ffd      	bf      	0x3e6c	// 3e6c <ADC12_ready_wait+0x6>
}
    3e74:	783c      	rts

00003e76 <ADC12_EOC_wait>:
//EntryParameter:NONE
//ReturnValue:ADC12 EOC
/*************************************************************/ 
void ADC12_EOC_wait(void)
{
	while(!(ADC0->SR & ADC12_EOC));			// EOC wait
    3e76:	1176      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3e78:	3201      	movi      	r2, 1
    3e7a:	9320      	ld.w      	r1, (r3, 0)
    3e7c:	9168      	ld.w      	r3, (r1, 0x20)
    3e7e:	68c8      	and      	r3, r2
    3e80:	3b40      	cmpnei      	r3, 0
    3e82:	0ffd      	bf      	0x3e7c	// 3e7c <ADC12_EOC_wait+0x6>
} 
    3e84:	783c      	rts

00003e86 <ADC12_SEQEND_wait>:
//EntryParameter:NONE
//ReturnValue:ADC12 EOC
/*************************************************************/ 
void ADC12_SEQEND_wait(U8_T val)
{
	while(!(ADC0->SR & (0x01ul << (16+val))));			// EOC wait
    3e86:	200f      	addi      	r0, 16
    3e88:	1171      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3e8a:	3201      	movi      	r2, 1
    3e8c:	9320      	ld.w      	r1, (r3, 0)
    3e8e:	7080      	lsl      	r2, r0
    3e90:	9168      	ld.w      	r3, (r1, 0x20)
    3e92:	68c8      	and      	r3, r2
    3e94:	3b40      	cmpnei      	r3, 0
    3e96:	0ffd      	bf      	0x3e90	// 3e90 <ADC12_SEQEND_wait+0xa>
} 
    3e98:	783c      	rts

00003e9a <ADC12_DATA_OUPUT>:
//EntryParameter:NONE
//ReturnValue:ADC12 DR
/*************************************************************/ 
U16_T ADC12_DATA_OUPUT(U16_T Data_index )
{
	return(ADC0->DR[Data_index]);
    3e9a:	203f      	addi      	r0, 64
    3e9c:	116c      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3e9e:	4002      	lsli      	r0, r0, 2
    3ea0:	9360      	ld.w      	r3, (r3, 0)
    3ea2:	600c      	addu      	r0, r3
    3ea4:	9000      	ld.w      	r0, (r0, 0)
    3ea6:	7401      	zexth      	r0, r0
} 
    3ea8:	783c      	rts

00003eaa <ADC12_Configure_Mode>:
  //10BIT or 12BIT adc ;
  //ADC12_BIT_SELECTED:ADC12_12BIT/ADC12_10BIT;
  //ADC12_ConverMode:One_shot_mode/Continuous_mode;
  //adc date output=last number of Conversions;
void  ADC12_Configure_Mode(ADC12_10bitor12bit_TypeDef ADC12_BIT_SELECTED  , ADC12_ConverMode_TypeDef  ADC12_ConverMode  , U8_T ADC12_PRI, U8_T ADC12_DIV , U8_T NumConver ) 
{
    3eaa:	14d4      	push      	r4-r7, r15
    3eac:	d88e0014 	ld.b      	r4, (sp, 0x14)
    3eb0:	6dcb      	mov      	r7, r2
	ADC0->MR|=ADC12_DIV|((NumConver-1)<<10);
    3eb2:	2c00      	subi      	r4, 1
    3eb4:	1146      	lrw      	r2, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3eb6:	448a      	lsli      	r4, r4, 10
    3eb8:	92a0      	ld.w      	r5, (r2, 0)
    3eba:	6cd0      	or      	r3, r4
{
    3ebc:	6d83      	mov      	r6, r0
	ADC0->MR|=ADC12_DIV|((NumConver-1)<<10);
    3ebe:	9505      	ld.w      	r0, (r5, 0x14)
    3ec0:	6cc0      	or      	r3, r0
	if(ADC12_ConverMode==One_shot_mode)
    3ec2:	3940      	cmpnei      	r1, 0
	ADC0->MR|=ADC12_DIV|((NumConver-1)<<10);
    3ec4:	b565      	st.w      	r3, (r5, 0x14)
    3ec6:	6d0b      	mov      	r4, r2
	if(ADC12_ConverMode==One_shot_mode)
    3ec8:	0818      	bt      	0x3ef8	// 3ef8 <ADC12_Configure_Mode+0x4e>
	{
		ADC0->MR&=~CONTCV;								//one short mode
    3eca:	9565      	ld.w      	r3, (r5, 0x14)
    3ecc:	4361      	lsli      	r3, r3, 1
    3ece:	4b61      	lsri      	r3, r3, 1
		while(ADC0->SR&ADC12_CTCVS);							
    3ed0:	3280      	movi      	r2, 128
		ADC0->MR&=~CONTCV;								//one short mode
    3ed2:	b565      	st.w      	r3, (r5, 0x14)
		while(ADC0->SR&ADC12_CTCVS);							
    3ed4:	4242      	lsli      	r2, r2, 2
    3ed6:	9568      	ld.w      	r3, (r5, 0x20)
    3ed8:	68c8      	and      	r3, r2
    3eda:	3b40      	cmpnei      	r3, 0
    3edc:	0bfd      	bt      	0x3ed6	// 3ed6 <ADC12_Configure_Mode+0x2c>
    3ede:	e3ffff78 	bsr      	0x3dce	// 3dce <ADC12_CMD.part.0>
	{
		ADC0->MR|=CONTCV;								//Continuous mode
		while(!(ADC0->SR&ADC12_CTCVS));							
	}
	ADC12_CMD(ENABLE);									//ADC0 enable
	if(ADC12_BIT_SELECTED)
    3ee2:	3e40      	cmpnei      	r6, 0
    3ee4:	0c16      	bf      	0x3f10	// 3f10 <ADC12_Configure_Mode+0x66>
	{
		ADC0->CR|=ADC12_10BITor12BIT;
    3ee6:	9440      	ld.w      	r2, (r4, 0)
    3ee8:	9264      	ld.w      	r3, (r2, 0x10)
    3eea:	3bbf      	bseti      	r3, r3, 31
	}
	else
	{
		ADC0->CR&=~ADC12_10BITor12BIT;
    3eec:	b264      	st.w      	r3, (r2, 0x10)
	}
	ADC0->CR|=ADC12_VREF_VDD | ADC12_FVR_DIS;
    3eee:	9460      	ld.w      	r3, (r4, 0)
    3ef0:	9344      	ld.w      	r2, (r3, 0x10)
    3ef2:	b344      	st.w      	r2, (r3, 0x10)
	ADC0 ->PRI=ADC12_PRI;
    3ef4:	b3fc      	st.w      	r7, (r3, 0x70)
} 
    3ef6:	1494      	pop      	r4-r7, r15
	else if(ADC12_ConverMode==Continuous_mode)
    3ef8:	3941      	cmpnei      	r1, 1
    3efa:	0bf2      	bt      	0x3ede	// 3ede <ADC12_Configure_Mode+0x34>
		ADC0->MR|=CONTCV;								//Continuous mode
    3efc:	9565      	ld.w      	r3, (r5, 0x14)
    3efe:	3bbf      	bseti      	r3, r3, 31
		while(!(ADC0->SR&ADC12_CTCVS));							
    3f00:	3280      	movi      	r2, 128
		ADC0->MR|=CONTCV;								//Continuous mode
    3f02:	b565      	st.w      	r3, (r5, 0x14)
		while(!(ADC0->SR&ADC12_CTCVS));							
    3f04:	4242      	lsli      	r2, r2, 2
    3f06:	9568      	ld.w      	r3, (r5, 0x20)
    3f08:	68c8      	and      	r3, r2
    3f0a:	3b40      	cmpnei      	r3, 0
    3f0c:	0ffd      	bf      	0x3f06	// 3f06 <ADC12_Configure_Mode+0x5c>
    3f0e:	07e8      	br      	0x3ede	// 3ede <ADC12_Configure_Mode+0x34>
		ADC0->CR&=~ADC12_10BITor12BIT;
    3f10:	9440      	ld.w      	r2, (r4, 0)
    3f12:	9264      	ld.w      	r3, (r2, 0x10)
    3f14:	4361      	lsli      	r3, r3, 1
    3f16:	4b61      	lsri      	r3, r3, 1
    3f18:	07ea      	br      	0x3eec	// 3eec <ADC12_Configure_Mode+0x42>

00003f1a <ADC12_TRGSRC_Configure>:
//TRGSRC_Data:ADC_TRG_None/ADC_TRG_SW /ADC_TRG_TC1/ADC_TRG_EPWM/ADC_TRG_CMP /ADC_TRG_EXRE/ADC_TRG_EXFE/ADC_TRG_EXRFE	
//ADC_Channel:0~15
//ReturnValue:NONE
/*************************************************************/ 
void ADC12_TRGSRC_Configure(ADC12_TRGSRC_TypeDef TRGSRC_Data,U8_T ADC_Channel)
{
    3f1a:	104d      	lrw      	r2, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3f1c:	4162      	lsli      	r3, r1, 2
    3f1e:	9220      	ld.w      	r1, (r2, 0)
    3f20:	604c      	addu      	r1, r3
	ADC0->SEQ[ADC_Channel] |= TRGSRC_Data;
    3f22:	916c      	ld.w      	r3, (r1, 0x30)
    3f24:	6c0c      	or      	r0, r3
    3f26:	b10c      	st.w      	r0, (r1, 0x30)
}
    3f28:	783c      	rts

00003f2a <ADC12_TRGDelay_Configure>:
//Dealy_Time:0~255
//ReturnValue:NONE
/*************************************************************/ 
void ADC12_TRGDelay_Configure(U8_T TRGSRC,U8_T Dealy_Time)
{
	if(TRGSRC<=16)
    3f2a:	3810      	cmphsi      	r0, 17
    3f2c:	1068      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
	{
		ADC0->TDL0 = Dealy_Time<<TRGSRC;
    3f2e:	9360      	ld.w      	r3, (r3, 0)
	if(TRGSRC<=16)
    3f30:	0804      	bt      	0x3f38	// 3f38 <ADC12_TRGDelay_Configure+0xe>
		ADC0->TDL0 = Dealy_Time<<TRGSRC;
    3f32:	7040      	lsl      	r1, r0
    3f34:	b33d      	st.w      	r1, (r3, 0x74)
	}
	else
	{
		ADC0->TDL1 = (Dealy_Time<<(TRGSRC-32));
	}
}
    3f36:	783c      	rts
		ADC0->TDL1 = (Dealy_Time<<(TRGSRC-32));
    3f38:	281f      	subi      	r0, 32
    3f3a:	7040      	lsl      	r1, r0
    3f3c:	b33e      	st.w      	r1, (r3, 0x78)
}
    3f3e:	07fc      	br      	0x3f36	// 3f36 <ADC12_TRGDelay_Configure+0xc>

00003f40 <ADC12_Configure_VREF_VDD>:
//EntryParameter:NONE
//ReturnValue:None
/*************************************************************/ 
void ADC12_Configure_VREF_VDD(void)
{
	ADC0->CR|= ADC12_VREF_VDD | ADC12_FVR_DIS;
    3f40:	1063      	lrw      	r3, 0x20000054	// 3f4c <ADC12_Configure_VREF_FVR+0x2>
    3f42:	9360      	ld.w      	r3, (r3, 0)
    3f44:	9344      	ld.w      	r2, (r3, 0x10)
    3f46:	b344      	st.w      	r2, (r3, 0x10)

}
    3f48:	783c      	rts

00003f4a <ADC12_Configure_VREF_FVR>:
//ADC12 VREF slection= Fixed voltage
//EntryParameter:ADC12_FVR_2_048V / ADC12_FVR_4_096V
//ReturnValue:None
/*************************************************************/ 
void ADC12_Configure_VREF_FVR(U32_T FVR_DATA)
{
    3f4a:	0405      	br      	0x3f54	// 3f54 <ADC12_Configure_VREF_FVR+0xa>
    3f4c:	20000054 	.long	0x20000054
    3f50:	3fffffff 	.long	0x3fffffff
	GPIOD0->CONLR = (GPIOD0->CONLR&0XFFFFFF0F) | 0X00000070;
    3f54:	1367      	lrw      	r3, 0x20000040	// 40f0 <ADC12_ConversionChannel_Config+0x11e>
    3f56:	31f0      	movi      	r1, 240
    3f58:	9340      	ld.w      	r2, (r3, 0)
    3f5a:	9260      	ld.w      	r3, (r2, 0)
    3f5c:	68c5      	andn      	r3, r1
    3f5e:	3170      	movi      	r1, 112
    3f60:	6cc4      	or      	r3, r1
    3f62:	b260      	st.w      	r3, (r2, 0)
	ADC0->CR|=ADC12_VREF_FVR | ADC12_FVR_EN | FVR_DATA;
    3f64:	1364      	lrw      	r3, 0x20000054	// 40f4 <ADC12_ConversionChannel_Config+0x122>
    3f66:	9340      	ld.w      	r2, (r3, 0)
    3f68:	9264      	ld.w      	r3, (r2, 0x10)
    3f6a:	3ba8      	bseti      	r3, r3, 8
    3f6c:	3ba9      	bseti      	r3, r3, 9
    3f6e:	6c0c      	or      	r0, r3
    3f70:	b204      	st.w      	r0, (r2, 0x10)
}
    3f72:	783c      	rts

00003f74 <ADC12_Configure_VREF_EX>:
//EntryParameter:None
//ReturnValue:None
/*************************************************************/ 
void ADC12_Configure_VREF_EX(void)
{
	GPIOD0->CONLR=(GPIOD0->CONLR & 0XFFFFFF0F)|0x00000070; 	
    3f74:	127f      	lrw      	r3, 0x20000040	// 40f0 <ADC12_ConversionChannel_Config+0x11e>
    3f76:	31f0      	movi      	r1, 240
    3f78:	9340      	ld.w      	r2, (r3, 0)
    3f7a:	9260      	ld.w      	r3, (r2, 0)
    3f7c:	68c5      	andn      	r3, r1
    3f7e:	3170      	movi      	r1, 112
    3f80:	6cc4      	or      	r3, r1
    3f82:	b260      	st.w      	r3, (r2, 0)
	ADC0->CR|=ADC12_VREF_FVR | ADC12_FVR_DIS;
    3f84:	127c      	lrw      	r3, 0x20000054	// 40f4 <ADC12_ConversionChannel_Config+0x122>
    3f86:	9340      	ld.w      	r2, (r3, 0)
    3f88:	9264      	ld.w      	r3, (r2, 0x10)
    3f8a:	3ba8      	bseti      	r3, r3, 8
    3f8c:	b264      	st.w      	r3, (r2, 0x10)
}
    3f8e:	783c      	rts

00003f90 <ADC12_CompareFunction_set>:
  //ADC will generate a CMPxH/CMPxL interrupt when result of this number of conversion is higher/lower than data set in ADC_CMPx register.
  //ConverNum_CM1Number of Conversions for Compare Function
  //ADC will generate a CMP1H/CMP1L interrupt when result of this number of conversion is greater/less than data set in ADC_CMP1 register.
  
void ADC12_CompareFunction_set(U8_T ConverNum_CM0 , U8_T ConverNum_CM1 , U16_T CMP0_data , U16_T CMP1_data ) 
{
    3f90:	14c2      	push      	r4-r5
	ADC0->MR|=((ConverNum_CM0-0)<<16)|((ConverNum_CM1-0)<<22);
    3f92:	1299      	lrw      	r4, 0x20000054	// 40f4 <ADC12_ConversionChannel_Config+0x122>
    3f94:	4136      	lsli      	r1, r1, 22
    3f96:	9480      	ld.w      	r4, (r4, 0)
    3f98:	4010      	lsli      	r0, r0, 16
    3f9a:	94a5      	ld.w      	r5, (r4, 0x14)
    3f9c:	6c04      	or      	r0, r1
    3f9e:	6c14      	or      	r0, r5
    3fa0:	b405      	st.w      	r0, (r4, 0x14)
	ADC0->CMP0=CMP0_data;
    3fa2:	24ff      	addi      	r4, 256
    3fa4:	b450      	st.w      	r2, (r4, 0x40)
	ADC0->CMP1=CMP1_data;
    3fa6:	b471      	st.w      	r3, (r4, 0x44)
}
    3fa8:	1482      	pop      	r4-r5

00003faa <ADC12_Compare_statue>:
//NBRCMPX_L_TypeDef:NBRCMPX_L_TypeDef,NBRCMPX_H_TypeDef
//ReturnValue:ADC12 Compare result flag
/*************************************************************/ 
  //output statue:ADC-SR(ADC12_CMP0H/ADC12_CMP0L/ADC12_CMP1H/ADC12_CMP1L)
U8_T ADC12_Compare_statue(ADC12_NBRCMPx_TypeDef ADC12_NBRCMPx, ADC12_NBRCMPx_HorL_TypeDef ADC12_NBRCMPx_HorL)
{
    3faa:	1273      	lrw      	r3, 0x20000054	// 40f4 <ADC12_ConversionChannel_Config+0x122>
	if(ADC12_NBRCMPx==NBRCMP0_TypeDef)
    3fac:	3840      	cmpnei      	r0, 0
	{
		if(ADC12_NBRCMPx_HorL==NBRCMPX_L_TypeDef)
		{
			return((ADC0->SR)&ADC12_CMP0L);
    3fae:	9360      	ld.w      	r3, (r3, 0)
    3fb0:	9308      	ld.w      	r0, (r3, 0x20)
	if(ADC12_NBRCMPx==NBRCMP0_TypeDef)
    3fb2:	0808      	bt      	0x3fc2	// 3fc2 <ADC12_Compare_statue+0x18>
		if(ADC12_NBRCMPx_HorL==NBRCMPX_L_TypeDef)
    3fb4:	3940      	cmpnei      	r1, 0
    3fb6:	0804      	bt      	0x3fbe	// 3fbe <ADC12_Compare_statue+0x14>
			return((ADC0->SR)&ADC12_CMP0L);
    3fb8:	3320      	movi      	r3, 32
		{
			return((ADC0->SR)&ADC12_CMP1L);
		}
		else
		{
			return((ADC0->SR)&ADC12_CMP1H);
    3fba:	680c      	and      	r0, r3
    3fbc:	0407      	br      	0x3fca	// 3fca <ADC12_Compare_statue+0x20>
			return((ADC0->SR)&ADC12_CMP0H);
    3fbe:	3310      	movi      	r3, 16
    3fc0:	07fd      	br      	0x3fba	// 3fba <ADC12_Compare_statue+0x10>
		if(ADC12_NBRCMPx_HorL==NBRCMPX_L_TypeDef)
    3fc2:	3940      	cmpnei      	r1, 0
    3fc4:	0805      	bt      	0x3fce	// 3fce <ADC12_Compare_statue+0x24>
			return((ADC0->SR)&ADC12_CMP1L);
    3fc6:	337f      	movi      	r3, 127
    3fc8:	680d      	andn      	r0, r3
			return((ADC0->SR)&ADC12_CMP1H);
    3fca:	7400      	zextb      	r0, r0
		}
	}
}
    3fcc:	783c      	rts
			return((ADC0->SR)&ADC12_CMP1H);
    3fce:	3340      	movi      	r3, 64
    3fd0:	07f5      	br      	0x3fba	// 3fba <ADC12_Compare_statue+0x10>

00003fd2 <ADC12_ConversionChannel_Config>:
//ADC12_ADCINX:ADC12_ADCIN0~ADC12_ADCIN17,ADC12_FVR,ADC12_DIV4_VDD,ADC12_VSS
//ReturnValue:NONE
/*************************************************************/ 
void ADC12_ConversionChannel_Config(ADC12_InputSet_TypeDef ADC12_ADCINX, ADC12_Sampling_TypeDef ADC12_Sample_SELECTED,
						ADC12_CV_RepeatNum_TypeDef CV_RepeatTime, ADC12_Control_TypeDef AVG_Set, U8_T SEQx)
{
    3fd2:	14d4      	push      	r4-r7, r15
    3fd4:	1422      	subi      	sp, sp, 8
    3fd6:	b820      	st.w      	r1, (sp, 0)
	switch(ADC12_ADCINX)
    3fd8:	3811      	cmphsi      	r0, 18
{
    3fda:	d82e001c 	ld.b      	r1, (sp, 0x1c)
    3fde:	6d83      	mov      	r6, r0
    3fe0:	b821      	st.w      	r1, (sp, 0x4)
	switch(ADC12_ADCINX)
    3fe2:	0828      	bt      	0x4032	// 4032 <ADC12_ConversionChannel_Config+0x60>
    3fe4:	1225      	lrw      	r1, 0x20000050	// 40f8 <ADC12_ConversionChannel_Config+0x126>
    3fe6:	12a6      	lrw      	r5, 0x20000048	// 40fc <ADC12_ConversionChannel_Config+0x12a>
    3fe8:	1286      	lrw      	r4, 0x2000004c	// 4100 <ADC12_ConversionChannel_Config+0x12e>
    3fea:	e0000965 	bsr      	0x52b4	// 52b4 <___gnu_csky_case_uhi>
    3fee:	0012      	.short	0x0012
    3ff0:	00430033 	.long	0x00430033
    3ff4:	005f0053 	.long	0x005f0053
    3ff8:	00760068 	.long	0x00760068
    3ffc:	0095008b 	.long	0x0095008b
    4000:	00ae009f 	.long	0x00ae009f
    4004:	00cd00bd 	.long	0x00cd00bd
    4008:	00dd00d5 	.long	0x00dd00d5
    400c:	00ed00e4 	.long	0x00ed00e4
    4010:	00f7      	.short	0x00f7
	{
		case 0:	
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC0 PA1.4
    4012:	9120      	ld.w      	r1, (r1, 0)
    4014:	9100      	ld.w      	r0, (r1, 0)
    4016:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
    4018:	9101      	ld.w      	r0, (r1, 0x4)
    401a:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
    401c:	9520      	ld.w      	r1, (r5, 0)
    401e:	9100      	ld.w      	r0, (r1, 0)
    4020:	b100      	st.w      	r0, (r1, 0)
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFFF0FFFF)  | 0x000A0000;							
    4022:	9400      	ld.w      	r0, (r4, 0)
    4024:	34f0      	movi      	r4, 240
    4026:	9020      	ld.w      	r1, (r0, 0)
    4028:	448c      	lsli      	r4, r4, 12
    402a:	6851      	andn      	r1, r4
    402c:	39b1      	bseti      	r1, r1, 17
    402e:	39b3      	bseti      	r1, r1, 19
			break;
		case 1:
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC1 PA1.5
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFF0FFFFF)  | 0x00A00000;							
    4030:	b020      	st.w      	r1, (r0, 0)
    4032:	9821      	ld.w      	r1, (sp, 0x4)
    4034:	4122      	lsli      	r1, r1, 2
    4036:	1110      	lrw      	r0, 0x20000054	// 40f4 <ADC12_ConversionChannel_Config+0x122>
		case 0x1Cul: break;
		case 0x1Dul: break;
		case 0x1Eul: break;
	}
	ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] & 0;
	ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] | ADC12_ADCINX | ADC12_Sample_SELECTED | CV_RepeatTime | AVG_Set;
    4038:	6c8c      	or      	r2, r3
    403a:	9000      	ld.w      	r0, (r0, 0)
    403c:	6004      	addu      	r0, r1
	ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] & 0;
    403e:	902c      	ld.w      	r1, (r0, 0x30)
	ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] | ADC12_ADCINX | ADC12_Sample_SELECTED | CV_RepeatTime | AVG_Set;
    4040:	9860      	ld.w      	r3, (sp, 0)
	ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] & 0;
    4042:	3100      	movi      	r1, 0
    4044:	b02c      	st.w      	r1, (r0, 0x30)
	ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] | ADC12_ADCINX | ADC12_Sample_SELECTED | CV_RepeatTime | AVG_Set;
    4046:	6c8c      	or      	r2, r3
    4048:	908c      	ld.w      	r4, (r0, 0x30)
    404a:	6d88      	or      	r6, r2
    404c:	6d90      	or      	r6, r4
    404e:	b0cc      	st.w      	r6, (r0, 0x30)
}
    4050:	1402      	addi      	sp, sp, 8
    4052:	1494      	pop      	r4-r7, r15
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC1 PA1.5
    4054:	9120      	ld.w      	r1, (r1, 0)
    4056:	9100      	ld.w      	r0, (r1, 0)
    4058:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
    405a:	9101      	ld.w      	r0, (r1, 0x4)
    405c:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
    405e:	9520      	ld.w      	r1, (r5, 0)
    4060:	9100      	ld.w      	r0, (r1, 0)
    4062:	b100      	st.w      	r0, (r1, 0)
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFF0FFFFF)  | 0x00A00000;							
    4064:	9400      	ld.w      	r0, (r4, 0)
    4066:	34f0      	movi      	r4, 240
    4068:	9020      	ld.w      	r1, (r0, 0)
    406a:	4490      	lsli      	r4, r4, 16
    406c:	6851      	andn      	r1, r4
    406e:	39b5      	bseti      	r1, r1, 21
    4070:	39b7      	bseti      	r1, r1, 23
    4072:	07df      	br      	0x4030	// 4030 <ADC12_ConversionChannel_Config+0x5e>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC2 PB0.0
    4074:	9120      	ld.w      	r1, (r1, 0)
    4076:	9100      	ld.w      	r0, (r1, 0)
    4078:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
    407a:	9101      	ld.w      	r0, (r1, 0x4)
    407c:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0)  | 0x0000000A;
    407e:	9500      	ld.w      	r0, (r5, 0)
    4080:	9020      	ld.w      	r1, (r0, 0)
    4082:	350f      	movi      	r5, 15
    4084:	6855      	andn      	r1, r5
    4086:	39a1      	bseti      	r1, r1, 1
    4088:	39a3      	bseti      	r1, r1, 3
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F)  | 0x000000A0;
    408a:	b020      	st.w      	r1, (r0, 0)
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFFFFF)  | 0x00000000;			
    408c:	9420      	ld.w      	r1, (r4, 0)
    408e:	9100      	ld.w      	r0, (r1, 0)
    4090:	b100      	st.w      	r0, (r1, 0)
			break;
    4092:	07d0      	br      	0x4032	// 4032 <ADC12_ConversionChannel_Config+0x60>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC3 PB0.1
    4094:	9120      	ld.w      	r1, (r1, 0)
    4096:	9100      	ld.w      	r0, (r1, 0)
    4098:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
    409a:	9101      	ld.w      	r0, (r1, 0x4)
    409c:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F)  | 0x000000A0;
    409e:	9500      	ld.w      	r0, (r5, 0)
    40a0:	9020      	ld.w      	r1, (r0, 0)
    40a2:	35f0      	movi      	r5, 240
    40a4:	6855      	andn      	r1, r5
    40a6:	39a5      	bseti      	r1, r1, 5
    40a8:	39a7      	bseti      	r1, r1, 7
    40aa:	07f0      	br      	0x408a	// 408a <ADC12_ConversionChannel_Config+0xb8>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0)  | 0x0000000A;							//ADC4 PA0.0
    40ac:	9100      	ld.w      	r0, (r1, 0)
    40ae:	9020      	ld.w      	r1, (r0, 0)
    40b0:	370f      	movi      	r7, 15
    40b2:	685d      	andn      	r1, r7
    40b4:	39a1      	bseti      	r1, r1, 1
    40b6:	39a3      	bseti      	r1, r1, 3
			GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)  | 0xA0000000;							//ADC14 PA0.7
    40b8:	b020      	st.w      	r1, (r0, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
    40ba:	9021      	ld.w      	r1, (r0, 0x4)
    40bc:	040a      	br      	0x40d0	// 40d0 <ADC12_ConversionChannel_Config+0xfe>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC5 PA0.11
    40be:	9100      	ld.w      	r0, (r1, 0)
    40c0:	9020      	ld.w      	r1, (r0, 0)
    40c2:	b020      	st.w      	r1, (r0, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF)  | 0x0000A000;	
    40c4:	37f0      	movi      	r7, 240
    40c6:	9021      	ld.w      	r1, (r0, 0x4)
    40c8:	47e8      	lsli      	r7, r7, 8
    40ca:	685d      	andn      	r1, r7
    40cc:	39ad      	bseti      	r1, r1, 13
    40ce:	39af      	bseti      	r1, r1, 15
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)  | 0x0000000A;	
    40d0:	b021      	st.w      	r1, (r0, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
    40d2:	9520      	ld.w      	r1, (r5, 0)
    40d4:	9100      	ld.w      	r0, (r1, 0)
    40d6:	b100      	st.w      	r0, (r1, 0)
    40d8:	07da      	br      	0x408c	// 408c <ADC12_ConversionChannel_Config+0xba>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC6 PA0.12
    40da:	9100      	ld.w      	r0, (r1, 0)
    40dc:	9020      	ld.w      	r1, (r0, 0)
    40de:	b020      	st.w      	r1, (r0, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF)  | 0x000A0000;	
    40e0:	37f0      	movi      	r7, 240
    40e2:	9021      	ld.w      	r1, (r0, 0x4)
    40e4:	47ec      	lsli      	r7, r7, 12
    40e6:	685d      	andn      	r1, r7
    40e8:	39b1      	bseti      	r1, r1, 17
    40ea:	39b3      	bseti      	r1, r1, 19
    40ec:	07f2      	br      	0x40d0	// 40d0 <ADC12_ConversionChannel_Config+0xfe>
    40ee:	0000      	bkpt
    40f0:	20000040 	.long	0x20000040
    40f4:	20000054 	.long	0x20000054
    40f8:	20000050 	.long	0x20000050
    40fc:	20000048 	.long	0x20000048
    4100:	2000004c 	.long	0x2000004c
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC7 PA0.13
    4104:	9100      	ld.w      	r0, (r1, 0)
    4106:	9020      	ld.w      	r1, (r0, 0)
    4108:	b020      	st.w      	r1, (r0, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF)  | 0x00A00000;	
    410a:	37f0      	movi      	r7, 240
    410c:	9021      	ld.w      	r1, (r0, 0x4)
    410e:	47f0      	lsli      	r7, r7, 16
    4110:	685d      	andn      	r1, r7
    4112:	39b5      	bseti      	r1, r1, 21
    4114:	39b7      	bseti      	r1, r1, 23
    4116:	07dd      	br      	0x40d0	// 40d0 <ADC12_ConversionChannel_Config+0xfe>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC8 PA0.14
    4118:	9100      	ld.w      	r0, (r1, 0)
    411a:	9020      	ld.w      	r1, (r0, 0)
    411c:	b020      	st.w      	r1, (r0, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF)  | 0x0A000000;	
    411e:	37f0      	movi      	r7, 240
    4120:	9021      	ld.w      	r1, (r0, 0x4)
    4122:	47f4      	lsli      	r7, r7, 20
    4124:	685d      	andn      	r1, r7
    4126:	39b9      	bseti      	r1, r1, 25
    4128:	39bb      	bseti      	r1, r1, 27
    412a:	07d3      	br      	0x40d0	// 40d0 <ADC12_ConversionChannel_Config+0xfe>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC9 PA1.0
    412c:	9120      	ld.w      	r1, (r1, 0)
    412e:	9100      	ld.w      	r0, (r1, 0)
    4130:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
    4132:	9101      	ld.w      	r0, (r1, 0x4)
    4134:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
    4136:	9520      	ld.w      	r1, (r5, 0)
    4138:	9100      	ld.w      	r0, (r1, 0)
    413a:	b100      	st.w      	r0, (r1, 0)
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFFFF0)  | 0x0000000A;	
    413c:	9400      	ld.w      	r0, (r4, 0)
    413e:	9020      	ld.w      	r1, (r0, 0)
    4140:	340f      	movi      	r4, 15
    4142:	6851      	andn      	r1, r4
    4144:	39a1      	bseti      	r1, r1, 1
    4146:	39a3      	bseti      	r1, r1, 3
    4148:	0774      	br      	0x4030	// 4030 <ADC12_ConversionChannel_Config+0x5e>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC10 PA1.1
    414a:	9120      	ld.w      	r1, (r1, 0)
    414c:	9100      	ld.w      	r0, (r1, 0)
    414e:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
    4150:	9101      	ld.w      	r0, (r1, 0x4)
    4152:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
    4154:	9520      	ld.w      	r1, (r5, 0)
    4156:	9100      	ld.w      	r0, (r1, 0)
    4158:	b100      	st.w      	r0, (r1, 0)
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFFF0F)  | 0x000000A0;	
    415a:	9400      	ld.w      	r0, (r4, 0)
    415c:	9020      	ld.w      	r1, (r0, 0)
    415e:	34f0      	movi      	r4, 240
    4160:	6851      	andn      	r1, r4
    4162:	39a5      	bseti      	r1, r1, 5
    4164:	39a7      	bseti      	r1, r1, 7
    4166:	0765      	br      	0x4030	// 4030 <ADC12_ConversionChannel_Config+0x5e>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC11 PA1.3
    4168:	9120      	ld.w      	r1, (r1, 0)
    416a:	9100      	ld.w      	r0, (r1, 0)
    416c:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
    416e:	9101      	ld.w      	r0, (r1, 0x4)
    4170:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
    4172:	9520      	ld.w      	r1, (r5, 0)
    4174:	9100      	ld.w      	r0, (r1, 0)
    4176:	b100      	st.w      	r0, (r1, 0)
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFF0FFF)  | 0x0000A000;			
    4178:	9400      	ld.w      	r0, (r4, 0)
    417a:	34f0      	movi      	r4, 240
    417c:	9020      	ld.w      	r1, (r0, 0)
    417e:	4488      	lsli      	r4, r4, 8
    4180:	6851      	andn      	r1, r4
    4182:	39ad      	bseti      	r1, r1, 13
    4184:	39af      	bseti      	r1, r1, 15
    4186:	0755      	br      	0x4030	// 4030 <ADC12_ConversionChannel_Config+0x5e>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF)  | 0x00A00000;							//ADC12 PA0.5
    4188:	9100      	ld.w      	r0, (r1, 0)
    418a:	37f0      	movi      	r7, 240
    418c:	9020      	ld.w      	r1, (r0, 0)
    418e:	47f0      	lsli      	r7, r7, 16
    4190:	685d      	andn      	r1, r7
    4192:	39b5      	bseti      	r1, r1, 21
    4194:	39b7      	bseti      	r1, r1, 23
    4196:	0791      	br      	0x40b8	// 40b8 <ADC12_ConversionChannel_Config+0xe6>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF)  | 0x0A000000;							//ADC13 PA0.6
    4198:	9100      	ld.w      	r0, (r1, 0)
    419a:	37f0      	movi      	r7, 240
    419c:	9020      	ld.w      	r1, (r0, 0)
    419e:	47f4      	lsli      	r7, r7, 20
    41a0:	685d      	andn      	r1, r7
    41a2:	39b9      	bseti      	r1, r1, 25
    41a4:	39bb      	bseti      	r1, r1, 27
    41a6:	0789      	br      	0x40b8	// 40b8 <ADC12_ConversionChannel_Config+0xe6>
			GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)  | 0xA0000000;							//ADC14 PA0.7
    41a8:	9100      	ld.w      	r0, (r1, 0)
    41aa:	9020      	ld.w      	r1, (r0, 0)
    41ac:	4124      	lsli      	r1, r1, 4
    41ae:	4924      	lsri      	r1, r1, 4
    41b0:	39bd      	bseti      	r1, r1, 29
    41b2:	39bf      	bseti      	r1, r1, 31
    41b4:	0782      	br      	0x40b8	// 40b8 <ADC12_ConversionChannel_Config+0xe6>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC15 PA0.8
    41b6:	9100      	ld.w      	r0, (r1, 0)
    41b8:	9020      	ld.w      	r1, (r0, 0)
    41ba:	b020      	st.w      	r1, (r0, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)  | 0x0000000A;	
    41bc:	9021      	ld.w      	r1, (r0, 0x4)
    41be:	370f      	movi      	r7, 15
    41c0:	685d      	andn      	r1, r7
    41c2:	39a1      	bseti      	r1, r1, 1
    41c4:	39a3      	bseti      	r1, r1, 3
    41c6:	0785      	br      	0x40d0	// 40d0 <ADC12_ConversionChannel_Config+0xfe>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC16 PA0.9
    41c8:	9120      	ld.w      	r1, (r1, 0)
    41ca:	9100      	ld.w      	r0, (r1, 0)
    41cc:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F)  | 0x000000A0;	
    41ce:	9101      	ld.w      	r0, (r1, 0x4)
    41d0:	37f0      	movi      	r7, 240
    41d2:	681d      	andn      	r0, r7
    41d4:	38a5      	bseti      	r0, r0, 5
    41d6:	38a7      	bseti      	r0, r0, 7
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF)  | 0x00000A00;	
    41d8:	b101      	st.w      	r0, (r1, 0x4)
    41da:	077c      	br      	0x40d2	// 40d2 <ADC12_ConversionChannel_Config+0x100>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC17 PA0.10
    41dc:	9120      	ld.w      	r1, (r1, 0)
    41de:	9100      	ld.w      	r0, (r1, 0)
    41e0:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF)  | 0x00000A00;	
    41e2:	37f0      	movi      	r7, 240
    41e4:	9101      	ld.w      	r0, (r1, 0x4)
    41e6:	47e4      	lsli      	r7, r7, 4
    41e8:	681d      	andn      	r0, r7
    41ea:	38a9      	bseti      	r0, r0, 9
    41ec:	38ab      	bseti      	r0, r0, 11
    41ee:	07f5      	br      	0x41d8	// 41d8 <ADC12_ConversionChannel_Config+0x206>

000041f0 <ADC_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void ADC_Int_Enable(void)
{
    ADC0->CSR=0xFFFFFFFF;
    41f0:	1073      	lrw      	r3, 0x20000054	// 423c <ADC_Test+0x26>
    41f2:	9340      	ld.w      	r2, (r3, 0)
    41f4:	3300      	movi      	r3, 0
    41f6:	2b00      	subi      	r3, 1
    41f8:	b267      	st.w      	r3, (r2, 0x1c)
	INTC_ISER_WRITE(ADC_INT);    
    41fa:	3208      	movi      	r2, 8
    41fc:	1071      	lrw      	r3, 0x20000064	// 4240 <ADC_Test+0x2a>
    41fe:	9360      	ld.w      	r3, (r3, 0)
    4200:	23ff      	addi      	r3, 256
    4202:	b340      	st.w      	r2, (r3, 0)
}
    4204:	783c      	rts

00004206 <ADC_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void ADC_Int_Disable(void)
{
    INTC_ICER_WRITE(ADC_INT);    
    4206:	106f      	lrw      	r3, 0x20000064	// 4240 <ADC_Test+0x2a>
    4208:	32c0      	movi      	r2, 192
    420a:	9360      	ld.w      	r3, (r3, 0)
    420c:	4241      	lsli      	r2, r2, 1
    420e:	60c8      	addu      	r3, r2
    4210:	3208      	movi      	r2, 8
    4212:	b340      	st.w      	r2, (r3, 0)
}
    4214:	783c      	rts

00004216 <ADC_Test>:

void ADC_Test(void)
{
    4216:	14d0      	push      	r15
	U8_T i;
	ADC12_ready_wait(); 
    4218:	e3fffe27 	bsr      	0x3e66	// 3e66 <ADC12_ready_wait>
	ADC12_Control(ADC12_START);
    421c:	3008      	movi      	r0, 8
    421e:	e3fffdd2 	bsr      	0x3dc2	// 3dc2 <ADC12_Control>
	for (i=0;i<3;i++)
	{
	ADC12_SEQEND_wait(i);
    4222:	3000      	movi      	r0, 0
    4224:	e3fffe31 	bsr      	0x3e86	// 3e86 <ADC12_SEQEND_wait>
    4228:	3001      	movi      	r0, 1
    422a:	e3fffe2e 	bsr      	0x3e86	// 3e86 <ADC12_SEQEND_wait>
    422e:	3002      	movi      	r0, 2
    4230:	e3fffe2b 	bsr      	0x3e86	// 3e86 <ADC12_SEQEND_wait>
	//adc_dr[i]=ADC0->DR[i];
	}
	ADC12_Control(ADC12_STOP);
    4234:	3010      	movi      	r0, 16
    4236:	e3fffdc6 	bsr      	0x3dc2	// 3dc2 <ADC12_Control>
}
    423a:	1490      	pop      	r15
    423c:	20000054 	.long	0x20000054
    4240:	20000064 	.long	0x20000064

00004244 <delay_nms>:
//software delay
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/	
void delay_nms(unsigned int t)
{
    4244:	1423      	subi      	sp, sp, 12
    volatile unsigned int i,j ,k=0;
    4246:	3300      	movi      	r3, 0
    4248:	b862      	st.w      	r3, (sp, 0x8)
    j = 50* t;
    424a:	3332      	movi      	r3, 50
    424c:	7c0c      	mult      	r0, r3
    424e:	b801      	st.w      	r0, (sp, 0x4)
    for ( i = 0; i < j; i++ )
    4250:	3300      	movi      	r3, 0
    4252:	b860      	st.w      	r3, (sp, 0)
    4254:	9840      	ld.w      	r2, (sp, 0)
    4256:	9861      	ld.w      	r3, (sp, 0x4)
    4258:	64c8      	cmphs      	r2, r3
    425a:	0c03      	bf      	0x4260	// 4260 <delay_nms+0x1c>
    {
        k++;
    }
}
    425c:	1403      	addi      	sp, sp, 12
    425e:	783c      	rts
        k++;
    4260:	9862      	ld.w      	r3, (sp, 0x8)
    4262:	2300      	addi      	r3, 1
    4264:	b862      	st.w      	r3, (sp, 0x8)
    for ( i = 0; i < j; i++ )
    4266:	9860      	ld.w      	r3, (sp, 0)
    4268:	2300      	addi      	r3, 1
    426a:	07f4      	br      	0x4252	// 4252 <delay_nms+0xe>

0000426c <GPIO_CONFIG>:
//GPIO Functions
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/ 
void GPIO_CONFIG(void)
{
    426c:	14d1      	push      	r4, r15
	GPIO_Init(GPIOA0,12,0);							//PA0.12 输出模式
    426e:	0383      	lrw      	r4, 0x20000050	// 44dc <GPT_CONFIG+0x8c>
    4270:	3200      	movi      	r2, 0
    4272:	9400      	ld.w      	r0, (r4, 0)
    4274:	310c      	movi      	r1, 12
    4276:	e3fff541 	bsr      	0x2cf8	// 2cf8 <GPIO_Init>
	
	GPIO_Write_High(GPIOA0,12);						//PA0.12 输出高	
    427a:	9400      	ld.w      	r0, (r4, 0)
    427c:	310c      	movi      	r1, 12
    427e:	e3fff75f 	bsr      	0x313c	// 313c <GPIO_Write_High>
//------------  EXI FUNTION  --------------------------------/
//EXI0_INT= EXI0,EXI1_INT= EXI1, EXI2_INT=EXI2~EXI3, EXI3_INT=EXI4~EXI9, EXI4_INT=EXI10~EXI15    
	GPIO_Init(GPIOA0,0,1);							//PA0.00 输入模式, 下面配置为下降沿外部中断方式
    4282:	3201      	movi      	r2, 1
    4284:	3100      	movi      	r1, 0
    4286:	9400      	ld.w      	r0, (r4, 0)
    4288:	e3fff538 	bsr      	0x2cf8	// 2cf8 <GPIO_Init>
						
	GPIO_IntGroup_Set(PA0);							//外部中断选GPIOA0组
    428c:	3000      	movi      	r0, 0
    428e:	e3fff60b 	bsr      	0x2ea4	// 2ea4 <GPIO_IntGroup_Set>
	
	EXTI_trigger_CMD(ENABLE,EXI_PIN0,_EXIFT);       //PA0.0下降沿中断
    4292:	3201      	movi      	r2, 1
    4294:	3101      	movi      	r1, 1
    4296:	3001      	movi      	r0, 1
    4298:	e3ffed4c 	bsr      	0x1d30	// 1d30 <EXTI_trigger_CMD>
	EXTI_interrupt_CMD(ENABLE,EXI_PIN0);            //使能EXI0中断
    429c:	3101      	movi      	r1, 1
    429e:	3001      	movi      	r0, 1
    42a0:	e3ffed65 	bsr      	0x1d6a	// 1d6a <EXTI_interrupt_CMD>
	
	GPIO_EXTI_interrupt(GPIOA0,EXI_PIN0);			//使能PA0.0做外部中断
    42a4:	9400      	ld.w      	r0, (r4, 0)
    42a6:	3101      	movi      	r1, 1
    42a8:	e3ffed75 	bsr      	0x1d92	// 1d92 <GPIO_EXTI_interrupt>
	
	EXI0_Int_Enable();                              //使能EXI0中断向量
    42ac:	e3ffedf6 	bsr      	0x1e98	// 1e98 <EXI0_Int_Enable>
	EXI0_WakeUp_Enable();							//使能EXI0中断唤醒
    42b0:	e3ffee5b 	bsr      	0x1f66	// 1f66 <EXI0_WakeUp_Enable>
}
    42b4:	1491      	pop      	r4, r15

000042b6 <CORET_CONFIG>:
//CORET Functions
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/ 
void CORET_CONFIG(void)
{
    42b6:	14d0      	push      	r15
	CORET_DeInit();									//Coret 所有寄存器复位赋值			
    42b8:	e3fff462 	bsr      	0x2b7c	// 2b7c <CORET_DeInit>
	SYSCON_General_CMD(ENABLE,ENDIS_SYSTICK);		//使能 STCLK 时钟
    42bc:	3180      	movi      	r1, 128
    42be:	4124      	lsli      	r1, r1, 4
    42c0:	3001      	movi      	r0, 1
    42c2:	e3ffec8f 	bsr      	0x1be0	// 1be0 <SYSCON_General_CMD>
	CK801->CORET_RVR=0x26259f;						//CORETCLK=sysclock/8=20M/8=0.4us  e.g:1s=(CORET_RVR+1)*0.4us;CORET_RVR=0x2625a0-1=0x26259f
    42c6:	0378      	lrw      	r3, 0x20000064	// 44e0 <GPT_CONFIG+0x90>
    42c8:	0358      	lrw      	r2, 0x26259f	// 44e4 <GPT_CONFIG+0x94>
    42ca:	9360      	ld.w      	r3, (r3, 0)
    42cc:	b345      	st.w      	r2, (r3, 0x14)
	CORET_reload();									// Coret CVR 清除						
    42ce:	e3fff4a3 	bsr      	0x2c14	// 2c14 <CORET_reload>
	CORET_CLKSOURCE_EX();							//使用时钟源为sysclk/8
    42d2:	e3fff489 	bsr      	0x2be4	// 2be4 <CORET_CLKSOURCE_EX>
	CORET_TICKINT_Enable();							//使能计数器清零中断
    42d6:	e3fff493 	bsr      	0x2bfc	// 2bfc <CORET_TICKINT_Enable>
	
	CORET_start();									//Coret 计时开始				
    42da:	e3fff479 	bsr      	0x2bcc	// 2bcc <CORET_start>
	CORET_Int_Enable();								//使能计数器清零中断向量
    42de:	e3fff459 	bsr      	0x2b90	// 2b90 <CORET_Int_Enable>
	//CORET_WakeUp_Enable();							//使能计数器清零中断唤醒
	
}
    42e2:	1490      	pop      	r15

000042e4 <LED_CONFIG>:
//LED Init
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void LED_CONFIG(void)  
{
    42e4:	14d0      	push      	r15
    42e6:	1421      	subi      	sp, sp, 4
	LED_RESET_VALUE();                                          //LED 所有寄存器复位赋值
    42e8:	e3ffe9de 	bsr      	0x16a4	// 16a4 <LED_RESET_VALUE>
	LED_seg_io_initial(LED_SEG_0,0);							//led seg0 io 初始化
    42ec:	3100      	movi      	r1, 0
    42ee:	3001      	movi      	r0, 1
    42f0:	e3ffea90 	bsr      	0x1810	// 1810 <LED_seg_io_initial>
	LED_seg_io_initial(LED_SEG_1,0);							//led seg1 io 初始化
    42f4:	3100      	movi      	r1, 0
    42f6:	3002      	movi      	r0, 2
    42f8:	e3ffea8c 	bsr      	0x1810	// 1810 <LED_seg_io_initial>
	LED_seg_io_initial(LED_SEG_4,0);							//led seg4 io 初始化
    42fc:	3100      	movi      	r1, 0
    42fe:	3005      	movi      	r0, 5
    4300:	e3ffea88 	bsr      	0x1810	// 1810 <LED_seg_io_initial>
	LED_seg_io_initial(LED_SEG_5,0);							//led seg5 io 初始化
    4304:	3100      	movi      	r1, 0
    4306:	3006      	movi      	r0, 6
    4308:	e3ffea84 	bsr      	0x1810	// 1810 <LED_seg_io_initial>
	LED_seg_io_initial(LED_SEG_6,0);							//led seg6 io 初始化
    430c:	3100      	movi      	r1, 0
    430e:	3007      	movi      	r0, 7
    4310:	e3ffea80 	bsr      	0x1810	// 1810 <LED_seg_io_initial>
	LED_seg_io_initial(LED_SEG_7,0);							//led seg7 io 初始化
    4314:	3100      	movi      	r1, 0
    4316:	3008      	movi      	r0, 8
    4318:	e3ffea7c 	bsr      	0x1810	// 1810 <LED_seg_io_initial>
	LED_Control_Config(LEDCLK_DIV32,0xff,LED_Bright_100,80,1);	//F_LedClk=32/20M;COM0~COM7使能;亮度100%;COM显示周期长度=(8*32/20M)*(80+7)=1.1MS;相邻COM互不交叠区时间时间=0;
    431c:	3301      	movi      	r3, 1
    431e:	3200      	movi      	r2, 0
    4320:	b860      	st.w      	r3, (sp, 0)
    4322:	31ff      	movi      	r1, 255
    4324:	3350      	movi      	r3, 80
    4326:	3006      	movi      	r0, 6
    4328:	e3ffea0b 	bsr      	0x173e	// 173e <LED_Control_Config>
	LED_SEGDATX_data_write(SEGDAT_NUM0 , 0xaa);                 //SegDat0=0xaa
    432c:	31aa      	movi      	r1, 170
    432e:	3000      	movi      	r0, 0
    4330:	e3ffeaf4 	bsr      	0x1918	// 1918 <LED_SEGDATX_data_write>
	LED_SEGDATX_data_write(SEGDAT_NUM1 , 0xbb);                 //SegDat1=0xbb
    4334:	31bb      	movi      	r1, 187
    4336:	3001      	movi      	r0, 1
    4338:	e3ffeaf0 	bsr      	0x1918	// 1918 <LED_SEGDATX_data_write>
	LED_SEGDATX_data_write(SEGDAT_NUM2 , 0xcc);                 //SegDat2=0xcc
    433c:	31cc      	movi      	r1, 204
    433e:	3002      	movi      	r0, 2
    4340:	e3ffeaec 	bsr      	0x1918	// 1918 <LED_SEGDATX_data_write>
	LED_SEGDATX_data_write(SEGDAT_NUM3 , 0xdd);                 //SegDat3=0xdd
    4344:	31dd      	movi      	r1, 221
    4346:	3003      	movi      	r0, 3
    4348:	e3ffeae8 	bsr      	0x1918	// 1918 <LED_SEGDATX_data_write>
	LED_SEGDATX_data_write(SEGDAT_NUM4 , 0xee);                 //SegDat4=0xee
    434c:	31ee      	movi      	r1, 238
    434e:	3004      	movi      	r0, 4
    4350:	e3ffeae4 	bsr      	0x1918	// 1918 <LED_SEGDATX_data_write>
	LED_SEGDATX_data_write(SEGDAT_NUM5 , 0xff);                 //SegDat5=0xff
    4354:	31ff      	movi      	r1, 255
    4356:	3005      	movi      	r0, 5
    4358:	e3ffeae0 	bsr      	0x1918	// 1918 <LED_SEGDATX_data_write>
	LED_SEGDATX_data_write(SEGDAT_NUM6 , 0x99);                 //SegDat6=0x99
    435c:	3199      	movi      	r1, 153
    435e:	3006      	movi      	r0, 6
    4360:	e3ffeadc 	bsr      	0x1918	// 1918 <LED_SEGDATX_data_write>
	LED_SEGDATX_data_write(SEGDAT_NUM7 , 0x88);                 //SegDat7=0x88
    4364:	3188      	movi      	r1, 136
    4366:	3007      	movi      	r0, 7
    4368:	e3ffead8 	bsr      	0x1918	// 1918 <LED_SEGDATX_data_write>
	LED_SCAN_ENABLE(ENABLE);                                    //LED Scan enable	
    436c:	3001      	movi      	r0, 1
    436e:	e3ffe9b3 	bsr      	0x16d4	// 16d4 <LED_SCAN_ENABLE>
	//LED_INT_CMD(IPEND,ENABLE);									//LED 一个com扫描结束中断使能
	//LED_INT_CMD(ICEND,ENABLE);									//LED 所有com扫描结束中断使能

	//LED_Int_Enable();											//LED INT Vector Enable			
										
}
    4372:	1401      	addi      	sp, sp, 4
    4374:	1490      	pop      	r15

00004376 <ADC_CONFIG>:
//ADC Functions
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/ 
void ADC_CONFIG(void)
{
    4376:	14d0      	push      	r15
    4378:	1421      	subi      	sp, sp, 4
	ADC12_RESET_VALUE();																//ADC 所有寄存器复位赋值
    437a:	e3fffce5 	bsr      	0x3d44	// 3d44 <ADC12_RESET_VALUE>
    ADC12_CLK_CMD(ADC_CLK_CR , ENABLE);                                                 //使能 ADC CLK
    437e:	3101      	movi      	r1, 1
    4380:	3002      	movi      	r0, 2
    4382:	e3fffd47 	bsr      	0x3e10	// 3e10 <ADC12_CLK_CMD>
    ADC12_Software_Reset();                                                             //ADC 软件复位
    4386:	e3fffd59 	bsr      	0x3e38	// 3e38 <ADC12_Software_Reset>
	ADC12_Configure_Mode(ADC12_12BIT , One_shot_mode ,0, 2 , 2);        				//选择12BIT ADC; 单次模式; 转换优先序列寄存器为0; ADC_CLK=PCLK/2*2=0.2us; 转换序列个数为2
    438a:	3302      	movi      	r3, 2
    438c:	b860      	st.w      	r3, (sp, 0)
    438e:	3200      	movi      	r2, 0
    4390:	3100      	movi      	r1, 0
    4392:	3001      	movi      	r0, 1
    4394:	e3fffd8b 	bsr      	0x3eaa	// 3eaa <ADC12_Configure_Mode>
	//ADC12_Configure_VREF_VDD();															//使用VDD为参考电压
	ADC12_Configure_VREF_FVR(ADC12_FVR_2_048V);											//使用内部为参考电压2.048mV
    4398:	3000      	movi      	r0, 0
    439a:	e3fffdd8 	bsr      	0x3f4a	// 3f4a <ADC12_Configure_VREF_FVR>
	//ADC12_Configure_VREF_EX();															//使用外部Vref为参考电压
	ADC12_ConversionChannel_Config(ADC12_ADCIN10,ADC12_3CYCLES,ADC12_CV_RepeatNum1,ADC12_AVGDIS,0);//转换序列0,选择ADCIN10通道, 3个转换周期, 连续重复采样次数为1,平均值计算禁止
    439e:	3300      	movi      	r3, 0
    43a0:	b860      	st.w      	r3, (sp, 0)
    43a2:	3200      	movi      	r2, 0
    43a4:	3100      	movi      	r1, 0
    43a6:	300a      	movi      	r0, 10
    43a8:	e3fffe15 	bsr      	0x3fd2	// 3fd2 <ADC12_ConversionChannel_Config>
	ADC12_ConversionChannel_Config(ADC12_ADCIN11,ADC12_3CYCLES,ADC12_CV_RepeatNum1,ADC12_AVGDIS,1);//转换序列1,选择ADCIN11通道, 3个转换周期, 连续重复采样次数为1,平均值计算禁止
    43ac:	3301      	movi      	r3, 1
    43ae:	3200      	movi      	r2, 0
    43b0:	3100      	movi      	r1, 0
    43b2:	b860      	st.w      	r3, (sp, 0)
    43b4:	300b      	movi      	r0, 11
    43b6:	3300      	movi      	r3, 0
    43b8:	e3fffe0d 	bsr      	0x3fd2	// 3fd2 <ADC12_ConversionChannel_Config>
	ADC12_CMD(ENABLE);                                                                  //使能ADC模块
    43bc:	3001      	movi      	r0, 1
    43be:	e3fffd42 	bsr      	0x3e42	// 3e42 <ADC12_CMD>
    ADC12_ready_wait(); 																//等待ADC模块配置完成
    43c2:	e3fffd52 	bsr      	0x3e66	// 3e66 <ADC12_ready_wait>
	ADC12_Control(ADC12_START);															//启动ADC转换
    43c6:	3008      	movi      	r0, 8
    43c8:	e3fffcfd 	bsr      	0x3dc2	// 3dc2 <ADC12_Control>
	 
}
    43cc:	1401      	addi      	sp, sp, 4
    43ce:	1490      	pop      	r15

000043d0 <UART_CONFIG>:
//UART Functions
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/ 
void UART_CONFIG(void)
{
    43d0:	14d0      	push      	r15
	UART_DeInit();                                                              //UART 所有寄存器复位赋值
    43d2:	e3fff9c9 	bsr      	0x3764	// 3764 <UART_DeInit>
    UART_IO_Init(IO_PA1);                                                  		//UART1脚位选择PA1.2->RXD1, PA1.1->TXD1
    43d6:	3001      	movi      	r0, 1
    43d8:	e3fff9f6 	bsr      	0x37c4	// 37c4 <UART_IO_Init>
    UARTInitRxTxIntEn(UART1,173,UART1_PAR_NONE);	                            //使能Uart中断, baudrate=20000000/173=115200, 使能偶校验位
    43dc:	1263      	lrw      	r3, 0x20000010	// 44e8 <GPT_CONFIG+0x98>
    43de:	3200      	movi      	r2, 0
    43e0:	9300      	ld.w      	r0, (r3, 0)
    43e2:	31ad      	movi      	r1, 173
    43e4:	e3fffa0c 	bsr      	0x37fc	// 37fc <UARTInitRxTxIntEn>
    UART1_Int_Enable();														    //uart1 中断向量使能
    43e8:	e3fff9ca 	bsr      	0x377c	// 377c <UART1_Int_Enable>
    //UART1_WakeUp_Enable();                                                      //uart1 wakeup Enable
	
} 
    43ec:	1490      	pop      	r15

000043ee <USART_CONFIG>:
//USART Functions
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/ 
void USART_CONFIG(void)
{
    43ee:	14d0      	push      	r15
    43f0:	1423      	subi      	sp, sp, 12
	USART_DeInit();                                                              	//USART 所有寄存器复位赋值
    43f2:	e3fffa5d 	bsr      	0x38ac	// 38ac <USART_DeInit>
    USART_CLK_Enable();																//USART CLK	使能
    43f6:	e3fffad6 	bsr      	0x39a2	// 39a2 <USART_CLK_Enable>
	USART_CTRL_Config(RSTRX,ENABLE);												//复位接收模块
    43fa:	3101      	movi      	r1, 1
    43fc:	3002      	movi      	r0, 2
    43fe:	e3fffb07 	bsr      	0x3a0c	// 3a0c <USART_CTRL_Config>
	USART_CTRL_Config(RSTTX,ENABLE);												//复位发射模块
    4402:	3101      	movi      	r1, 1
    4404:	3003      	movi      	r0, 3
    4406:	e3fffb03 	bsr      	0x3a0c	// 3a0c <USART_CTRL_Config>
	USART_IO_Init(USART_PB0);                                                  		//USART 使用PB0.0->RXD0, PB0.1->TXD0
    440a:	3000      	movi      	r0, 0
    440c:	e3fffa90 	bsr      	0x392c	// 392c <USART_IO_Init>
	//USART_CLKIO_Init(CLK_PA02);													//同步模式下可以选择PA0.2作为UARTCLK
    USART_MODE_Config(SENDTIME0,PCLK,CHRL8,ASYNC,PAR_EVEN,NBSTOP1,CHMODE_NORMAL);	//重发次数为0, CLKs=PCLK, 字节长度8bit, 异步模式, 偶校验位, 1个停止位, 普通模式
    4410:	3300      	movi      	r3, 0
    4412:	b862      	st.w      	r3, (sp, 0x8)
    4414:	b861      	st.w      	r3, (sp, 0x4)
    4416:	b860      	st.w      	r3, (sp, 0)
    4418:	32c0      	movi      	r2, 192
    441a:	3100      	movi      	r1, 0
    441c:	3000      	movi      	r0, 0
    441e:	e3fffade 	bsr      	0x39da	// 39da <USART_MODE_Config>
	//USART_CLKO_Config(ENABLE);														//同步模式下需要输出UARTCLK时,需要使能
    USART_Baudrate_Cal(115200,20000000,PCLK,ASYNC);									//波特率=38400, 主频选择20M, PCLK不分频, 异步模式							
    4422:	30e1      	movi      	r0, 225
    4424:	3300      	movi      	r3, 0
    4426:	3200      	movi      	r2, 0
    4428:	4009      	lsli      	r0, r0, 9
    442a:	1131      	lrw      	r1, 0x1312d00	// 44ec <GPT_CONFIG+0x9c>
    442c:	e3fffb1c 	bsr      	0x3a64	// 3a64 <USART_Baudrate_Cal>
	USART_CTRL_Config(TXEN,ENABLE);													//USART 发送使能
    4430:	3101      	movi      	r1, 1
    4432:	3006      	movi      	r0, 6
    4434:	e3fffaec 	bsr      	0x3a0c	// 3a0c <USART_CTRL_Config>
	USART_CTRL_Config(RXEN,ENABLE);													//USART 接收使能
    4438:	3101      	movi      	r1, 1
    443a:	3004      	movi      	r0, 4
    443c:	e3fffae8 	bsr      	0x3a0c	// 3a0c <USART_CTRL_Config>
	USART_INT_Config(RXRDY_INT,ENABLE);												//USART 接收中断使能
    4440:	3101      	movi      	r1, 1
    4442:	3000      	movi      	r0, 0
    4444:	e3fffab5 	bsr      	0x39ae	// 39ae <USART_INT_Config>
	//USART_INT_Config(TXRDY_INT,ENABLE);												//USART 发射中断使能	
	USART_Int_Enable();																//USART 中断向量使能
    4448:	e3fffa4e 	bsr      	0x38e4	// 38e4 <USART_Int_Enable>
	//USART_WakeUp_Enable();															//USART 中断唤醒使能
	
}
    444c:	1403      	addi      	sp, sp, 12
    444e:	1490      	pop      	r15

00004450 <GPT_CONFIG>:
//GPT Functions
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/ 
void GPT_CONFIG(void)
{
    4450:	14d3      	push      	r4-r6, r15
    4452:	1421      	subi      	sp, sp, 4
	GPT_RESET_VALUE(GPTCH0);												//GPT0 所有寄存器复位赋值
    4454:	11c7      	lrw      	r6, 0x20000034	// 44f0 <GPT_CONFIG+0xa0>
	GPT_RESET_VALUE(GPTCH1);												//GPT1 所有寄存器复位赋值
    4456:	11a8      	lrw      	r5, 0x20000030	// 44f4 <GPT_CONFIG+0xa4>
	GPT_RESET_VALUE(GPTCH2);												//GPT2 所有寄存器复位赋值
    4458:	1188      	lrw      	r4, 0x2000002c	// 44f8 <GPT_CONFIG+0xa8>
	GPT_RESET_VALUE(GPTCH0);												//GPT0 所有寄存器复位赋值
    445a:	9600      	ld.w      	r0, (r6, 0)
    445c:	e3ffee24 	bsr      	0x20a4	// 20a4 <GPT_RESET_VALUE>
	GPT_RESET_VALUE(GPTCH1);												//GPT1 所有寄存器复位赋值
    4460:	9500      	ld.w      	r0, (r5, 0)
    4462:	e3ffee21 	bsr      	0x20a4	// 20a4 <GPT_RESET_VALUE>
	GPT_RESET_VALUE(GPTCH2);												//GPT2 所有寄存器复位赋值
    4466:	9400      	ld.w      	r0, (r4, 0)
    4468:	e3ffee1e 	bsr      	0x20a4	// 20a4 <GPT_RESET_VALUE>
	//GPT_IO_Init(GPT_IO_IO1A,0);												//IO1A 初始化
	//GPT_IO_Init(GPT_IO_IO1B,0);												//IO1B 初始化
	//GPT_IO_Init(GPT_IO_IO2A,0);												//IO2A 初始化
	//GPT_IO_Init(GPT_IO_IO2B,0);												//IO2B 初始化	
	
	GPTCHX_Clk_CMD(GPTCH0,ENABLE);											//GPT0 时钟使能	
    446c:	9600      	ld.w      	r0, (r6, 0)
    446e:	3101      	movi      	r1, 1
    4470:	e3ffef40 	bsr      	0x22f0	// 22f0 <GPTCHX_Clk_CMD>
	GPTCHX_Clk_CMD(GPTCH1,ENABLE);											//GPT1 时钟使能
    4474:	9500      	ld.w      	r0, (r5, 0)
    4476:	3101      	movi      	r1, 1
    4478:	e3ffef3c 	bsr      	0x22f0	// 22f0 <GPTCHX_Clk_CMD>
	GPTCHX_Clk_CMD(GPTCH2,ENABLE);											//GPT2 时钟使能
    447c:	3101      	movi      	r1, 1
    447e:	9400      	ld.w      	r0, (r4, 0)
    4480:	e3ffef38 	bsr      	0x22f0	// 22f0 <GPTCHX_Clk_CMD>
	
	GPTCHX_SoftwareReset(GPTCH0);											//GPT0 软件复位
    4484:	9600      	ld.w      	r0, (r6, 0)
    4486:	e3ffef2b 	bsr      	0x22dc	// 22dc <GPTCHX_SoftwareReset>
	GPTCHX_SoftwareReset(GPTCH1);											//GPT1 软件复位
    448a:	9500      	ld.w      	r0, (r5, 0)
    448c:	e3ffef28 	bsr      	0x22dc	// 22dc <GPTCHX_SoftwareReset>
	GPTCHX_SoftwareReset(GPTCH2);											//GPT2 软件复位
    4490:	9400      	ld.w      	r0, (r4, 0)
    4492:	e3ffef25 	bsr      	0x22dc	// 22dc <GPTCHX_SoftwareReset>
	//-------------外部时钟XC0~XC2源输入口选择-------------------
	//GPTCHX_XCn_Configure(XC0_Configure,XC0_Selecte_TCLK0);					//XC0 选择 TCLK0
	//GPTCHX_XCn_Configure(XC1_Configure,XC1_Selecte_TCLK1);					//XC1 选择 TCLK1
	//GPTCHX_XCn_Configure(XC2_Configure,XC2_Selecte_TCLK2);					//XC2 选择 TCLK2
	
	GPTCHX_CLK_Configure(GPTCH0,GPT_Mclk_Selecte_Pclk,GptClks_MCLK_DIV1,GPTCHX_CLKI_0,GPTCHX_BURST_SET_None);	//GTP0 选择 PCLK 作为 MCLK;CLKS=MCLK/1;CLK上升沿计数;关闭群脉冲模式
    4496:	3300      	movi      	r3, 0
    4498:	b860      	st.w      	r3, (sp, 0)
    449a:	9600      	ld.w      	r0, (r6, 0)
    449c:	3200      	movi      	r2, 0
    449e:	3100      	movi      	r1, 0
    44a0:	e3ffef3e 	bsr      	0x231c	// 231c <GPTCHX_CLK_Configure>
	GPTCHX_CLK_Configure(GPTCH1,GPT_Mclk_Selecte_Pclk,GptClks_MCLK_DIV1,GPTCHX_CLKI_0,GPTCHX_BURST_SET_None);	//GTP1 选择 PCLK 作为 MCLK;CLKS=MCLK/1;CLK上升沿计数;关闭群脉冲模式
    44a4:	3300      	movi      	r3, 0
    44a6:	b860      	st.w      	r3, (sp, 0)
    44a8:	9500      	ld.w      	r0, (r5, 0)
    44aa:	3200      	movi      	r2, 0
    44ac:	3100      	movi      	r1, 0
    44ae:	e3ffef37 	bsr      	0x231c	// 231c <GPTCHX_CLK_Configure>
	GPTCHX_CLK_Configure(GPTCH2,GPT_Mclk_Selecte_Pclk,GptClks_MCLK_DIV1,GPTCHX_CLKI_0,GPTCHX_BURST_SET_None);	//GTP2 选择 PCLK 作为 MCLK;CLKS=MCLK/1;CLK上升沿计数;关闭群脉冲模式
    44b2:	3300      	movi      	r3, 0
    44b4:	b860      	st.w      	r3, (sp, 0)
    44b6:	3200      	movi      	r2, 0
    44b8:	9400      	ld.w      	r0, (r4, 0)
    44ba:	3100      	movi      	r1, 0
    44bc:	e3ffef30 	bsr      	0x231c	// 231c <GPTCHX_CLK_Configure>
	
	//------------RC匹配定时模块-------------------------
	GPTCHX_COUNT_Configure(GPTCH0,CPC_Reload_ENABLE);						//GPT0 RC匹配重新计数
    44c0:	3180      	movi      	r1, 128
    44c2:	9600      	ld.w      	r0, (r6, 0)
    44c4:	4127      	lsli      	r1, r1, 7
    44c6:	e3ffef78 	bsr      	0x23b6	// 23b6 <GPTCHX_COUNT_Configure>
	GPTCHX_COUNT_Configure(GPTCH1,CPC_Reload_ENABLE);						//GPT1 RC匹配重新计数
    44ca:	3180      	movi      	r1, 128
    44cc:	9500      	ld.w      	r0, (r5, 0)
    44ce:	4127      	lsli      	r1, r1, 7
    44d0:	e3ffef73 	bsr      	0x23b6	// 23b6 <GPTCHX_COUNT_Configure>
	GPTCHX_COUNT_Configure(GPTCH2,CPC_Reload_ENABLE);						//GPT2 RC匹配重新计数
    44d4:	3180      	movi      	r1, 128
    44d6:	9400      	ld.w      	r0, (r4, 0)
    44d8:	0412      	br      	0x44fc	// 44fc <GPT_CONFIG+0xac>
    44da:	0000      	bkpt
    44dc:	20000050 	.long	0x20000050
    44e0:	20000064 	.long	0x20000064
    44e4:	0026259f 	.long	0x0026259f
    44e8:	20000010 	.long	0x20000010
    44ec:	01312d00 	.long	0x01312d00
    44f0:	20000034 	.long	0x20000034
    44f4:	20000030 	.long	0x20000030
    44f8:	2000002c 	.long	0x2000002c
    44fc:	4127      	lsli      	r1, r1, 7
    44fe:	e3ffef5c 	bsr      	0x23b6	// 23b6 <GPTCHX_COUNT_Configure>
	//					TIOA_SWTRG_OutPut_High,TIOA_EEVT_OutPut_NoChange,TIOA_CPA_OutPut_Low,TIOA_CPC_OutPut_High,TIOB_SWTRG_OutPut_High,TIOB_EEVT_OutPut_NoChange,TIOB_CPB_OutPut_Low,TIOB_CPC_OutPut_High);
	//GPT1,RC匹配停止计数禁止;RC匹配停止计数时钟禁止;RC匹配重新计数禁止;外部事件触发重新计数禁止;外部事件XC0选择禁止;软件触发TIOA为高电平;外部事件触发TIOA不改变;RA匹配TIOA输出低电平;RC匹配TIOA输出高;软件触发TIOB为高电平;外部事件触发TIOB不改变;RB匹配TIOB输出低电平;RC匹配TIOB输出高
	//GPTCHX_PWM_Configure(GPTCH2,CPC_STOP_DISABLE,CPC_DisCountClk_DISABLE,CPC_Reload_ENABLE,EEVT_Reload_DISABLE,EEVT_XC0_NONE,
	//					TIOA_SWTRG_OutPut_High,TIOA_EEVT_OutPut_NoChange,TIOA_CPA_OutPut_Low,TIOA_CPC_OutPut_High,TIOB_SWTRG_OutPut_High,TIOB_EEVT_OutPut_NoChange,TIOB_CPB_OutPut_Low,TIOB_CPC_OutPut_High);
	//GPT2,RC匹配停止计数禁止;RC匹配停止计数时钟禁止;RC匹配重新计数禁止;外部事件触发重新计数禁止;外部事件XC0选择禁止;软件触发TIOA为高电平;外部事件间触发TIOA不改变;RA匹配TIOA输出低电平;RC匹配TIOA输出高;软件触发TIOB为高电平;外部事件触发TIOB不改变;RB匹配TIOB输出低电平;RC匹配TIOB输出高
	GPTCHX_Set_RA_RB_RC(GPTCH0,0,0,1000);				//GPT0 RA=0,RB=0,RC=1000
    4502:	33fa      	movi      	r3, 250
    4504:	9600      	ld.w      	r0, (r6, 0)
    4506:	4362      	lsli      	r3, r3, 2
    4508:	3200      	movi      	r2, 0
    450a:	3100      	movi      	r1, 0
    450c:	e3ffef03 	bsr      	0x2312	// 2312 <GPTCHX_Set_RA_RB_RC>
	GPTCHX_Set_RA_RB_RC(GPTCH1,0,0,1000);				//GPT1 RA=0,RB=0,RC=1000
    4510:	33fa      	movi      	r3, 250
    4512:	9500      	ld.w      	r0, (r5, 0)
    4514:	4362      	lsli      	r3, r3, 2
    4516:	3200      	movi      	r2, 0
    4518:	3100      	movi      	r1, 0
    451a:	e3ffeefc 	bsr      	0x2312	// 2312 <GPTCHX_Set_RA_RB_RC>
	GPTCHX_Set_RA_RB_RC(GPTCH2,0,0,1000);				//GPT2 RA=0,RB=0,RC=1000
    451e:	33fa      	movi      	r3, 250
    4520:	4362      	lsli      	r3, r3, 2
    4522:	9400      	ld.w      	r0, (r4, 0)
    4524:	3200      	movi      	r2, 0
    4526:	3100      	movi      	r1, 0
    4528:	e3ffeef5 	bsr      	0x2312	// 2312 <GPTCHX_Set_RA_RB_RC>
	
	//GPTCHX_ConfigInterrupt_CMD(GPTCH0,GPTCHX_INT_COVFS,ENABLE);			//使能 GPT0计数溢出中断
	//GPTCHX_ConfigInterrupt_CMD(GPTCH0,GPTCHX_INT_LOVRS,ENABLE);			//使能 GPT0载入溢出中断
	//GPTCHX_ConfigInterrupt_CMD(GPTCH0,GPTCHX_INT_CPAS,ENABLE);			//使能 GPT0比较寄存器A匹配中断
	//GPTCHX_ConfigInterrupt_CMD(GPTCH0,GPTCHX_INT_CPBS,ENABLE);			//使能 GPT0比较寄存器B匹配中断
	GPTCHX_ConfigInterrupt_CMD(GPTCH0,GPTCHX_INT_CPCS,ENABLE);			//使能 GPT0比较寄存器C匹配中断
    452c:	9600      	ld.w      	r0, (r6, 0)
    452e:	3201      	movi      	r2, 1
    4530:	3110      	movi      	r1, 16
    4532:	e3fff021 	bsr      	0x2574	// 2574 <GPTCHX_ConfigInterrupt_CMD>
	
	//GPTCHX_ConfigInterrupt_CMD(GPTCH1,GPTCHX_INT_COVFS,ENABLE);			//使能 GPT1计数溢出中断
	//GPTCHX_ConfigInterrupt_CMD(GPTCH1,GPTCHX_INT_LOVRS,ENABLE);			//使能 GPT1载入溢出中断
	//GPTCHX_ConfigInterrupt_CMD(GPTCH1,GPTCHX_INT_CPAS,ENABLE);			//使能 GPT1比较寄存器A匹配中断
	//GPTCHX_ConfigInterrupt_CMD(GPTCH1,GPTCHX_INT_CPBS,ENABLE);			//使能 GPT1比较寄存器B匹配中断
	GPTCHX_ConfigInterrupt_CMD(GPTCH1,GPTCHX_INT_CPCS,ENABLE);			//使能 GPT1比较寄存器C匹配中断
    4536:	9500      	ld.w      	r0, (r5, 0)
    4538:	3201      	movi      	r2, 1
    453a:	3110      	movi      	r1, 16
    453c:	e3fff01c 	bsr      	0x2574	// 2574 <GPTCHX_ConfigInterrupt_CMD>
	
	//GPTCHX_ConfigInterrupt_CMD(GPTCH2,GPTCHX_INT_COVFS,ENABLE);			//使能 GPT2计数溢出中断	
	//GPTCHX_ConfigInterrupt_CMD(GPTCH2,GPTCHX_INT_LOVRS,ENABLE);			//使能 GPT2载入溢出中断
	//GPTCHX_ConfigInterrupt_CMD(GPTCH2,GPTCHX_INT_CPAS,ENABLE);			//使能 GPT2比较寄存器A匹配中断
	//GPTCHX_ConfigInterrupt_CMD(GPTCH2,GPTCHX_INT_CPBS,ENABLE);			//使能 GPT2比较寄存器B匹配中断
	GPTCHX_ConfigInterrupt_CMD(GPTCH2,GPTCHX_INT_CPCS,ENABLE);			//使能 GPT2比较寄存器C匹配中断
    4540:	3201      	movi      	r2, 1
    4542:	9400      	ld.w      	r0, (r4, 0)
    4544:	3110      	movi      	r1, 16
    4546:	e3fff017 	bsr      	0x2574	// 2574 <GPTCHX_ConfigInterrupt_CMD>
	//GPTCHX_ConfigInterrupt_CMD(GPTCH2,GPTCHX_INT_LDRAS,ENABLE);			//使能 GPT2载入寄存器A中断
	//GPTCHX_ConfigInterrupt_CMD(GPTCH2,GPTCHX_INT_LDRBS,ENABLE);			//使能 GPT2载入寄存器B中断
	//GPTCHX_ConfigInterrupt_CMD(GPTCH2,GPTCHX_INT_ETRGS,ENABLE);			//使能 GPT2外部触发中断
	
	//---------------------GPT 开启-----------------------
	GPTCHX_CountClk_CMD(GPTCH0,ENABLE);									//使能 GPT0 计数时钟
    454a:	9600      	ld.w      	r0, (r6, 0)
    454c:	3101      	movi      	r1, 1
    454e:	e3ffeeca 	bsr      	0x22e2	// 22e2 <GPTCHX_CountClk_CMD>
	GPTCHX_CountClk_CMD(GPTCH1,ENABLE);									//使能 GPT1 计数时钟
    4552:	9500      	ld.w      	r0, (r5, 0)
    4554:	3101      	movi      	r1, 1
    4556:	e3ffeec6 	bsr      	0x22e2	// 22e2 <GPTCHX_CountClk_CMD>
	GPTCHX_CountClk_CMD(GPTCH2,ENABLE);									//使能 GPT2 计数时钟
    455a:	3101      	movi      	r1, 1
    455c:	9400      	ld.w      	r0, (r4, 0)
    455e:	e3ffeec2 	bsr      	0x22e2	// 22e2 <GPTCHX_CountClk_CMD>
	//All_GPT_SWTRG();													//GPT0、GPT1、GPT2同时触发
	GPTCHX_SWTRG(GPTCH0);												//软件触发GPT0  
    4562:	9600      	ld.w      	r0, (r6, 0)
    4564:	e3ffeeb9 	bsr      	0x22d6	// 22d6 <GPTCHX_SWTRG>
	GPTCHX_SWTRG(GPTCH1);												//软件触发GPT1  
    4568:	9500      	ld.w      	r0, (r5, 0)
    456a:	e3ffeeb6 	bsr      	0x22d6	// 22d6 <GPTCHX_SWTRG>
	GPTCHX_SWTRG(GPTCH2);												//软件触发GPT2  
    456e:	9400      	ld.w      	r0, (r4, 0)
    4570:	e3ffeeb3 	bsr      	0x22d6	// 22d6 <GPTCHX_SWTRG>
	
	GPTCH0_Int_Enable();												//使能 GPT0 中断向量
    4574:	e3fff00e 	bsr      	0x2590	// 2590 <GPTCH0_Int_Enable>
	GPTCH1_Int_Enable();												//使能 GPT1 中断向量
    4578:	e3fff012 	bsr      	0x259c	// 259c <GPTCH1_Int_Enable>
	GPTCH2_Int_Enable();												//使能 GPT2 中断向量
    457c:	e3fff016 	bsr      	0x25a8	// 25a8 <GPTCH2_Int_Enable>
	
}
    4580:	1401      	addi      	sp, sp, 4
    4582:	1493      	pop      	r4-r6, r15

00004584 <GTC_CONFIG>:
//gtc Functions
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/ 
void GTC_CONFIG(void)
{
    4584:	14d0      	push      	r15
    4586:	1422      	subi      	sp, sp, 8
    GTC_RESET_VALUE();                                                        	//GTC 所有寄存器复位赋值
    4588:	e3fff068 	bsr      	0x2658	// 2658 <GTC_RESET_VALUE>
	GTC_SoftwareReset();														//GTC 软件复位
    458c:	e3fff0b0 	bsr      	0x26ec	// 26ec <GTC_SoftwareReset>
    //GTC_IO_Init(GTC_IO_TXOUT , 0 );                                           //PWM输出初始化
    GTC_Configure(GTC_FIN_PCLK , 1 , 9 , Counter_Size_32BIT  , 100000 , 0);  		//TCCLK=sysclock/2^1/10，GTC_Clk-->1us
    4590:	3300      	movi      	r3, 0
    4592:	b861      	st.w      	r3, (sp, 0x4)
    4594:	0363      	lrw      	r3, 0x186a0	// 4804 <SPI_MASTER_CONFIG+0x22>
    4596:	3209      	movi      	r2, 9
    4598:	b860      	st.w      	r3, (sp, 0)
    459a:	3101      	movi      	r1, 1
    459c:	331f      	movi      	r3, 31
    459e:	3000      	movi      	r0, 0
    45a0:	e3fff077 	bsr      	0x268e	// 268e <GTC_Configure>
    GTC_ControlSet_Configure(GTC_ControlSet_REPEAT,ENABLE);                  	//使能循环重复模式
    45a4:	3080      	movi      	r0, 128
    45a6:	3101      	movi      	r1, 1
    45a8:	4006      	lsli      	r0, r0, 6
    45aa:	e3fff083 	bsr      	0x26b0	// 26b0 <GTC_ControlSet_Configure>
	//GTC_ControlSet_Configure(GTC_ControlSet_OUTST,ENABLE);                   		//计数开始时输出高电平
    //GTC_ControlSet_Configure(GTC_ControlSet_CAPT_F,ENABLE);                		//下降沿捕捉使能
    //GTC_ControlSet_Configure(GTC_ControlSet_CAPT_TCAP,ENABLE);            		//捕捉输入使能
    //GTC_ConfigInterrupt_CMD(GTC_STARTI, ENABLE);                         			//start中断使能
    //GTC_ConfigInterrupt_CMD(GTC_STOPI, ENABLE);                          			//stop中断使能
    GTC_ConfigInterrupt_CMD(GTC_PSTARTI, ENABLE);                          		//周期start中断使能
    45ae:	3101      	movi      	r1, 1
    45b0:	3004      	movi      	r0, 4
    45b2:	e3fff08f 	bsr      	0x26d0	// 26d0 <GTC_ConfigInterrupt_CMD>
    //GTC_ConfigInterrupt_CMD(GTC_PENDI, ENABLE);                          			//周期stop中断使能
    //GTC_ConfigInterrupt_CMD(GTC_MATI, ENABLE);                           			//脉冲匹配中断使能
    //GTC_ConfigInterrupt_CMD(GTC_OVFI, ENABLE);                           			//溢出中断使能
    //GTC_ConfigInterrupt_CMD(GTC_CAPTI, ENABLE);                          			//捕捉中断使能
    GTC_Start();                                                              	//start GTC
    45b6:	e3fff0a0 	bsr      	0x26f6	// 26f6 <GTC_Start>
    GTC_Int_Enable();                                                           //使能GTC中断向量
    45ba:	e3fff0bb 	bsr      	0x2730	// 2730 <GTC_Int_Enable>
	
}
    45be:	1402      	addi      	sp, sp, 8
    45c0:	1490      	pop      	r15

000045c2 <STC16_CONFIG>:
//stc16 Functions
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/ 
void STC16_CONFIG(void)
{
    45c2:	14d0      	push      	r15
    45c4:	1422      	subi      	sp, sp, 8
	STC16_RESET_VALUE();														//STC16 所有寄存器复位赋值
    45c6:	e3fff131 	bsr      	0x2828	// 2828 <STC16_RESET_VALUE>
	STC16_Softreset();															//STC16 软件复位
    45ca:	e3fff17c 	bsr      	0x28c2	// 28c2 <STC16_Softreset>
	
	//STC16_IO_Init(STC16_IO_CAP0,0);												//STC16 CAP0 初始化
	//STC16_IO_Init(STC16_IO_CAP1,0);												//STC16 CAP1 初始化
	
	STC16_Clk_CMD(ENABLE);														//STC16 时钟使能
    45ce:	3001      	movi      	r0, 1
    45d0:	e3fff16f 	bsr      	0x28ae	// 28ae <STC16_Clk_CMD>
	
	//STC16_Channel0_CMD(ENABLE);													//STC16 通道0使能
	//STC16_Channel1_CMD(ENABLE);													//STC16 通道1使能
	
	STC16_Configure(STC16_Count_mode_Continue,STC16_Count_STOPTYPE_StopConmand,STC16_CM0_Mode_Capture,STC16_CM1_Mode_Match,19,0);
    45d4:	3300      	movi      	r3, 0
    45d6:	b861      	st.w      	r3, (sp, 0x4)
    45d8:	3180      	movi      	r1, 128
    45da:	3313      	movi      	r3, 19
    45dc:	b860      	st.w      	r3, (sp, 0)
    45de:	3201      	movi      	r2, 1
    45e0:	3300      	movi      	r3, 0
    45e2:	4122      	lsli      	r1, r1, 2
    45e4:	3000      	movi      	r0, 0
    45e6:	e3fff1b6 	bsr      	0x2952	// 2952 <STC16_Configure>
	//STC16 Configure;设置为连续计数模式;单次计数模式下,选择立即停止模式;通道0作为捕捉模式;通道1作为匹配模式;stc16_timeclk=pclk/(19+1)/2^0=1us
	//STC16_Channel0_Capture_LoadMode_set(STC16_C0SR_CaptureFall);					//stc16 Channel0下降沿捕捉
	STC16_CNR_CC0_CC1_Load(10000,0,0);												//STC16 CNTR=50,CC0R=0,CC1R=0
    45ea:	3200      	movi      	r2, 0
    45ec:	3100      	movi      	r1, 0
    45ee:	0318      	lrw      	r0, 0x2710	// 4808 <SPI_MASTER_CONFIG+0x26>
    45f0:	e3fff1f9 	bsr      	0x29e2	// 29e2 <STC16_CNR_CC0_CC1_Load>
	
	
	//STC16_MINT_CMD(ST16_STARTI,ENABLE);											//STC16 STARTI中断使能
	//STC16_MINT_CMD(ST16_STOPI,ENABLE);											//STC16 STOP中断使能
	STC16_MINT_CMD(ST16_PENDI,ENABLE);											//STC16 周期结束中断使能	
    45f4:	3101      	movi      	r1, 1
    45f6:	3004      	movi      	r0, 4
    45f8:	e3fff193 	bsr      	0x291e	// 291e <STC16_MINT_CMD>
	//STC16_CINT_CMD(ST16_CC1RI,ENABLE);											//STC16 通道1上升沿中断使能
	//STC16_CINT_CMD(ST16_CC1FI,ENABLE);											//STC16 通道1下降沿中断使能
	//STC16_CINT_CMD(ST16_Match0,ENABLE);												//STC16 通道0匹配中断
	//STC16_CINT_CMD(ST16_Match1,ENABLE);												//STC16 通道1匹配中断
	
	STC16_Start();																//Start stc16
    45fc:	e3fff169 	bsr      	0x28ce	// 28ce <STC16_Start>
	STC16_Int_Enable();															//ENABLE STC16 中断向量
    4600:	e3fff1ff 	bsr      	0x29fe	// 29fe <STC16_Int_Enable>
	
}
    4604:	1402      	addi      	sp, sp, 8
    4606:	1490      	pop      	r15

00004608 <CTC_CONFIG>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/ 
//计算公式：Trct_ck * (2^32 - TIMDR) 
void CTC_CONFIG(void)
{
    4608:	14d0      	push      	r15
	CTC_RESET_VALUE();									//CTC 所有寄存器复位赋值
    460a:	e3fff21d 	bsr      	0x2a44	// 2a44 <CTC_RESET_VALUE>
	CTC_SoftReset();									//CTC 软件复位
    460e:	e3fff296 	bsr      	0x2b3a	// 2b3a <CTC_SoftReset>
	//CTC_IO_Init(0);										//BUZZ io 初始化
	CTC_Clk_CMD(ENABLE);								//使能 CTC_CLK
    4612:	3001      	movi      	r0, 1
    4614:	e3fff247 	bsr      	0x2aa2	// 2aa2 <CTC_Clk_CMD>
	CTC_Config(CTC_CLK_Source_set_EMOSC,CTC_BUZZ_Freq_1kHz,CTC_Count_Period_PRDR);		//CTC使用外部晶振振，buzz输出频率为1Khz, 计数周期2s,若计数周期大于2s,周期=PRDR*2S
    4618:	3238      	movi      	r2, 56
    461a:	3102      	movi      	r1, 2
    461c:	3000      	movi      	r0, 0
    461e:	e3fff27b 	bsr      	0x2b14	// 2b14 <CTC_Config>
	CTC->PRDR=0X02;
    4622:	137b      	lrw      	r3, 0x20000020	// 480c <SPI_MASTER_CONFIG+0x2a>
    4624:	3202      	movi      	r2, 2
    4626:	9360      	ld.w      	r3, (r3, 0)
    4628:	b345      	st.w      	r2, (r3, 0x14)
	CTC_INT_CMD(CTC_INT_PEND,ENABLE);					//使能 CTC PEND 中断
    462a:	3101      	movi      	r1, 1
    462c:	3001      	movi      	r0, 1
    462e:	e3fff265 	bsr      	0x2af8	// 2af8 <CTC_INT_CMD>
	//CTC_INT_CMD(CTC_INT_OVF,ENABLE);						//使能 CTC OVF 中断
	CTC_Start();										//CTC 开启
    4632:	e3fff289 	bsr      	0x2b44	// 2b44 <CTC_Start>
	CTC_Int_Enable();									//使能 CTC 中断向量		
    4636:	e3fff241 	bsr      	0x2ab8	// 2ab8 <CTC_Int_Enable>
	CTC_Wakeup_Enable();								//使能 CTC 唤醒
    463a:	e3fff24f 	bsr      	0x2ad8	// 2ad8 <CTC_Wakeup_Enable>
	
}
    463e:	1490      	pop      	r15

00004640 <CMP_CONFIG>:
//CMP Init
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void CMP_CONFIG(void)
{
    4640:	14d0      	push      	r15
    4642:	1423      	subi      	sp, sp, 12
	CMP_RESET_VALUE();								//CMP 所有寄存器复位赋值
    4644:	e3ffde14 	bsr      	0x26c	// 26c <CMP_RESET_VALUE>
	CMP_software_reset();							//CMP 软件复位	
    4648:	e3ffde34 	bsr      	0x2b0	// 2b0 <CMP_software_reset>
	
	CMP_IO_Init(CPINP0,0);							//CPINP0 初始化
    464c:	3100      	movi      	r1, 0
    464e:	3000      	movi      	r0, 0
    4650:	e3ffde6e 	bsr      	0x32c	// 32c <CMP_IO_Init>
	//CMP_IO_Init(CPINP6,0);							//CPINP6 初始化
	//CMP_IO_Init(CPINP7,0);							//CPINP7 初始化
	//CMP_IO_Init(CPINP8,0);							//CPINP8 初始化
	//CMP_IO_Init(CPINP9,0);							//CPINP9 初始化
	
	CMP_IO_Init(CPINN0,0);							//CPINN0 初始化	
    4654:	3100      	movi      	r1, 0
    4656:	300a      	movi      	r0, 10
    4658:	e3ffde6a 	bsr      	0x32c	// 32c <CMP_IO_Init>
	//CMP_IO_Init(CPINN1,0);							//CPINN1 初始化		
	//CMP_IO_Init(CPINN2,0);							//CPINN2 初始化	
	//CMP_IO_Init(CPINN3,0);							//CPINN3 初始化	
	//CMP_IO_Init(CPINN4,0);							//CPINN4 初始化	
	
	CMP_IO_Init(CP0_OUT,0);							//CP0_OUT 初始化	
    465c:	3100      	movi      	r1, 0
    465e:	300f      	movi      	r0, 15
    4660:	e3ffde66 	bsr      	0x32c	// 32c <CMP_IO_Init>
	//CMP_IO_Init(CP1_OUT,0);							//CP1_OUT 初始化	
	//CMP_IO_Init(CP2_OUT,0);							//CP2_OUT 初始化	
	//CMP_IO_Init(CP3_OUT,0);							//CP3_OUT 初始化	
	//CMP_IO_Init(CP4_OUT,0);							//CP4_OUT 初始化	
	
	CMP_INPCRX_Config(CMP0_NUM,248,0);						//比较器负向:CPINN0  比较器正向:CPINP0
    4664:	3200      	movi      	r2, 0
    4666:	31f8      	movi      	r1, 248
    4668:	3000      	movi      	r0, 0
    466a:	e3ffdf57 	bsr      	0x518	// 518 <CMP_INPCRX_Config>
	CMP_CLK_CMD(CMP0_NUM,ENABLE);							//比较器0时钟使能
    466e:	3101      	movi      	r1, 1
    4670:	3000      	movi      	r0, 0
    4672:	e3ffde25 	bsr      	0x2bc	// 2bc <CMP_CLK_CMD>
	CMP_CR_Config(CMP0_NUM,NHYST_0mv,PHYST_0mv,POLARITY_0,EVE_SEL_fall_rise,EN_FLTEN,CPOS_1);
    4676:	3380      	movi      	r3, 128
    4678:	4368      	lsli      	r3, r3, 8
    467a:	b862      	st.w      	r3, (sp, 0x8)
    467c:	3380      	movi      	r3, 128
    467e:	4363      	lsli      	r3, r3, 3
    4680:	b861      	st.w      	r3, (sp, 0x4)
    4682:	3380      	movi      	r3, 128
    4684:	4362      	lsli      	r3, r3, 2
    4686:	b860      	st.w      	r3, (sp, 0)
    4688:	3200      	movi      	r2, 0
    468a:	3300      	movi      	r3, 0
    468c:	3100      	movi      	r1, 0
    468e:	3000      	movi      	r0, 0
    4690:	e3ffdf96 	bsr      	0x5bc	// 5bc <CMP_CR_Config>
	//使能CMP0比较器，比较器正向和负向迟滞电压为0mV，比较器输出不反向，事件触发为上升沿和下降沿，滤波器使能，选择经过滤波器后输出
	CMPX_FLTCR_Config(CMP0_NUM,CMPX_CLK_PCLK,4,199);		//FLT_CK = 20M/(199+1)/2^4=160us; 滤波次数固定为3次 160us*3=480us
    4694:	33c7      	movi      	r3, 199
    4696:	3204      	movi      	r2, 4
    4698:	3100      	movi      	r1, 0
    469a:	3000      	movi      	r0, 0
    469c:	e3ffe050 	bsr      	0x73c	// 73c <CMPX_FLTCR_Config>
	CMP_Open(CMP0_NUM);										//比较器0打开
    46a0:	3000      	movi      	r0, 0
    46a2:	e3ffdffd 	bsr      	0x69c	// 69c <CMP_Open>
	CMP->ICR =	EDGEDET0;									//清除CMP0中断标志位
    46a6:	127b      	lrw      	r3, 0x20000004	// 4810 <SPI_MASTER_CONFIG+0x2e>
    46a8:	3201      	movi      	r2, 1
    46aa:	9360      	ld.w      	r3, (r3, 0)
    46ac:	b357      	st.w      	r2, (r3, 0x5c)
	CMP_ConfigInterrupt_CMD(EDGEDET0,ENABLE);				//CMP0 中断使能
    46ae:	3101      	movi      	r1, 1
    46b0:	3001      	movi      	r0, 1
    46b2:	e3ffe11f 	bsr      	0x8f0	// 8f0 <CMP_ConfigInterrupt_CMD>
	//CMPX_FLTCR_Config(CMP4_NUM,CMPX_CLK_PCLK,4,199);			//FLT_CK = 20M/(199+1)/2^4=160ms; 滤波次数固定为3次
	//CMP_Open(CMP4_NUM);										//比较器4打开
	//CMP->ICR = EDGEDET4;										//清除CMP4中断标志位
	//CMP_ConfigInterrupt_CMD(EDGEDET4,ENABLE);					//CMP4 中断使能
	
	CMP0_Int_Enable();										//CMP0~CMP1 中断向量使能
    46b6:	e3ffe12b 	bsr      	0x90c	// 90c <CMP0_Int_Enable>
	//CMP1_Int_Enable();										//CMP2~CMP3 中断向量使能
	
}
    46ba:	1403      	addi      	sp, sp, 12
    46bc:	1490      	pop      	r15

000046be <OPAMP_CONFIG>:
//OPAMP Init
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/ 
void OPAMP_CONFIG(void)
{
    46be:	14d0      	push      	r15
    46c0:	1422      	subi      	sp, sp, 8
	OPA_RESET_VALUE();										//OPAx 所有寄存器复位赋值
    46c2:	e3ffe961 	bsr      	0x1984	// 1984 <OPA_RESET_VALUE>
	
	OPA_IO_Init(OPA0P,0);									//OPA0P 初始化				
    46c6:	3100      	movi      	r1, 0
    46c8:	3001      	movi      	r0, 1
    46ca:	e3ffe967 	bsr      	0x1998	// 1998 <OPA_IO_Init>
	//OPA_IO_Init(OPA0N,0);									//OPA0N 初始化				
	OPA_IO_Init(OPA0X,0);									//OPA0X 初始化				
    46ce:	3100      	movi      	r1, 0
    46d0:	3003      	movi      	r0, 3
    46d2:	e3ffe963 	bsr      	0x1998	// 1998 <OPA_IO_Init>
	
	OPA_IO_Init(OPA1P,0);									//OPA1P 初始化		
    46d6:	3100      	movi      	r1, 0
    46d8:	3004      	movi      	r0, 4
    46da:	e3ffe95f 	bsr      	0x1998	// 1998 <OPA_IO_Init>
	//OPA_IO_Init(OPA1N,0);									//OPA1N 初始化		
	OPA_IO_Init(OPA1X,0);									//OPA1X 初始化		
    46de:	3100      	movi      	r1, 0
    46e0:	3006      	movi      	r0, 6
    46e2:	e3ffe95b 	bsr      	0x1998	// 1998 <OPA_IO_Init>
	
	OPA_EN_CMD(OPA0_NUM,ENABLE);							//OPA0  ENABLE
    46e6:	3101      	movi      	r1, 1
    46e8:	3000      	movi      	r0, 0
    46ea:	e3ffe9a5 	bsr      	0x1a34	// 1a34 <OPA_EN_CMD>
	OPA_EN_CMD(OPA1_NUM,ENABLE);							//OPA1  ENABLE
    46ee:	3101      	movi      	r1, 1
    46f0:	3001      	movi      	r0, 1
    46f2:	e3ffe9a1 	bsr      	0x1a34	// 1a34 <OPA_EN_CMD>
	
	OPA_Config_Prg(OPA0_NUM,PGAEN_ENABLE,Op_ExtPinConnect_DIS,0,4,0);			//OPA0,使能内部增益控制,负向输入口与PIN脚连通禁止,正向输入口为OPA0P,增益x5,微调增益0
    46f6:	3300      	movi      	r3, 0
    46f8:	b861      	st.w      	r3, (sp, 0x4)
    46fa:	3304      	movi      	r3, 4
    46fc:	b860      	st.w      	r3, (sp, 0)
    46fe:	3200      	movi      	r2, 0
    4700:	3300      	movi      	r3, 0
    4702:	3101      	movi      	r1, 1
    4704:	3000      	movi      	r0, 0
    4706:	e3ffe9b0 	bsr      	0x1a66	// 1a66 <OPA_Config_Prg>
	OPA_Config_Prg(OPA1_NUM,PGAEN_ENABLE,Op_ExtPinConnect_DIS,0,1,0);			//OPA1,使能内部增益控制,负向输入口与PIN脚连通禁止,正向输入口为OPA1P,增益x10,微调增益0
    470a:	3300      	movi      	r3, 0
    470c:	b861      	st.w      	r3, (sp, 0x4)
    470e:	3301      	movi      	r3, 1
    4710:	b860      	st.w      	r3, (sp, 0)
    4712:	3200      	movi      	r2, 0
    4714:	3300      	movi      	r3, 0
    4716:	3101      	movi      	r1, 1
    4718:	3001      	movi      	r0, 1
    471a:	e3ffe9a6 	bsr      	0x1a66	// 1a66 <OPA_Config_Prg>
	
}
    471e:	1402      	addi      	sp, sp, 8
    4720:	1490      	pop      	r15

00004722 <EPWM_CONFIG>:
/*                   - PX ---                           -- PWM_X        */
/*      PWM Engine --         ---PWM output Control ---                 */
/*                   -PY ---                            --PWM_Y         */
/*************************************************************************/ 
void EPWM_CONFIG(void)
{
    4722:	14d0      	push      	r15
    4724:	1425      	subi      	sp, sp, 20
	EPWM_RESET_VALUE();									//EPWM 所有寄存器复位赋值
    4726:	e3ffe137 	bsr      	0x994	// 994 <EPWM_RESET_VALUE>
	EPWM_software_reset();								//EPWM 软件复位	
    472a:	e3ffe3fc 	bsr      	0xf22	// f22 <EPWM_software_reset>
	
	//EPWM_IO_Init(PWM_X0,0);							//PWM_X0 初始化
	EPWM_IO_Init(PWM_Y0,1);							//PWM_Y0 初始化
    472e:	3101      	movi      	r1, 1
    4730:	3001      	movi      	r0, 1
    4732:	e3ffe16f 	bsr      	0xa10	// a10 <EPWM_IO_Init>
	//EPWM_IO_Init(PWM_EP1,0);							//PWM_EP1 初始化
	//EPWM_IO_Init(PWM_EP2,0);							//PWM_EP2 初始化
	//EPWM_IO_Init(PWM_EP3,0);							//PWM_EP3 初始化
	//EPWM_IO_Init(PWM_EP4,0);							//PWM_EP4 初始化
		
	EPWM_CONTER_Configure(EPWM_ContMode_decrease,EPWM_Conter_three,EMP_Overflow_Mode_Continue,0,1);		//递减计数, EPMW_CLK=PCLK/(2^DIVN)/(DINM+1)=20M/2/(9+1)=1M=1US, 单次触发
    4736:	3301      	movi      	r3, 1
    4738:	b860      	st.w      	r3, (sp, 0)
    473a:	3200      	movi      	r2, 0
    473c:	3300      	movi      	r3, 0
    473e:	3100      	movi      	r1, 0
    4740:	3008      	movi      	r0, 8
    4742:	e3ffe293 	bsr      	0xc68	// c68 <EPWM_CONTER_Configure>
	
	//EPWM_PX_PY_Configure(EPWM_P0X,EPWM_StartStopEvent_OutHigh,EPWM_PendEvent_OutHigh,EPWM_CentralEvent_NoChange,EPWM_EqCMPAEvent_OutLow,EPWM_EqCMPBEvent_NoChange,1000,500,0);	//P0X CNTR=1000,CMPAR=500,CMPBR=0
	EPWM_PX_PY_Configure(EPWM_P0Y,EPWM_StartStopEvent_OutLow,EPWM_PendEvent_OutLow,EPWM_CentralEvent_NoChange,EPWM_EqCMPAEvent_OutHigh,EPWM_EqCMPBEvent_NoChange,1000,500,0);		//P0Y CNTR=1000,CMPAR=500,CMPBR=0
    4746:	3300      	movi      	r3, 0
    4748:	b864      	st.w      	r3, (sp, 0x10)
    474a:	33fa      	movi      	r3, 250
    474c:	4361      	lsli      	r3, r3, 1
    474e:	b863      	st.w      	r3, (sp, 0xc)
    4750:	33fa      	movi      	r3, 250
    4752:	4362      	lsli      	r3, r3, 2
    4754:	b862      	st.w      	r3, (sp, 0x8)
    4756:	3300      	movi      	r3, 0
    4758:	b861      	st.w      	r3, (sp, 0x4)
    475a:	3302      	movi      	r3, 2
    475c:	b860      	st.w      	r3, (sp, 0)
    475e:	3201      	movi      	r2, 1
    4760:	3300      	movi      	r3, 0
    4762:	3101      	movi      	r1, 1
    4764:	3001      	movi      	r0, 1
    4766:	e3ffe292 	bsr      	0xc8a	// c8a <EPWM_PX_PY_Configure>
	//EPWM_PX_PY_Configure(EPWM_P1X,EPWM_StartStopEvent_OutHigh,EPWM_PendEvent_OutHigh,EPWM_CentralEvent_NoChange,EPWM_EqCMPAEvent_OutLow,EPWM_EqCMPBEvent_NoChange,1000,500,0);	//P1X CNTR=1000,CMPAR=500,CMPBR=0
	//EPWM_PX_PY_Configure(EPWM_P1Y,EPWM_StartStopEvent_OutLow,EPWM_PendEvent_OutLow,EPWM_CentralEvent_NoChange,EPWM_EqCMPAEvent_OutHigh,EPWM_EqCMPBEvent_NoChange,1000,500,0);		//P1Y CNTR=1000,CMPAR=500,CMPBR=0
	//EPWM_PX_PY_Configure(EPWM_P2X,EPWM_StartStopEvent_OutHigh,EPWM_PendEvent_OutHigh,EPWM_CentralEvent_NoChange,EPWM_EqCMPAEvent_OutLow,EPWM_EqCMPBEvent_NoChange,1000,500,0);	//P2X CNTR=1000,CMPAR=500,CMPBR=0
	//EPWM_PX_PY_Configure(EPWM_P2Y,EPWM_StartStopEvent_OutLow,EPWM_PendEvent_OutLow,EPWM_CentralEvent_NoChange,EPWM_EqCMPAEvent_OutHigh,EPWM_EqCMPBEvent_NoChange,1000,500,0);		//P2Y CNTR=1000,CMPAR=500,CMPBR=0
	
	EPWM_OUTPUT_Configure(EPWM_PWM_X0OrPWM_Y0,EPWM_OUTSE_PXPYOutputDirect,EPWM_X_POLARITY_NoChange,EPWM_Y_POLARITY_NoChange,EPWM_SRCSEL_PX,0x10,0x10);		//PWM_X PWM_Y 直接输出模式,输出端电平保持不变,RED=EPMW_CLK*16=16us,FED=EPMW_CLK*16=16us								
    476a:	3310      	movi      	r3, 16
    476c:	b862      	st.w      	r3, (sp, 0x8)
    476e:	b861      	st.w      	r3, (sp, 0x4)
    4770:	3300      	movi      	r3, 0
    4772:	b860      	st.w      	r3, (sp, 0)
    4774:	3200      	movi      	r2, 0
    4776:	3100      	movi      	r1, 0
    4778:	3000      	movi      	r0, 0
    477a:	e3ffe35a 	bsr      	0xe2e	// e2e <EPWM_OUTPUT_Configure>
	EPWM_OUTPUT_Configure(EPWM_PWM_X1OrPWM_Y1,EPWM_OUTSE_PXPYOutputDirect,EPWM_X_POLARITY_NoChange,EPWM_Y_POLARITY_NoChange,EPWM_SRCSEL_PX,0x10,0x10);		//PWM_X PWM_Y 直接输出模式,输出端电平保持不变,RED=EPMW_CLK*16=16us,FED=EPMW_CLK*16=16us						
    477e:	3310      	movi      	r3, 16
    4780:	b862      	st.w      	r3, (sp, 0x8)
    4782:	b861      	st.w      	r3, (sp, 0x4)
    4784:	3300      	movi      	r3, 0
    4786:	b860      	st.w      	r3, (sp, 0)
    4788:	3200      	movi      	r2, 0
    478a:	3100      	movi      	r1, 0
    478c:	3001      	movi      	r0, 1
    478e:	e3ffe350 	bsr      	0xe2e	// e2e <EPWM_OUTPUT_Configure>
	EPWM_OUTPUT_Configure(EPWM_PWM_X2OrPWM_Y2,EPWM_OUTSE_PXPYOutputDirect,EPWM_X_POLARITY_NoChange,EPWM_Y_POLARITY_NoChange,EPWM_SRCSEL_PX,0x10,0x10);		//PWM_X PWM_Y 直接输出模式,输出端电平保持不变,RED=EPMW_CLK*16=16us,FED=EPMW_CLK*16=16us	
    4792:	3310      	movi      	r3, 16
    4794:	b862      	st.w      	r3, (sp, 0x8)
    4796:	b861      	st.w      	r3, (sp, 0x4)
    4798:	3300      	movi      	r3, 0
    479a:	b860      	st.w      	r3, (sp, 0)
    479c:	3200      	movi      	r2, 0
    479e:	3100      	movi      	r1, 0
    47a0:	3002      	movi      	r0, 2
    47a2:	e3ffe346 	bsr      	0xe2e	// e2e <EPWM_OUTPUT_Configure>
	//EPWM_ConfigInterrupt_CMD(EPWM2_CMPADM,ENABLE);			//使能 Count2递减CMPA匹配中断
	//EPWM_ConfigInterrupt_CMD(EPWM2_CMPBUM,ENABLE);			//使能 Count2递增CMPB匹配中断
	//EPWM_ConfigInterrupt_CMD(EPWM2_CMPBDM,ENABLE);			//使能 Count2递减CMPB配置中断
	
	//EPWM_AllConter_START();					//Count0~Count3 同时开启
	EPWM_Conter0_START();						//Count0 开启	
    47a6:	e3ffe3ca 	bsr      	0xf3a	// f3a <EPWM_Conter0_START>
	//EPWM_Conter1_START();						//Count1 开启
	//EPWM_Conter2_START();						//Count2 开启
	
	//EPWM_Int_Enable();						//使能 EPWM 中断向量
	
} 
    47aa:	1405      	addi      	sp, sp, 20
    47ac:	1490      	pop      	r15

000047ae <I2C_MASTER_CONFIG>:
//I2C MASTER Initial
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/	
void I2C_MASTER_CONFIG(void)
{
    47ae:	14d0      	push      	r15
    I2C_DeInit();                                           //所有寄存器复位赋值
    47b0:	e3fff504 	bsr      	0x31b8	// 31b8 <I2C_DeInit>
    I2C_Master_Init(I2C_G0,FAST_MODE,0x040,0x20);           //查询方式参数配置
    47b4:	3320      	movi      	r3, 32
    47b6:	3240      	movi      	r2, 64
    47b8:	3101      	movi      	r1, 1
    47ba:	3000      	movi      	r0, 0
    47bc:	e3fff50e 	bsr      	0x31d8	// 31d8 <I2C_Master_Init>
	//I2C_Master_Init(I2C_G0,FAST_MODE,0x70,0x30);			//INT方式参数配置			
    //I2C_Int_Enable();                                      //I2C中断向量使能
	
}
    47c0:	1490      	pop      	r15

000047c2 <I2C_SLAVE_CONFIG>:
//I2C SLAVE Initial
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/	
void I2C_SLAVE_CONFIG(void)
{
    47c2:	14d0      	push      	r15
    47c4:	1421      	subi      	sp, sp, 4
    I2C_DeInit();                                           //所有寄存器复位赋值
    47c6:	e3fff4f9 	bsr      	0x31b8	// 31b8 <I2C_DeInit>
    I2C_Slave_Init(I2C_G2,FAST_MODE,0x4F,0x40,0xAE);        //从机地址=0xae(8bit), 快速模式, sysclock=20M, 通讯速度=sysclock/(0x4f+4)=240K
    47ca:	33ae      	movi      	r3, 174
    47cc:	b860      	st.w      	r3, (sp, 0)
    47ce:	324f      	movi      	r2, 79
    47d0:	3340      	movi      	r3, 64
    47d2:	3101      	movi      	r1, 1
    47d4:	3002      	movi      	r0, 2
    47d6:	e3fff53c 	bsr      	0x324e	// 324e <I2C_Slave_Init>
    I2C_Int_Enable();                                       //I2C中断向量使能
    47da:	e3fff588 	bsr      	0x32ea	// 32ea <I2C_Int_Enable>
	
} 
    47de:	1401      	addi      	sp, sp, 4
    47e0:	1490      	pop      	r15

000047e2 <SPI_MASTER_CONFIG>:
//SPI MASTER Initial
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/	
void SPI_MASTER_CONFIG(void)
{
    47e2:	14d0      	push      	r15
    47e4:	1424      	subi      	sp, sp, 16
	SPI_DeInit();
    47e6:	e3fff9bb 	bsr      	0x3b5c	// 3b5c <SPI_DeInit>
	SPI_NSS_IO_Init(1);
    47ea:	3001      	movi      	r0, 1
    47ec:	e3fff9cc 	bsr      	0x3b84	// 3b84 <SPI_NSS_IO_Init>
	SPI_Master_Init(SPI_G1,SPI_DATA_SIZE_8BIT,SPI_SPO_0,SPI_SPH_0,SPI_LBM_0,SPI_RXIFLSEL_1_8,0,10);
    47f0:	330a      	movi      	r3, 10
    47f2:	b863      	st.w      	r3, (sp, 0xc)
    47f4:	3300      	movi      	r3, 0
    47f6:	b862      	st.w      	r3, (sp, 0x8)
    47f8:	3301      	movi      	r3, 1
    47fa:	b861      	st.w      	r3, (sp, 0x4)
    47fc:	3300      	movi      	r3, 0
    47fe:	b860      	st.w      	r3, (sp, 0)
    4800:	3200      	movi      	r2, 0
    4802:	0409      	br      	0x4814	// 4814 <SPI_MASTER_CONFIG+0x32>
    4804:	000186a0 	.long	0x000186a0
    4808:	00002710 	.long	0x00002710
    480c:	20000020 	.long	0x20000020
    4810:	20000004 	.long	0x20000004
    4814:	3107      	movi      	r1, 7
    4816:	3001      	movi      	r0, 1
    4818:	e3fff9d4 	bsr      	0x3bc0	// 3bc0 <SPI_Master_Init>
	//选择SPI IO group1; 发送数据大小为8BIT; SCK工作时为高电平; SCK第一个时钟沿捕捉; 串行正常输出; 接收占用1/8 FIFO中断触发断点; FSSPCLKOUT=20M/10=1M
	//SPI_ConfigInterrupt_CMD(SPI_RXIM,ENABLE);				//使能FIFO接收中断
	//SPI_Int_Enable();										//使能SPI中断向量
	
}
    481c:	1404      	addi      	sp, sp, 16
    481e:	1490      	pop      	r15

00004820 <SPI_SLAVE_CONFIG>:
//SPI SLAVE Initial
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/	
void SPI_SLAVE_CONFIG(void)
{
    4820:	14d0      	push      	r15
    4822:	1421      	subi      	sp, sp, 4
	SPI_DeInit();
    4824:	e3fff99c 	bsr      	0x3b5c	// 3b5c <SPI_DeInit>
	SPI_NSS_IO_Init(1);
    4828:	3001      	movi      	r0, 1
    482a:	e3fff9ad 	bsr      	0x3b84	// 3b84 <SPI_NSS_IO_Init>
	SPI_Slave_Init(SPI_G1,SPI_DATA_SIZE_8BIT,SPI_RXIFLSEL_1_8,0,12);			
    482e:	330c      	movi      	r3, 12
    4830:	3201      	movi      	r2, 1
    4832:	b860      	st.w      	r3, (sp, 0)
    4834:	3107      	movi      	r1, 7
    4836:	3300      	movi      	r3, 0
    4838:	3001      	movi      	r0, 1
    483a:	e3fff9f8 	bsr      	0x3c2a	// 3c2a <SPI_Slave_Init>
	//选择SPI IO group1; 发送数据大小为8BIT;接收占用1/8 FIFO中断触发断点 ;FSSPCLKOUT=20M/12=1.6M
	SPI_ConfigInterrupt_CMD(SPI_RXIM,ENABLE);				//使能FIFO接收中断
    483e:	3101      	movi      	r1, 1
    4840:	3004      	movi      	r0, 4
    4842:	e3fffa3e 	bsr      	0x3cbe	// 3cbe <SPI_ConfigInterrupt_CMD>
	SPI_Int_Enable();										//使能SPI中断向量
    4846:	e3fffa4a 	bsr      	0x3cda	// 3cda <SPI_Int_Enable>
}
    484a:	1401      	addi      	sp, sp, 4
    484c:	1490      	pop      	r15

0000484e <SYSCON_CONFIG>:
//syscon Functions
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_CONFIG(void)
{
    484e:	14d0      	push      	r15
//------SYSTEM CLK AND PCLK FUNTION---------------------------/
    SYSCON_RST_VALUE();                                                         //SYSCON所有寄存器复位赋值
    4850:	e3ffe990 	bsr      	0x1b70	// 1b70 <SYSCON_RST_VALUE>
	//SYSCON_General_CMD(ENABLE,ENDIS_IDLE_PCLK);								//SLEEP模式下PCLK使能
    SYSCON_General_CMD(ENABLE,ENDIS_ISOSC);                                     //使能/禁止内部副频
    4854:	3101      	movi      	r1, 1
    4856:	3001      	movi      	r0, 1
    4858:	e3ffe9c4 	bsr      	0x1be0	// 1be0 <SYSCON_General_CMD>
    SYSCON_General_CMD(ENABLE,ENDIS_IMOSC);	                                    //使能/禁止内部主频
    485c:	3102      	movi      	r1, 2
    485e:	3001      	movi      	r0, 1
    4860:	e3ffe9c0 	bsr      	0x1be0	// 1be0 <SYSCON_General_CMD>
	SYSCON_General_CMD(DISABLE,ENDIS_EMOSC);	                                //使能/禁止外部晶振
    4864:	3108      	movi      	r1, 8
    4866:	3000      	movi      	r0, 0
    4868:	e3ffe9bc 	bsr      	0x1be0	// 1be0 <SYSCON_General_CMD>
	//SYSON_EMOSC_32k_EN();														//使能 外部晶振外接 32.768K
	SYSCON_IMOSC_SETECTE(IMOSC_SETECTE_20M);									//选择内部主频为20M
    486c:	3001      	movi      	r0, 1
    486e:	e3ffeadc 	bsr      	0x1e26	// 1e26 <SYSCON_IMOSC_SETECTE>
    SystemCLK_HCLKDIV_PCLKDIV_Config(SYSCLK_IMOSC,HCLK_DIV_1,PCLK_DIV_1);       //内部主振作为系统时钟，HCLK 1分频，PCLK 1分频
    4872:	3180      	movi      	r1, 128
    4874:	3200      	movi      	r2, 0
    4876:	4121      	lsli      	r1, r1, 1
    4878:	3000      	movi      	r0, 0
    487a:	e3ffe9c2 	bsr      	0x1bfe	// 1bfe <SystemCLK_HCLKDIV_PCLKDIV_Config>
//------------  WDT FUNTION  --------------------------------/
    SYSCON_IWDCNT_Config(IWDT_TIME_1S,IWDT_INTW_DIV_1);     					//WDT溢出时间1s;WDT TEIM:1S*(1-(8-1)/8)=0.75S
    487e:	30c0      	movi      	r0, 192
    4880:	3118      	movi      	r1, 24
    4882:	4002      	lsli      	r0, r0, 2
    4884:	e3ffea02 	bsr      	0x1c88	// 1c88 <SYSCON_IWDCNT_Config>
    //SYSCON_WDT_CMD(ENABLE);                                                   //禁止WDT功能
    SYSCON_WDT_CMD(DISABLE);
    4888:	3000      	movi      	r0, 0
    488a:	e3ffe9d9 	bsr      	0x1c3c	// 1c3c <SYSCON_WDT_CMD>
    SYSCON_IWDCNT_Reload();                                                     //清狗
    488e:	e3ffe9f6 	bsr      	0x1c7a	// 1c7a <SYSCON_IWDCNT_Reload>
	//SYSCON->IECR|=IWDT_INT_ST;												//使能WDT报警中断
	//SYSCON_WakeUp_Enable();													//使能syscon中断唤醒
//------------  LVD FUNTION  --------------------------------/ 
	LVR_Enable();																//Disable LVR ,上电缺省LVR Enable,
    4892:	e3ffea18 	bsr      	0x1cc2	// 1cc2 <LVR_Enable>
    SYSCON_LVD_Config(ENABLE_LVDEN,INTDET_LVL_2_5V,RSTDET_LVL_2_2V,ENABLE_LVD_INT);	//使能LVD LVR功能, LVD检测电压2.5V, LVR检测电压2.2V, 使能LVD中断
    4896:	3380      	movi      	r3, 128
    4898:	4364      	lsli      	r3, r3, 4
    489a:	3200      	movi      	r2, 0
    489c:	3100      	movi      	r1, 0
    489e:	3000      	movi      	r0, 0
    48a0:	e3ffe9fc 	bsr      	0x1c98	// 1c98 <SYSCON_LVD_Config>
    //LVD_Int_Enable();															//使能LVD中断向量
}
    48a4:	1490      	pop      	r15

000048a6 <APT32F172_init>:
//APT32F172_init                                                                  /
//EntryParameter:NONE                                                             /
//ReturnValue:NONE                                                                /
/*********************************************************************************/
void APT32F172_init(void) 
{
    48a6:	14d1      	push      	r4, r15
//------------------------------------------------------------/
//Peripheral clock enable and disable
//EntryParameter:NONE
//ReturnValue:NONE
//------------------------------------------------------------/
	SYSCON_WDT_CMD(DISABLE);                                        //禁止 WDT
    48a8:	3000      	movi      	r0, 0
    48aa:	e3ffe9c9 	bsr      	0x1c3c	// 1c3c <SYSCON_WDT_CMD>
	SYSCON->PCER0=0xFFFFFFF;                                        //使能IP
    48ae:	106e      	lrw      	r3, 0x2000005c	// 48e4 <APT32F172_init+0x3e>
    48b0:	102e      	lrw      	r1, 0xfffffff	// 48e8 <APT32F172_init+0x42>
    48b2:	9340      	ld.w      	r2, (r3, 0)
    48b4:	b22a      	st.w      	r1, (r2, 0x28)
    48b6:	6d0f      	mov      	r4, r3
    SYSCON->PCER1=0xFFFFFFF;                                        //使能IP
    48b8:	b22d      	st.w      	r1, (r2, 0x34)
	while(!(SYSCON->PCSR0&0x1));                                    //判断IP是否使能
    48ba:	3101      	movi      	r1, 1
    48bc:	926c      	ld.w      	r3, (r2, 0x30)
    48be:	68c4      	and      	r3, r1
    48c0:	3b40      	cmpnei      	r3, 0
    48c2:	0ffd      	bf      	0x48bc	// 48bc <APT32F172_init+0x16>
//------------------------------------------------------------/
//ISOSC/IMOSC/EMOSC/SYSCLK/IWDT/LVD/EM_CMFAIL/EM_CMRCV/CMD_ERR OSC stable interrupt
//EntryParameter:NONE
//ReturnValue:NONE
//------------------------------------------------------------/
	SYSCON_Int_Enable();                                             //使能SYSCON中断向量
    48c4:	e3ffeb9f 	bsr      	0x2002	// 2002 <SYSCON_Int_Enable>
	SYSCON->IECR=ISOSC_ST|IMOSC_ST|EMOSC_ST|SYSCLK_ST;               //使能 ISOSC时钟稳定中断,使能IMOSC 时钟稳定中断,使能EMOSC时钟稳定中断
    48c8:	9460      	ld.w      	r3, (r4, 0)
    48ca:	328b      	movi      	r2, 139
    48cc:	b35d      	st.w      	r2, (r3, 0x74)
	CK_CPU_EnAllNormalIrq();                                         //打开全局中断
    48ce:	e3ffdcc6 	bsr      	0x25a	// 25a <CK_CPU_EnAllNormalIrq>
	SYSCON_CONFIG();                                                 //syscon参数 初始化
    48d2:	e3ffffbe 	bsr      	0x484e	// 484e <SYSCON_CONFIG>
	//CMP_CONFIG();													 	//CMP 初始化
	//OPAMP_CONFIG();													//OPAMP 初始化
	//ADC_CONFIG();														//ADC 初始化
	//EPWM_CONFIG();													//EPWM 初始化
	//LED_CONFIG();														//LED 初始化
	CORET_CONFIG();														//CORET 初始化 1000ms@20M
    48d6:	e3fffcf0 	bsr      	0x42b6	// 42b6 <CORET_CONFIG>
	//GPT_CONFIG();														//GPT 初始化
	GTC_CONFIG();														//GTC 初始化  100ms@20M
    48da:	e3fffe55 	bsr      	0x4584	// 4584 <GTC_CONFIG>
	STC16_CONFIG();													//STC16 初始化		10ms@20M
    48de:	e3fffe72 	bsr      	0x45c2	// 45c2 <STC16_CONFIG>
    //I2C_SLAVE_CONFIG();                                           	//I2C 作从机 初始化 	
	//SPI_MASTER_CONFIG();												//SPI 作主机 初始化 	
	//SPI_SLAVE_CONFIG();												//SPI 作从机 初始化  
	//UART_CONFIG();													//UART 初始化
	//USART_CONFIG();													//USART 初始化
}		
    48e2:	1491      	pop      	r4, r15
    48e4:	2000005c 	.long	0x2000005c
    48e8:	0fffffff 	.long	0x0fffffff

000048ec <CORETHandler>:
//CORET Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORETHandler(void) 
{
    48ec:	1460      	nie
    48ee:	1462      	ipush
    // ISR content ...
	
	CK801->CORET_CVR = 0;							// Coret CVR 清除
    48f0:	1063      	lrw      	r3, 0x20000064	// 48fc <CORETHandler+0x10>
    48f2:	3200      	movi      	r2, 0
    48f4:	9360      	ld.w      	r3, (r3, 0)
    48f6:	b346      	st.w      	r2, (r3, 0x18)
}
    48f8:	1463      	ipop
    48fa:	1461      	nir
    48fc:	20000064 	.long	0x20000064

00004900 <SYSCONIntHandler>:
//SYSCON Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCONIntHandler(void) 
{
    4900:	1460      	nie
    4902:	1462      	ipush
    // ISR content ...
	 if((SYSCON->ISR&ISOSC_ST)==ISOSC_ST)
    4904:	136f      	lrw      	r3, 0x2000005c	// 4ac0 <EXI10to15IntHandler+0x10>
    4906:	3080      	movi      	r0, 128
    4908:	9360      	ld.w      	r3, (r3, 0)
    490a:	60c0      	addu      	r3, r0
    490c:	9323      	ld.w      	r1, (r3, 0xc)
    490e:	3201      	movi      	r2, 1
    4910:	6848      	and      	r1, r2
    4912:	3940      	cmpnei      	r1, 0
    4914:	0c06      	bf      	0x4920	// 4920 <SYSCONIntHandler+0x20>
    {
        SYSCON->ICR = ISOSC_ST;
    4916:	b341      	st.w      	r2, (r3, 0x4)
        SYSCON_ISOSCSTFlag=1;
    4918:	136b      	lrw      	r3, 0x2000006a	// 4ac4 <EXI10to15IntHandler+0x14>
        SYSCON_EM_CMRCVFlag=1;
    }
    else if((SYSCON->ISR&CMD_ERR_ST)==CMD_ERR_ST)
    {
        SYSCON->ICR = CMD_ERR_ST;
        SYSCON_CMD_ERRFlag=1;
    491a:	a340      	st.b      	r2, (r3, 0)
    }
}
    491c:	1463      	ipop
    491e:	1461      	nir
    else if((SYSCON->ISR&IMOSC_ST)==IMOSC_ST)
    4920:	9323      	ld.w      	r1, (r3, 0xc)
    4922:	3202      	movi      	r2, 2
    4924:	6848      	and      	r1, r2
    4926:	3940      	cmpnei      	r1, 0
    4928:	0c05      	bf      	0x4932	// 4932 <SYSCONIntHandler+0x32>
        SYSCON->ICR = IMOSC_ST;
    492a:	b341      	st.w      	r2, (r3, 0x4)
        SYSCON_IMOSCSTFlag=1;
    492c:	1367      	lrw      	r3, 0x20000068	// 4ac8 <EXI10to15IntHandler+0x18>
        SYSCON_CMD_ERRFlag=1;
    492e:	3201      	movi      	r2, 1
    4930:	07f5      	br      	0x491a	// 491a <SYSCONIntHandler+0x1a>
    else if((SYSCON->ISR&EMOSC_ST)==EMOSC_ST)
    4932:	9323      	ld.w      	r1, (r3, 0xc)
    4934:	3208      	movi      	r2, 8
    4936:	6848      	and      	r1, r2
    4938:	3940      	cmpnei      	r1, 0
    493a:	0c04      	bf      	0x4942	// 4942 <SYSCONIntHandler+0x42>
        SYSCON->ICR = EMOSC_ST;
    493c:	b341      	st.w      	r2, (r3, 0x4)
        SYSCON_EMOSCSTFlag=1;
    493e:	1364      	lrw      	r3, 0x20000069	// 4acc <EXI10to15IntHandler+0x1c>
    4940:	07f7      	br      	0x492e	// 492e <SYSCONIntHandler+0x2e>
    else if((SYSCON->ISR&SYSCLK_ST)==SYSCLK_ST)
    4942:	9343      	ld.w      	r2, (r3, 0xc)
    4944:	6880      	and      	r2, r0
    4946:	3a40      	cmpnei      	r2, 0
    4948:	0c05      	bf      	0x4952	// 4952 <SYSCONIntHandler+0x52>
        SYSCON->ICR = SYSCLK_ST;
    494a:	3280      	movi      	r2, 128
    494c:	b341      	st.w      	r2, (r3, 0x4)
        SYSCON_SYSCLKSTFlag=1;
    494e:	1361      	lrw      	r3, 0x2000006b	// 4ad0 <EXI10to15IntHandler+0x20>
    4950:	07ef      	br      	0x492e	// 492e <SYSCONIntHandler+0x2e>
    else if((SYSCON->ISR&IWDT_INT_ST)==IWDT_INT_ST)
    4952:	3280      	movi      	r2, 128
    4954:	9323      	ld.w      	r1, (r3, 0xc)
    4956:	4241      	lsli      	r2, r2, 1
    4958:	6848      	and      	r1, r2
    495a:	3940      	cmpnei      	r1, 0
    495c:	0c04      	bf      	0x4964	// 4964 <SYSCONIntHandler+0x64>
        SYSCON->ICR = IWDT_INT_ST;
    495e:	b341      	st.w      	r2, (r3, 0x4)
        SYSCON_IWDTINTFlag=1;
    4960:	127d      	lrw      	r3, 0x20000070	// 4ad4 <EXI10to15IntHandler+0x24>
    4962:	07e6      	br      	0x492e	// 492e <SYSCONIntHandler+0x2e>
    else if((SYSCON->ISR&LVD_INT_ST)==LVD_INT_ST)
    4964:	3280      	movi      	r2, 128
    4966:	9323      	ld.w      	r1, (r3, 0xc)
    4968:	4244      	lsli      	r2, r2, 4
    496a:	6848      	and      	r1, r2
    496c:	3940      	cmpnei      	r1, 0
    496e:	0c04      	bf      	0x4976	// 4976 <SYSCONIntHandler+0x76>
        SYSCON->ICR = LVD_INT_ST;
    4970:	b341      	st.w      	r2, (r3, 0x4)
        SYSCON_LVDINTFlag=1;
    4972:	127a      	lrw      	r3, 0x2000006f	// 4ad8 <EXI10to15IntHandler+0x28>
    4974:	07dd      	br      	0x492e	// 492e <SYSCONIntHandler+0x2e>
    else if((SYSCON->ISR&EM_CMFAIL_ST)==EM_CMFAIL_ST)
    4976:	3280      	movi      	r2, 128
    4978:	9323      	ld.w      	r1, (r3, 0xc)
    497a:	424b      	lsli      	r2, r2, 11
    497c:	6848      	and      	r1, r2
    497e:	3940      	cmpnei      	r1, 0
    4980:	0c04      	bf      	0x4988	// 4988 <SYSCONIntHandler+0x88>
        SYSCON->ICR = EM_CMFAIL_ST;
    4982:	b341      	st.w      	r2, (r3, 0x4)
        SYSCON_EM_CMFAILFlag=1;
    4984:	1276      	lrw      	r3, 0x2000006e	// 4adc <EXI10to15IntHandler+0x2c>
    4986:	07d4      	br      	0x492e	// 492e <SYSCONIntHandler+0x2e>
    else if((SYSCON->ISR&EM_CMRCV_ST)==EM_CMRCV_ST)
    4988:	3280      	movi      	r2, 128
    498a:	9323      	ld.w      	r1, (r3, 0xc)
    498c:	424c      	lsli      	r2, r2, 12
    498e:	6848      	and      	r1, r2
    4990:	3940      	cmpnei      	r1, 0
    4992:	0c04      	bf      	0x499a	// 499a <SYSCONIntHandler+0x9a>
        SYSCON->ICR = EM_CMRCV_ST;
    4994:	b341      	st.w      	r2, (r3, 0x4)
        SYSCON_EM_CMRCVFlag=1;
    4996:	1273      	lrw      	r3, 0x2000006d	// 4ae0 <EXI10to15IntHandler+0x30>
    4998:	07cb      	br      	0x492e	// 492e <SYSCONIntHandler+0x2e>
    else if((SYSCON->ISR&CMD_ERR_ST)==CMD_ERR_ST)
    499a:	3280      	movi      	r2, 128
    499c:	9323      	ld.w      	r1, (r3, 0xc)
    499e:	4256      	lsli      	r2, r2, 22
    49a0:	6848      	and      	r1, r2
    49a2:	3940      	cmpnei      	r1, 0
    49a4:	0fbc      	bf      	0x491c	// 491c <SYSCONIntHandler+0x1c>
        SYSCON->ICR = CMD_ERR_ST;
    49a6:	b341      	st.w      	r2, (r3, 0x4)
        SYSCON_CMD_ERRFlag=1;
    49a8:	126f      	lrw      	r3, 0x2000006c	// 4ae4 <EXI10to15IntHandler+0x34>
    49aa:	07c2      	br      	0x492e	// 492e <SYSCONIntHandler+0x2e>

000049ac <IFCIntHandler>:
//IFC Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void IFCIntHandler(void)
{
    49ac:	1460      	nie
    49ae:	1462      	ipush
    // ISR content ...
	if((IFC->MISR&End_INT)==End_INT)
    49b0:	126e      	lrw      	r3, 0x20000060	// 4ae8 <EXI10to15IntHandler+0x38>
    49b2:	3101      	movi      	r1, 1
    49b4:	9360      	ld.w      	r3, (r3, 0)
    49b6:	934b      	ld.w      	r2, (r3, 0x2c)
    49b8:	6884      	and      	r2, r1
    49ba:	3a40      	cmpnei      	r2, 0
    49bc:	0c04      	bf      	0x49c4	// 49c4 <IFCIntHandler+0x18>
    {
        IFC->ICLR = End_INT;
    49be:	3201      	movi      	r2, 1
    } else if((IFC->MISR&Add_INT)==Add_INT)
    {
        IFC->ICLR = Add_INT;
    } else if((IFC->MISR&OverWrite_INT)==OverWrite_INT)
    {
        IFC->ICLR = OverWrite_INT;
    49c0:	b34c      	st.w      	r2, (r3, 0x30)
    }
}
    49c2:	0419      	br      	0x49f4	// 49f4 <IFCIntHandler+0x48>
    } else if((IFC->MISR&Port_INT)==Port_INT)
    49c4:	3280      	movi      	r2, 128
    49c6:	932b      	ld.w      	r1, (r3, 0x2c)
    49c8:	4245      	lsli      	r2, r2, 5
    49ca:	6848      	and      	r1, r2
    49cc:	3940      	cmpnei      	r1, 0
    49ce:	0bf9      	bt      	0x49c0	// 49c0 <IFCIntHandler+0x14>
    } else if((IFC->MISR&Undefine_INT)==Undefine_INT)
    49d0:	3280      	movi      	r2, 128
    49d2:	932b      	ld.w      	r1, (r3, 0x2c)
    49d4:	4246      	lsli      	r2, r2, 6
    49d6:	6848      	and      	r1, r2
    49d8:	3940      	cmpnei      	r1, 0
    49da:	0bf3      	bt      	0x49c0	// 49c0 <IFCIntHandler+0x14>
    } else if((IFC->MISR&Add_INT)==Add_INT)
    49dc:	3280      	movi      	r2, 128
    49de:	932b      	ld.w      	r1, (r3, 0x2c)
    49e0:	4247      	lsli      	r2, r2, 7
    49e2:	6848      	and      	r1, r2
    49e4:	3940      	cmpnei      	r1, 0
    49e6:	0bed      	bt      	0x49c0	// 49c0 <IFCIntHandler+0x14>
    } else if((IFC->MISR&OverWrite_INT)==OverWrite_INT)
    49e8:	3280      	movi      	r2, 128
    49ea:	932b      	ld.w      	r1, (r3, 0x2c)
    49ec:	4248      	lsli      	r2, r2, 8
    49ee:	6848      	and      	r1, r2
    49f0:	3940      	cmpnei      	r1, 0
    49f2:	0be7      	bt      	0x49c0	// 49c0 <IFCIntHandler+0x14>
}
    49f4:	1463      	ipop
    49f6:	1461      	nir

000049f8 <EXI0IntHandler>:
//EXI0 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0IntHandler(void) 
{
    49f8:	1460      	nie
    49fa:	1462      	ipush
    // ISR content ...
	if ((SYSCON->EXIRS&EXI_PIN0)==EXI_PIN0) 
    49fc:	1171      	lrw      	r3, 0x2000005c	// 4ac0 <EXI10to15IntHandler+0x10>
    49fe:	3101      	movi      	r1, 1
    4a00:	9360      	ld.w      	r3, (r3, 0)
    4a02:	237f      	addi      	r3, 128
    4a04:	934c      	ld.w      	r2, (r3, 0x30)
    4a06:	6884      	and      	r2, r1
    4a08:	3a40      	cmpnei      	r2, 0
    4a0a:	0c03      	bf      	0x4a10	// 4a10 <EXI0IntHandler+0x18>
    {
        SYSCON->EXICR = EXI_PIN0;
    4a0c:	3201      	movi      	r2, 1
    4a0e:	b34b      	st.w      	r2, (r3, 0x2c)
    }
}
    4a10:	1463      	ipop
    4a12:	1461      	nir

00004a14 <EXI1IntHandler>:
//EXI1 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1IntHandler(void) 
{
    4a14:	1460      	nie
    4a16:	1462      	ipush
    // ISR content ...
	if ((SYSCON->EXIRS&EXI_PIN1)==EXI_PIN1) 
    4a18:	116a      	lrw      	r3, 0x2000005c	// 4ac0 <EXI10to15IntHandler+0x10>
    4a1a:	3102      	movi      	r1, 2
    4a1c:	9360      	ld.w      	r3, (r3, 0)
    4a1e:	237f      	addi      	r3, 128
    4a20:	934c      	ld.w      	r2, (r3, 0x30)
    4a22:	6884      	and      	r2, r1
    4a24:	3a40      	cmpnei      	r2, 0
    4a26:	0c03      	bf      	0x4a2c	// 4a2c <EXI1IntHandler+0x18>
    {
        SYSCON->EXICR = EXI_PIN1;
    4a28:	3202      	movi      	r2, 2
    4a2a:	b34b      	st.w      	r2, (r3, 0x2c)
    }
}
    4a2c:	1463      	ipop
    4a2e:	1461      	nir

00004a30 <EXI2to3IntHandler>:
//EXI2~EXI3 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2to3IntHandler(void) 
{
    4a30:	1460      	nie
    4a32:	1462      	ipush
    // ISR content ...
	if ((SYSCON->EXIRS&EXI_PIN2)==EXI_PIN2) 
    4a34:	1163      	lrw      	r3, 0x2000005c	// 4ac0 <EXI10to15IntHandler+0x10>
    4a36:	3104      	movi      	r1, 4
    4a38:	9360      	ld.w      	r3, (r3, 0)
    4a3a:	237f      	addi      	r3, 128
    4a3c:	934c      	ld.w      	r2, (r3, 0x30)
    4a3e:	6884      	and      	r2, r1
    4a40:	3a40      	cmpnei      	r2, 0
    4a42:	0c05      	bf      	0x4a4c	// 4a4c <EXI2to3IntHandler+0x1c>
    {
        SYSCON->EXICR = EXI_PIN2;
    4a44:	3204      	movi      	r2, 4
    } 
    else if ((SYSCON->EXIRS&EXI_PIN3)==EXI_PIN3) 
    {
        SYSCON->EXICR = EXI_PIN3;
    4a46:	b34b      	st.w      	r2, (r3, 0x2c)
    }
}
    4a48:	1463      	ipop
    4a4a:	1461      	nir
    else if ((SYSCON->EXIRS&EXI_PIN3)==EXI_PIN3) 
    4a4c:	934c      	ld.w      	r2, (r3, 0x30)
    4a4e:	3108      	movi      	r1, 8
    4a50:	6884      	and      	r2, r1
    4a52:	3a40      	cmpnei      	r2, 0
    4a54:	0ffa      	bf      	0x4a48	// 4a48 <EXI2to3IntHandler+0x18>
        SYSCON->EXICR = EXI_PIN3;
    4a56:	3208      	movi      	r2, 8
    4a58:	07f7      	br      	0x4a46	// 4a46 <EXI2to3IntHandler+0x16>

00004a5a <EXI4to9IntHandler>:
//EXI4~EXI9 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4to9IntHandler(void) 
{
    4a5a:	1460      	nie
    4a5c:	1462      	ipush
    // ISR content ...
	if ((SYSCON->EXIRS&EXI_PIN4)==EXI_PIN4) 
    4a5e:	1079      	lrw      	r3, 0x2000005c	// 4ac0 <EXI10to15IntHandler+0x10>
    4a60:	3080      	movi      	r0, 128
    4a62:	9360      	ld.w      	r3, (r3, 0)
    4a64:	60c0      	addu      	r3, r0
    4a66:	932c      	ld.w      	r1, (r3, 0x30)
    4a68:	3210      	movi      	r2, 16
    4a6a:	6848      	and      	r1, r2
    4a6c:	3940      	cmpnei      	r1, 0
    4a6e:	0c03      	bf      	0x4a74	// 4a74 <EXI4to9IntHandler+0x1a>
    {
        SYSCON->EXICR = EXI_PIN8;
    }
	else if ((SYSCON->EXIRS&EXI_PIN9)==EXI_PIN9) 
	{
        SYSCON->EXICR = EXI_PIN9;
    4a70:	b34b      	st.w      	r2, (r3, 0x2c)
	}
}
    4a72:	041d      	br      	0x4aac	// 4aac <EXI4to9IntHandler+0x52>
    else if ((SYSCON->EXIRS&EXI_PIN5)==EXI_PIN5) 
    4a74:	932c      	ld.w      	r1, (r3, 0x30)
    4a76:	3220      	movi      	r2, 32
    4a78:	6848      	and      	r1, r2
    4a7a:	3940      	cmpnei      	r1, 0
    4a7c:	0bfa      	bt      	0x4a70	// 4a70 <EXI4to9IntHandler+0x16>
    else if ((SYSCON->EXIRS&EXI_PIN6)==EXI_PIN6) 
    4a7e:	932c      	ld.w      	r1, (r3, 0x30)
    4a80:	3240      	movi      	r2, 64
    4a82:	6848      	and      	r1, r2
    4a84:	3940      	cmpnei      	r1, 0
    4a86:	0bf5      	bt      	0x4a70	// 4a70 <EXI4to9IntHandler+0x16>
    else if ((SYSCON->EXIRS&EXI_PIN7)==EXI_PIN7) 
    4a88:	934c      	ld.w      	r2, (r3, 0x30)
    4a8a:	6880      	and      	r2, r0
    4a8c:	3a40      	cmpnei      	r2, 0
    4a8e:	0c03      	bf      	0x4a94	// 4a94 <EXI4to9IntHandler+0x3a>
        SYSCON->EXICR = EXI_PIN7;
    4a90:	3280      	movi      	r2, 128
    4a92:	07ef      	br      	0x4a70	// 4a70 <EXI4to9IntHandler+0x16>
    else if ((SYSCON->EXIRS&EXI_PIN8)==EXI_PIN8) 
    4a94:	3280      	movi      	r2, 128
    4a96:	932c      	ld.w      	r1, (r3, 0x30)
    4a98:	4241      	lsli      	r2, r2, 1
    4a9a:	6848      	and      	r1, r2
    4a9c:	3940      	cmpnei      	r1, 0
    4a9e:	0be9      	bt      	0x4a70	// 4a70 <EXI4to9IntHandler+0x16>
	else if ((SYSCON->EXIRS&EXI_PIN9)==EXI_PIN9) 
    4aa0:	3280      	movi      	r2, 128
    4aa2:	932c      	ld.w      	r1, (r3, 0x30)
    4aa4:	4242      	lsli      	r2, r2, 2
    4aa6:	6848      	and      	r1, r2
    4aa8:	3940      	cmpnei      	r1, 0
    4aaa:	0be3      	bt      	0x4a70	// 4a70 <EXI4to9IntHandler+0x16>
}
    4aac:	1463      	ipop
    4aae:	1461      	nir

00004ab0 <EXI10to15IntHandler>:
//EXI10~EXI15 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI10to15IntHandler(void) 
{
    4ab0:	1460      	nie
    4ab2:	1462      	ipush
    if ((SYSCON->EXIRS&EXI_PIN10)==EXI_PIN10) 
    4ab4:	1063      	lrw      	r3, 0x2000005c	// 4ac0 <EXI10to15IntHandler+0x10>
    4ab6:	3280      	movi      	r2, 128
    4ab8:	9360      	ld.w      	r3, (r3, 0)
    4aba:	237f      	addi      	r3, 128
    4abc:	0418      	br      	0x4aec	// 4aec <EXI10to15IntHandler+0x3c>
    4abe:	0000      	bkpt
    4ac0:	2000005c 	.long	0x2000005c
    4ac4:	2000006a 	.long	0x2000006a
    4ac8:	20000068 	.long	0x20000068
    4acc:	20000069 	.long	0x20000069
    4ad0:	2000006b 	.long	0x2000006b
    4ad4:	20000070 	.long	0x20000070
    4ad8:	2000006f 	.long	0x2000006f
    4adc:	2000006e 	.long	0x2000006e
    4ae0:	2000006d 	.long	0x2000006d
    4ae4:	2000006c 	.long	0x2000006c
    4ae8:	20000060 	.long	0x20000060
    4aec:	932c      	ld.w      	r1, (r3, 0x30)
    4aee:	4243      	lsli      	r2, r2, 3
    4af0:	6848      	and      	r1, r2
    4af2:	3940      	cmpnei      	r1, 0
    4af4:	0c03      	bf      	0x4afa	// 4afa <EXI10to15IntHandler+0x4a>
    {
        SYSCON->EXICR = EXI_PIN14;
    }
	else if ((SYSCON->EXIRS&EXI_PIN15)==EXI_PIN15) 
	{
        SYSCON->EXICR = EXI_PIN15;
    4af6:	b34b      	st.w      	r2, (r3, 0x2c)
    }
}
    4af8:	041f      	br      	0x4b36	// 4b36 <EXI10to15IntHandler+0x86>
    else if ((SYSCON->EXIRS&EXI_PIN11)==EXI_PIN11) 
    4afa:	3280      	movi      	r2, 128
    4afc:	932c      	ld.w      	r1, (r3, 0x30)
    4afe:	4244      	lsli      	r2, r2, 4
    4b00:	6848      	and      	r1, r2
    4b02:	3940      	cmpnei      	r1, 0
    4b04:	0bf9      	bt      	0x4af6	// 4af6 <EXI10to15IntHandler+0x46>
    else if ((SYSCON->EXIRS&EXI_PIN12)==EXI_PIN12) 
    4b06:	3280      	movi      	r2, 128
    4b08:	932c      	ld.w      	r1, (r3, 0x30)
    4b0a:	4245      	lsli      	r2, r2, 5
    4b0c:	6848      	and      	r1, r2
    4b0e:	3940      	cmpnei      	r1, 0
    4b10:	0bf3      	bt      	0x4af6	// 4af6 <EXI10to15IntHandler+0x46>
    else if ((SYSCON->EXIRS&EXI_PIN13)==EXI_PIN13) 
    4b12:	3280      	movi      	r2, 128
    4b14:	932c      	ld.w      	r1, (r3, 0x30)
    4b16:	4246      	lsli      	r2, r2, 6
    4b18:	6848      	and      	r1, r2
    4b1a:	3940      	cmpnei      	r1, 0
    4b1c:	0bed      	bt      	0x4af6	// 4af6 <EXI10to15IntHandler+0x46>
	else if ((SYSCON->EXIRS&EXI_PIN14)==EXI_PIN14) 
    4b1e:	3280      	movi      	r2, 128
    4b20:	932c      	ld.w      	r1, (r3, 0x30)
    4b22:	4247      	lsli      	r2, r2, 7
    4b24:	6848      	and      	r1, r2
    4b26:	3940      	cmpnei      	r1, 0
    4b28:	0be7      	bt      	0x4af6	// 4af6 <EXI10to15IntHandler+0x46>
	else if ((SYSCON->EXIRS&EXI_PIN15)==EXI_PIN15) 
    4b2a:	3280      	movi      	r2, 128
    4b2c:	932c      	ld.w      	r1, (r3, 0x30)
    4b2e:	4248      	lsli      	r2, r2, 8
    4b30:	6848      	and      	r1, r2
    4b32:	3940      	cmpnei      	r1, 0
    4b34:	0be1      	bt      	0x4af6	// 4af6 <EXI10to15IntHandler+0x46>
}
    4b36:	1463      	ipop
    4b38:	1461      	nir

00004b3a <USART0IntHandler>:
//USART0 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void USART0IntHandler(void) 
{
    4b3a:	1460      	nie
    4b3c:	1462      	ipush
    // ISR content ...
	unsigned int status;
	status = USART0->MISR & USART0->IMSCR ;
    4b3e:	1371      	lrw      	r3, 0x20000014	// 4d00 <GPT_2IntHandler+0x14>
    4b40:	9320      	ld.w      	r1, (r3, 0)
    4b42:	9167      	ld.w      	r3, (r1, 0x1c)
    4b44:	9145      	ld.w      	r2, (r1, 0x14)
    4b46:	68c8      	and      	r3, r2
	if( status & USART_RXRDY ) 
    4b48:	3201      	movi      	r2, 1
    4b4a:	68c8      	and      	r3, r2
    4b4c:	3b40      	cmpnei      	r3, 0
    4b4e:	0c14      	bf      	0x4b76	// 4b76 <USART0IntHandler+0x3c>
	{
	   r_usrat_cont++;
    4b50:	136d      	lrw      	r3, 0x200002cc	// 4d04 <GPT_2IntHandler+0x18>
    4b52:	8340      	ld.b      	r2, (r3, 0)
    4b54:	2200      	addi      	r2, 1
    4b56:	7488      	zextb      	r2, r2
    4b58:	a340      	st.b      	r2, (r3, 0)
		if(r_usrat_cont>=3)
    4b5a:	8300      	ld.b      	r0, (r3, 0)
    4b5c:	3202      	movi      	r2, 2
    4b5e:	6408      	cmphs      	r2, r0
    4b60:	0803      	bt      	0x4b66	// 4b66 <USART0IntHandler+0x2c>
		{
			r_usrat_cont=0;
    4b62:	3200      	movi      	r2, 0
    4b64:	a340      	st.b      	r2, (r3, 0)
		}
		r_usart_buf[r_usrat_cont]=CSP_USART_GET_RHR(USART0);
    4b66:	8360      	ld.b      	r3, (r3, 0)
    4b68:	1308      	lrw      	r0, 0x2000029f	// 4d08 <GPT_2IntHandler+0x1c>
    4b6a:	60c0      	addu      	r3, r0
    4b6c:	914a      	ld.w      	r2, (r1, 0x28)
    4b6e:	7488      	zextb      	r2, r2
    4b70:	a340      	st.b      	r2, (r3, 0)
		CSP_USART_SET_ICR(USART0, USART_RXRDY);
    4b72:	3301      	movi      	r3, 1
    4b74:	b168      	st.w      	r3, (r1, 0x20)
	}
	if (status & USART_TXRDY) 
	{
		//CSP_USART_SET_ICR(USART0, USART_TXRDY);
	}
}
    4b76:	1463      	ipop
    4b78:	1461      	nir

00004b7a <UART1IntHandler>:
//UART1 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1IntHandler(void) 
{
    4b7a:	1460      	nie
    4b7c:	1462      	ipush
	// ISR content ...
	if (UART1->ISR&UART_RX_INT_S)
    4b7e:	1364      	lrw      	r3, 0x20000010	// 4d0c <GPT_2IntHandler+0x20>
    4b80:	3002      	movi      	r0, 2
    4b82:	9360      	ld.w      	r3, (r3, 0)
    4b84:	9343      	ld.w      	r2, (r3, 0xc)
    4b86:	6880      	and      	r2, r0
    4b88:	3a40      	cmpnei      	r2, 0
    4b8a:	0c13      	bf      	0x4bb0	// 4bb0 <UART1IntHandler+0x36>
	{
		r_urat_cont++;
    4b8c:	1341      	lrw      	r2, 0x2000028c	// 4d10 <GPT_2IntHandler+0x24>
    4b8e:	8220      	ld.b      	r1, (r2, 0)
    4b90:	2100      	addi      	r1, 1
    4b92:	7444      	zextb      	r1, r1
    4b94:	a220      	st.b      	r1, (r2, 0)
		if(r_urat_cont>=3)
    4b96:	8220      	ld.b      	r1, (r2, 0)
    4b98:	6440      	cmphs      	r0, r1
    4b9a:	0803      	bt      	0x4ba0	// 4ba0 <UART1IntHandler+0x26>
		{
			r_urat_cont=0;
    4b9c:	3100      	movi      	r1, 0
    4b9e:	a220      	st.b      	r1, (r2, 0)
		}
		r_uart_buf[r_urat_cont]=CSP_UART_GET_DATA(UART1);
    4ba0:	8240      	ld.b      	r2, (r2, 0)
    4ba2:	121d      	lrw      	r0, 0x2000029c	// 4d14 <GPT_2IntHandler+0x28>
    4ba4:	6080      	addu      	r2, r0
    4ba6:	9320      	ld.w      	r1, (r3, 0)
    4ba8:	7444      	zextb      	r1, r1
    4baa:	a220      	st.b      	r1, (r2, 0)
		UART1->ISR=UART_RX_INT_S;
    4bac:	3202      	movi      	r2, 2
    4bae:	b343      	st.w      	r2, (r3, 0xc)
	}
	if( UART1->ISR&UART_TX_INT_S) 
    4bb0:	9343      	ld.w      	r2, (r3, 0xc)
    {
		//UART1->ISR=UART_TX_INT_S;
	}
	if ((UART1->ISR&UART_RX_IOV_S)==UART_RX_IOV_S)
    4bb2:	3108      	movi      	r1, 8
    4bb4:	9343      	ld.w      	r2, (r3, 0xc)
    4bb6:	6884      	and      	r2, r1
    4bb8:	3a40      	cmpnei      	r2, 0
    4bba:	0c03      	bf      	0x4bc0	// 4bc0 <UART1IntHandler+0x46>
	{
		UART1->ISR=UART_RX_IOV_S;
    4bbc:	3208      	movi      	r2, 8
    4bbe:	b343      	st.w      	r2, (r3, 0xc)
	}
	if ((UART1->ISR&UART_TX_IOV_S)==UART_TX_IOV_S)
    4bc0:	9343      	ld.w      	r2, (r3, 0xc)
    4bc2:	3104      	movi      	r1, 4
    4bc4:	6884      	and      	r2, r1
    4bc6:	3a40      	cmpnei      	r2, 0
    4bc8:	0c03      	bf      	0x4bce	// 4bce <UART1IntHandler+0x54>
	{
		UART1->ISR=UART_TX_IOV_S;
    4bca:	3204      	movi      	r2, 4
    4bcc:	b343      	st.w      	r2, (r3, 0xc)
	}
	if ((UART1->ISR&UART_PAR_ERR_S)==UART_PAR_ERR_S)
    4bce:	9343      	ld.w      	r2, (r3, 0xc)
    4bd0:	3110      	movi      	r1, 16
    4bd2:	6884      	and      	r2, r1
    4bd4:	3a40      	cmpnei      	r2, 0
    4bd6:	0c03      	bf      	0x4bdc	// 4bdc <UART1IntHandler+0x62>
	{
		UART1->ISR=UART_PAR_ERR_S;
    4bd8:	3210      	movi      	r2, 16
    4bda:	b343      	st.w      	r2, (r3, 0xc)
	}
}
    4bdc:	1463      	ipop
    4bde:	1461      	nir

00004be0 <I2CIntHandler>:
//I2C Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2CIntHandler(void) 
{
    4be0:	1460      	nie
    4be2:	1462      	ipush
    4be4:	14d0      	push      	r15
		}
    }*/
    //I2C slave
    //else if (I2CMode==0)
   // {
		I2C_Slave_Receive();
    4be6:	e3fff4ff 	bsr      	0x35e4	// 35e4 <I2C_Slave_Receive>
   // }
}
    4bea:	d9ee2000 	ld.w      	r15, (sp, 0)
    4bee:	1401      	addi      	sp, sp, 4
    4bf0:	1463      	ipop
    4bf2:	1461      	nir

00004bf4 <GPT_0IntHandler>:
//GPT_0 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT_0IntHandler(void) 
{
    4bf4:	1460      	nie
    4bf6:	1462      	ipush
    // ISR content ...
	if((GPTCH0->SR&GPTCHX_INT_COVFS)==GPTCHX_INT_COVFS)
    4bf8:	1268      	lrw      	r3, 0x20000034	// 4d18 <GPT_2IntHandler+0x2c>
    4bfa:	3101      	movi      	r1, 1
    4bfc:	9360      	ld.w      	r3, (r3, 0)
    4bfe:	935c      	ld.w      	r2, (r3, 0x70)
    4c00:	6884      	and      	r2, r1
    4c02:	3a40      	cmpnei      	r2, 0
    4c04:	0c03      	bf      	0x4c0a	// 4c0a <GPT_0IntHandler+0x16>
	{
		GPTCH0->CSR = GPTCHX_INT_COVFS;
    4c06:	3201      	movi      	r2, 1
    4c08:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH0->SR&GPTCHX_INT_LOVRS)==GPTCHX_INT_LOVRS)
    4c0a:	935c      	ld.w      	r2, (r3, 0x70)
    4c0c:	3102      	movi      	r1, 2
    4c0e:	6884      	and      	r2, r1
    4c10:	3a40      	cmpnei      	r2, 0
    4c12:	0c03      	bf      	0x4c18	// 4c18 <GPT_0IntHandler+0x24>
	{
		GPTCH0->CSR = GPTCHX_INT_LOVRS;
    4c14:	3202      	movi      	r2, 2
    4c16:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH0->SR&GPTCHX_INT_CPAS)==GPTCHX_INT_CPAS)
    4c18:	935c      	ld.w      	r2, (r3, 0x70)
    4c1a:	3104      	movi      	r1, 4
    4c1c:	6884      	and      	r2, r1
    4c1e:	3a40      	cmpnei      	r2, 0
    4c20:	0c03      	bf      	0x4c26	// 4c26 <GPT_0IntHandler+0x32>
	{
		GPTCH0->CSR = GPTCHX_INT_CPAS;
    4c22:	3204      	movi      	r2, 4
    4c24:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH0->SR&GPTCHX_INT_CPBS)==GPTCHX_INT_CPBS)
    4c26:	935c      	ld.w      	r2, (r3, 0x70)
    4c28:	3108      	movi      	r1, 8
    4c2a:	6884      	and      	r2, r1
    4c2c:	3a40      	cmpnei      	r2, 0
    4c2e:	0c03      	bf      	0x4c34	// 4c34 <GPT_0IntHandler+0x40>
	{
		GPTCH0->CSR = GPTCHX_INT_CPBS;
    4c30:	3208      	movi      	r2, 8
    4c32:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH0->SR&GPTCHX_INT_CPCS)==GPTCHX_INT_CPCS)
    4c34:	935c      	ld.w      	r2, (r3, 0x70)
    4c36:	3110      	movi      	r1, 16
    4c38:	6884      	and      	r2, r1
    4c3a:	3a40      	cmpnei      	r2, 0
    4c3c:	0c03      	bf      	0x4c42	// 4c42 <GPT_0IntHandler+0x4e>
	{
		GPTCH0->CSR = GPTCHX_INT_CPCS;
    4c3e:	3210      	movi      	r2, 16
    4c40:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH0->SR&GPTCHX_INT_LDRAS)==GPTCHX_INT_LDRAS)
    4c42:	935c      	ld.w      	r2, (r3, 0x70)
    4c44:	3120      	movi      	r1, 32
    4c46:	6884      	and      	r2, r1
    4c48:	3a40      	cmpnei      	r2, 0
    4c4a:	0c03      	bf      	0x4c50	// 4c50 <GPT_0IntHandler+0x5c>
	{
		GPTCH0->CSR = GPTCHX_INT_LDRAS;
    4c4c:	3220      	movi      	r2, 32
    4c4e:	b35b      	st.w      	r2, (r3, 0x6c)
		//RA_Capture=GPTCH0->RA;
	}
	if((GPTCH0->SR&GPTCHX_INT_LDRBS)==GPTCHX_INT_LDRBS)
    4c50:	935c      	ld.w      	r2, (r3, 0x70)
    4c52:	3140      	movi      	r1, 64
    4c54:	6884      	and      	r2, r1
    4c56:	3a40      	cmpnei      	r2, 0
    4c58:	0c03      	bf      	0x4c5e	// 4c5e <GPT_0IntHandler+0x6a>
	{
		GPTCH0->CSR = GPTCHX_INT_LDRBS;
    4c5a:	3240      	movi      	r2, 64
    4c5c:	b35b      	st.w      	r2, (r3, 0x6c)
		//RB_Capture=GPTCH0->RB;
	}
	if((GPTCH0->SR&GPTCHX_INT_ETRGS)==GPTCHX_INT_ETRGS)
    4c5e:	935c      	ld.w      	r2, (r3, 0x70)
    4c60:	3180      	movi      	r1, 128
    4c62:	6884      	and      	r2, r1
    4c64:	3a40      	cmpnei      	r2, 0
    4c66:	0c03      	bf      	0x4c6c	// 4c6c <GPT_0IntHandler+0x78>
	{
		GPTCH0->CSR = GPTCHX_INT_ETRGS;
    4c68:	3280      	movi      	r2, 128
    4c6a:	b35b      	st.w      	r2, (r3, 0x6c)
	}
}
    4c6c:	1463      	ipop
    4c6e:	1461      	nir

00004c70 <GPT_1IntHandler>:
//GPT_1 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT_1IntHandler(void) 
{
    4c70:	1460      	nie
    4c72:	1462      	ipush
	// ISR content ...
	if((GPTCH1->SR&GPTCHX_INT_COVFS)==GPTCHX_INT_COVFS)
    4c74:	116a      	lrw      	r3, 0x20000030	// 4d1c <GPT_2IntHandler+0x30>
    4c76:	3101      	movi      	r1, 1
    4c78:	9360      	ld.w      	r3, (r3, 0)
    4c7a:	935c      	ld.w      	r2, (r3, 0x70)
    4c7c:	6884      	and      	r2, r1
    4c7e:	3a40      	cmpnei      	r2, 0
    4c80:	0c03      	bf      	0x4c86	// 4c86 <GPT_1IntHandler+0x16>
	{
		GPTCH1->CSR = GPTCHX_INT_COVFS;
    4c82:	3201      	movi      	r2, 1
    4c84:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH1->SR&GPTCHX_INT_LOVRS)==GPTCHX_INT_LOVRS)
    4c86:	935c      	ld.w      	r2, (r3, 0x70)
    4c88:	3102      	movi      	r1, 2
    4c8a:	6884      	and      	r2, r1
    4c8c:	3a40      	cmpnei      	r2, 0
    4c8e:	0c03      	bf      	0x4c94	// 4c94 <GPT_1IntHandler+0x24>
	{
		GPTCH1->CSR = GPTCHX_INT_LOVRS;
    4c90:	3202      	movi      	r2, 2
    4c92:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH1->SR&GPTCHX_INT_CPAS)==GPTCHX_INT_CPAS)
    4c94:	935c      	ld.w      	r2, (r3, 0x70)
    4c96:	3104      	movi      	r1, 4
    4c98:	6884      	and      	r2, r1
    4c9a:	3a40      	cmpnei      	r2, 0
    4c9c:	0c03      	bf      	0x4ca2	// 4ca2 <GPT_1IntHandler+0x32>
	{
		GPTCH1->CSR = GPTCHX_INT_CPAS;
    4c9e:	3204      	movi      	r2, 4
    4ca0:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH1->SR&GPTCHX_INT_CPBS)==GPTCHX_INT_CPBS)
    4ca2:	935c      	ld.w      	r2, (r3, 0x70)
    4ca4:	3108      	movi      	r1, 8
    4ca6:	6884      	and      	r2, r1
    4ca8:	3a40      	cmpnei      	r2, 0
    4caa:	0c03      	bf      	0x4cb0	// 4cb0 <GPT_1IntHandler+0x40>
	{
		GPTCH1->CSR = GPTCHX_INT_CPBS;
    4cac:	3208      	movi      	r2, 8
    4cae:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH1->SR&GPTCHX_INT_CPCS)==GPTCHX_INT_CPCS)
    4cb0:	935c      	ld.w      	r2, (r3, 0x70)
    4cb2:	3110      	movi      	r1, 16
    4cb4:	6884      	and      	r2, r1
    4cb6:	3a40      	cmpnei      	r2, 0
    4cb8:	0c03      	bf      	0x4cbe	// 4cbe <GPT_1IntHandler+0x4e>
	{
		GPTCH1->CSR = GPTCHX_INT_CPCS;
    4cba:	3210      	movi      	r2, 16
    4cbc:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH1->SR&GPTCHX_INT_LDRAS)==GPTCHX_INT_LDRAS)
    4cbe:	935c      	ld.w      	r2, (r3, 0x70)
    4cc0:	3120      	movi      	r1, 32
    4cc2:	6884      	and      	r2, r1
    4cc4:	3a40      	cmpnei      	r2, 0
    4cc6:	0c03      	bf      	0x4ccc	// 4ccc <GPT_1IntHandler+0x5c>
	{
		GPTCH1->CSR = GPTCHX_INT_LDRAS;
    4cc8:	3220      	movi      	r2, 32
    4cca:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH1->SR&GPTCHX_INT_LDRBS)==GPTCHX_INT_LDRBS)
    4ccc:	935c      	ld.w      	r2, (r3, 0x70)
    4cce:	3140      	movi      	r1, 64
    4cd0:	6884      	and      	r2, r1
    4cd2:	3a40      	cmpnei      	r2, 0
    4cd4:	0c03      	bf      	0x4cda	// 4cda <GPT_1IntHandler+0x6a>
	{
		GPTCH1->CSR = GPTCHX_INT_LDRBS;
    4cd6:	3240      	movi      	r2, 64
    4cd8:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH1->SR&GPTCHX_INT_ETRGS)==GPTCHX_INT_ETRGS)
    4cda:	935c      	ld.w      	r2, (r3, 0x70)
    4cdc:	3180      	movi      	r1, 128
    4cde:	6884      	and      	r2, r1
    4ce0:	3a40      	cmpnei      	r2, 0
    4ce2:	0c03      	bf      	0x4ce8	// 4ce8 <GPT_1IntHandler+0x78>
	{
		GPTCH1->CSR = GPTCHX_INT_ETRGS;
    4ce4:	3280      	movi      	r2, 128
    4ce6:	b35b      	st.w      	r2, (r3, 0x6c)
	}
}
    4ce8:	1463      	ipop
    4cea:	1461      	nir

00004cec <GPT_2IntHandler>:
//GPT_2 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT_2IntHandler(void) 
{
    4cec:	1460      	nie
    4cee:	1462      	ipush
    // ISR content ...
	if((GPTCH2->SR&GPTCHX_INT_COVFS)==GPTCHX_INT_COVFS)
    4cf0:	106c      	lrw      	r3, 0x2000002c	// 4d20 <GPT_2IntHandler+0x34>
    4cf2:	3101      	movi      	r1, 1
    4cf4:	9360      	ld.w      	r3, (r3, 0)
    4cf6:	935c      	ld.w      	r2, (r3, 0x70)
    4cf8:	6884      	and      	r2, r1
    4cfa:	3a40      	cmpnei      	r2, 0
    4cfc:	0c16      	bf      	0x4d28	// 4d28 <GPT_2IntHandler+0x3c>
    4cfe:	0413      	br      	0x4d24	// 4d24 <GPT_2IntHandler+0x38>
    4d00:	20000014 	.long	0x20000014
    4d04:	200002cc 	.long	0x200002cc
    4d08:	2000029f 	.long	0x2000029f
    4d0c:	20000010 	.long	0x20000010
    4d10:	2000028c 	.long	0x2000028c
    4d14:	2000029c 	.long	0x2000029c
    4d18:	20000034 	.long	0x20000034
    4d1c:	20000030 	.long	0x20000030
    4d20:	2000002c 	.long	0x2000002c
	{
		GPTCH2->CSR = GPTCHX_INT_COVFS;
    4d24:	3201      	movi      	r2, 1
    4d26:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH2->SR&GPTCHX_INT_LOVRS)==GPTCHX_INT_LOVRS)
    4d28:	935c      	ld.w      	r2, (r3, 0x70)
    4d2a:	3102      	movi      	r1, 2
    4d2c:	6884      	and      	r2, r1
    4d2e:	3a40      	cmpnei      	r2, 0
    4d30:	0c03      	bf      	0x4d36	// 4d36 <GPT_2IntHandler+0x4a>
	{
		GPTCH2->CSR = GPTCHX_INT_LOVRS;
    4d32:	3202      	movi      	r2, 2
    4d34:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH2->SR&GPTCHX_INT_CPAS)==GPTCHX_INT_CPAS)
    4d36:	935c      	ld.w      	r2, (r3, 0x70)
    4d38:	3104      	movi      	r1, 4
    4d3a:	6884      	and      	r2, r1
    4d3c:	3a40      	cmpnei      	r2, 0
    4d3e:	0c03      	bf      	0x4d44	// 4d44 <GPT_2IntHandler+0x58>
	{
		GPTCH2->CSR = GPTCHX_INT_CPAS;
    4d40:	3204      	movi      	r2, 4
    4d42:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH2->SR&GPTCHX_INT_CPBS)==GPTCHX_INT_CPBS)
    4d44:	935c      	ld.w      	r2, (r3, 0x70)
    4d46:	3108      	movi      	r1, 8
    4d48:	6884      	and      	r2, r1
    4d4a:	3a40      	cmpnei      	r2, 0
    4d4c:	0c03      	bf      	0x4d52	// 4d52 <GPT_2IntHandler+0x66>
	{
		GPTCH2->CSR = GPTCHX_INT_CPBS;
    4d4e:	3208      	movi      	r2, 8
    4d50:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH2->SR&GPTCHX_INT_CPCS)==GPTCHX_INT_CPCS)
    4d52:	935c      	ld.w      	r2, (r3, 0x70)
    4d54:	3110      	movi      	r1, 16
    4d56:	6884      	and      	r2, r1
    4d58:	3a40      	cmpnei      	r2, 0
    4d5a:	0c03      	bf      	0x4d60	// 4d60 <GPT_2IntHandler+0x74>
	{
		GPTCH2->CSR = GPTCHX_INT_CPCS;
    4d5c:	3210      	movi      	r2, 16
    4d5e:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH2->SR&GPTCHX_INT_LDRAS)==GPTCHX_INT_LDRAS)
    4d60:	935c      	ld.w      	r2, (r3, 0x70)
    4d62:	3120      	movi      	r1, 32
    4d64:	6884      	and      	r2, r1
    4d66:	3a40      	cmpnei      	r2, 0
    4d68:	0c03      	bf      	0x4d6e	// 4d6e <GPT_2IntHandler+0x82>
	{
		GPTCH2->CSR = GPTCHX_INT_LDRAS;
    4d6a:	3220      	movi      	r2, 32
    4d6c:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH2->SR&GPTCHX_INT_LDRBS)==GPTCHX_INT_LDRBS)
    4d6e:	935c      	ld.w      	r2, (r3, 0x70)
    4d70:	3140      	movi      	r1, 64
    4d72:	6884      	and      	r2, r1
    4d74:	3a40      	cmpnei      	r2, 0
    4d76:	0c03      	bf      	0x4d7c	// 4d7c <GPT_2IntHandler+0x90>
	{
		GPTCH2->CSR = GPTCHX_INT_LDRBS;
    4d78:	3240      	movi      	r2, 64
    4d7a:	b35b      	st.w      	r2, (r3, 0x6c)
	}
	if((GPTCH2->SR&GPTCHX_INT_ETRGS)==GPTCHX_INT_ETRGS)
    4d7c:	935c      	ld.w      	r2, (r3, 0x70)
    4d7e:	3180      	movi      	r1, 128
    4d80:	6884      	and      	r2, r1
    4d82:	3a40      	cmpnei      	r2, 0
    4d84:	0c03      	bf      	0x4d8a	// 4d8a <GPT_2IntHandler+0x9e>
	{
		GPTCH2->CSR = GPTCHX_INT_ETRGS;
    4d86:	3280      	movi      	r2, 128
    4d88:	b35b      	st.w      	r2, (r3, 0x6c)
	}
}
    4d8a:	1463      	ipop
    4d8c:	1461      	nir

00004d8e <GTCIntHandler>:
//GTC Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTCIntHandler(void) 
{
    4d8e:	1460      	nie
    4d90:	1462      	ipush
    4d92:	14d0      	push      	r15
    // ISR content ...
	GPIO_Reverse(GPIOA1,0);
    4d94:	1370      	lrw      	r3, 0x2000004c	// 4f54 <SPIIntHandler+0x12>
    4d96:	3100      	movi      	r1, 0
    4d98:	9300      	ld.w      	r0, (r3, 0)
    4d9a:	e3fff1e4 	bsr      	0x3162	// 3162 <GPIO_Reverse>
	if((GTC->MISR&GTC_PENDI)==GTC_PENDI)
    4d9e:	136f      	lrw      	r3, 0x20000028	// 4f58 <SPIIntHandler+0x16>
    4da0:	3108      	movi      	r1, 8
    4da2:	9360      	ld.w      	r3, (r3, 0)
    4da4:	9349      	ld.w      	r2, (r3, 0x24)
    4da6:	6884      	and      	r2, r1
    4da8:	3a40      	cmpnei      	r2, 0
    4daa:	0c03      	bf      	0x4db0	// 4db0 <GTCIntHandler+0x22>
	{
		GTC->ICR = GTC_PENDI;
    4dac:	3208      	movi      	r2, 8
    4dae:	b34a      	st.w      	r2, (r3, 0x28)
	} 
	if((GTC->MISR&GTC_STOPI)==GTC_STOPI)
    4db0:	9349      	ld.w      	r2, (r3, 0x24)
    4db2:	3102      	movi      	r1, 2
    4db4:	6884      	and      	r2, r1
    4db6:	3a40      	cmpnei      	r2, 0
    4db8:	0c03      	bf      	0x4dbe	// 4dbe <GTCIntHandler+0x30>
	{
		GTC->ICR = GTC_STOPI;
    4dba:	3202      	movi      	r2, 2
    4dbc:	b34a      	st.w      	r2, (r3, 0x28)
	} 
	if((GTC->MISR&GTC_OVFI)==GTC_OVFI)
    4dbe:	9349      	ld.w      	r2, (r3, 0x24)
    4dc0:	3120      	movi      	r1, 32
    4dc2:	6884      	and      	r2, r1
    4dc4:	3a40      	cmpnei      	r2, 0
    4dc6:	0c03      	bf      	0x4dcc	// 4dcc <GTCIntHandler+0x3e>
	{
		GTC->ICR = GTC_OVFI;
    4dc8:	3220      	movi      	r2, 32
    4dca:	b34a      	st.w      	r2, (r3, 0x28)
	} 
	if((GTC->MISR&GTC_STARTI)==GTC_STARTI)
    4dcc:	9349      	ld.w      	r2, (r3, 0x24)
    4dce:	3101      	movi      	r1, 1
    4dd0:	6884      	and      	r2, r1
    4dd2:	3a40      	cmpnei      	r2, 0
    4dd4:	0c03      	bf      	0x4dda	// 4dda <GTCIntHandler+0x4c>
	{
		GTC->ICR = GTC_STARTI;
    4dd6:	3201      	movi      	r2, 1
    4dd8:	b34a      	st.w      	r2, (r3, 0x28)
	}
	if((GTC->MISR&GTC_PSTARTI)==GTC_PSTARTI)
    4dda:	9349      	ld.w      	r2, (r3, 0x24)
    4ddc:	3104      	movi      	r1, 4
    4dde:	6884      	and      	r2, r1
    4de0:	3a40      	cmpnei      	r2, 0
    4de2:	0c03      	bf      	0x4de8	// 4de8 <GTCIntHandler+0x5a>
	{
		GTC->ICR = GTC_PSTARTI;
    4de4:	3204      	movi      	r2, 4
    4de6:	b34a      	st.w      	r2, (r3, 0x28)
	}
	if((GTC->MISR&GTC_MATI)==GTC_MATI)
    4de8:	9349      	ld.w      	r2, (r3, 0x24)
    4dea:	3110      	movi      	r1, 16
    4dec:	6884      	and      	r2, r1
    4dee:	3a40      	cmpnei      	r2, 0
    4df0:	0c03      	bf      	0x4df6	// 4df6 <GTCIntHandler+0x68>
	{
		GTC->ICR = GTC_MATI;
    4df2:	3210      	movi      	r2, 16
    4df4:	b34a      	st.w      	r2, (r3, 0x28)
	}
	if((GTC->MISR&GTC_CAPTI)==GTC_CAPTI)
    4df6:	9349      	ld.w      	r2, (r3, 0x24)
    4df8:	3140      	movi      	r1, 64
    4dfa:	6884      	and      	r2, r1
    4dfc:	3a40      	cmpnei      	r2, 0
    4dfe:	0c03      	bf      	0x4e04	// 4e04 <GTCIntHandler+0x76>
	{
		GTC->ICR = GTC_CAPTI;
    4e00:	3240      	movi      	r2, 64
    4e02:	b34a      	st.w      	r2, (r3, 0x28)
		else
		{
			R_Capture_buf3=R_Capture_buf2-R_Capture_buf1;
		}*/
	}
}
    4e04:	d9ee2000 	ld.w      	r15, (sp, 0)
    4e08:	1401      	addi      	sp, sp, 4
    4e0a:	1463      	ipop
    4e0c:	1461      	nir

00004e0e <STC16IntHandler>:
//STC16 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void STC16IntHandler(void) 
{
    4e0e:	1460      	nie
    4e10:	1462      	ipush
    4e12:	14c2      	push      	r4-r5
    // ISR content ...
	
	
	if((ST16->MISR&ST16_STARTI)==ST16_STARTI)
    4e14:	1272      	lrw      	r3, 0x20000024	// 4f5c <SPIIntHandler+0x1a>
    4e16:	3501      	movi      	r5, 1
    4e18:	9360      	ld.w      	r3, (r3, 0)
    4e1a:	9345      	ld.w      	r2, (r3, 0x14)
    4e1c:	6894      	and      	r2, r5
    4e1e:	3a40      	cmpnei      	r2, 0
    4e20:	0c08      	bf      	0x4e30	// 4e30 <STC16IntHandler+0x22>
	{
		ST16->ICR = ST16_STARTI;
    4e22:	3201      	movi      	r2, 1
	}
	else if((ST16->MISR&ST16_STOPI)==ST16_STOPI)
	{
		ST16->ICR = ST16_STOPI;
    4e24:	b346      	st.w      	r2, (r3, 0x18)
	}
	else if((ST16->CMISR&ST16_CC1FI)==ST16_CC1FI)
	{
		ST16->CICR = ST16_CC1FI;
	}
}
    4e26:	98a1      	ld.w      	r5, (sp, 0x4)
    4e28:	9880      	ld.w      	r4, (sp, 0)
    4e2a:	1402      	addi      	sp, sp, 8
    4e2c:	1463      	ipop
    4e2e:	1461      	nir
	else if((ST16->MISR&ST16_STOPI)==ST16_STOPI)
    4e30:	9345      	ld.w      	r2, (r3, 0x14)
    4e32:	3402      	movi      	r4, 2
    4e34:	6890      	and      	r2, r4
    4e36:	3a40      	cmpnei      	r2, 0
    4e38:	0c03      	bf      	0x4e3e	// 4e3e <STC16IntHandler+0x30>
		ST16->ICR = ST16_STOPI;
    4e3a:	3202      	movi      	r2, 2
    4e3c:	07f4      	br      	0x4e24	// 4e24 <STC16IntHandler+0x16>
	else if((ST16->MISR&ST16_PENDI)==ST16_PENDI)
    4e3e:	9305      	ld.w      	r0, (r3, 0x14)
    4e40:	3204      	movi      	r2, 4
    4e42:	6808      	and      	r0, r2
    4e44:	3840      	cmpnei      	r0, 0
    4e46:	0bef      	bt      	0x4e24	// 4e24 <STC16IntHandler+0x16>
	else if((ST16->CMISR&ST16_CC0RI)==ST16_CC0RI)
    4e48:	237f      	addi      	r3, 128
    4e4a:	9324      	ld.w      	r1, (r3, 0x10)
    4e4c:	6854      	and      	r1, r5
    4e4e:	3940      	cmpnei      	r1, 0
    4e50:	0c04      	bf      	0x4e58	// 4e58 <STC16IntHandler+0x4a>
		ST16->CICR = ST16_CC0RI;
    4e52:	3201      	movi      	r2, 1
		ST16->CICR = ST16_CC1FI;
    4e54:	b345      	st.w      	r2, (r3, 0x14)
}
    4e56:	07e8      	br      	0x4e26	// 4e26 <STC16IntHandler+0x18>
	else if((ST16->CMISR&ST16_CC1RI)==ST16_CC1RI)
    4e58:	9344      	ld.w      	r2, (r3, 0x10)
    4e5a:	6890      	and      	r2, r4
    4e5c:	3a40      	cmpnei      	r2, 0
    4e5e:	0c03      	bf      	0x4e64	// 4e64 <STC16IntHandler+0x56>
		ST16->CICR = ST16_CC1RI;
    4e60:	3202      	movi      	r2, 2
    4e62:	07f9      	br      	0x4e54	// 4e54 <STC16IntHandler+0x46>
	else if((ST16->CMISR&ST16_CC0FI)==ST16_CC0FI)
    4e64:	3280      	movi      	r2, 128
    4e66:	9324      	ld.w      	r1, (r3, 0x10)
    4e68:	4241      	lsli      	r2, r2, 1
    4e6a:	6848      	and      	r1, r2
    4e6c:	3940      	cmpnei      	r1, 0
    4e6e:	0bf3      	bt      	0x4e54	// 4e54 <STC16IntHandler+0x46>
	else if((ST16->CMISR&ST16_CC1FI)==ST16_CC1FI)
    4e70:	3280      	movi      	r2, 128
    4e72:	9324      	ld.w      	r1, (r3, 0x10)
    4e74:	4242      	lsli      	r2, r2, 2
    4e76:	6848      	and      	r1, r2
    4e78:	3940      	cmpnei      	r1, 0
    4e7a:	0bed      	bt      	0x4e54	// 4e54 <STC16IntHandler+0x46>
    4e7c:	07d5      	br      	0x4e26	// 4e26 <STC16IntHandler+0x18>

00004e7e <CTCIntHandler>:
//CTC Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CTCIntHandler(void) 
{
    4e7e:	1460      	nie
    4e80:	1462      	ipush
    // ISR content ...
	if((CTC->MISR&CTC_INT_PEND)==CTC_INT_PEND)
    4e82:	1178      	lrw      	r3, 0x20000020	// 4f60 <SPIIntHandler+0x1e>
    4e84:	3101      	movi      	r1, 1
    4e86:	9360      	ld.w      	r3, (r3, 0)
    4e88:	9349      	ld.w      	r2, (r3, 0x24)
    4e8a:	6884      	and      	r2, r1
    4e8c:	3a40      	cmpnei      	r2, 0
    4e8e:	0c07      	bf      	0x4e9c	// 4e9c <CTCIntHandler+0x1e>
	{
		CTC->ICR = CTC_INT_PEND;
    4e90:	3201      	movi      	r2, 1
    4e92:	b34a      	st.w      	r2, (r3, 0x28)
		CTC->TIMDR=0;
    4e94:	3200      	movi      	r2, 0
    4e96:	b346      	st.w      	r2, (r3, 0x18)
	}
	else if((CTC->MISR&CTC_INT_OVF)==CTC_INT_OVF)
	{
		CTC->ICR = CTC_INT_OVF;
	}
}
    4e98:	1463      	ipop
    4e9a:	1461      	nir
	else if((CTC->MISR&CTC_INT_OVF)==CTC_INT_OVF)
    4e9c:	9349      	ld.w      	r2, (r3, 0x24)
    4e9e:	3102      	movi      	r1, 2
    4ea0:	6884      	and      	r2, r1
    4ea2:	3a40      	cmpnei      	r2, 0
    4ea4:	0ffa      	bf      	0x4e98	// 4e98 <CTCIntHandler+0x1a>
		CTC->ICR = CTC_INT_OVF;
    4ea6:	3202      	movi      	r2, 2
    4ea8:	b34a      	st.w      	r2, (r3, 0x28)
}
    4eaa:	07f7      	br      	0x4e98	// 4e98 <CTCIntHandler+0x1a>

00004eac <ADCIntHandler>:
//ADC Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void ADCIntHandler(void) 
{
    4eac:	1460      	nie
    4eae:	1462      	ipush
    // ISR content ...
	if((ADC0->SR&ADC12_EOC)==ADC12_EOC)
    4eb0:	116d      	lrw      	r3, 0x20000054	// 4f64 <SPIIntHandler+0x22>
    4eb2:	3101      	movi      	r1, 1
    4eb4:	9360      	ld.w      	r3, (r3, 0)
    4eb6:	9348      	ld.w      	r2, (r3, 0x20)
    4eb8:	6884      	and      	r2, r1
    4eba:	3a40      	cmpnei      	r2, 0
    4ebc:	0c05      	bf      	0x4ec6	// 4ec6 <ADCIntHandler+0x1a>
	{
		ADC0->CSR = ADC12_EOC;
    4ebe:	3201      	movi      	r2, 1
	{
		ADC0->CSR = ADC12_CMP1H;
	}
	else if((ADC0->SR&ADC12_CMP1L)==ADC12_CMP1L)
	{
		ADC0->CSR = ADC12_CMP1L;
    4ec0:	b347      	st.w      	r2, (r3, 0x1c)
	}
}
    4ec2:	1463      	ipop
    4ec4:	1461      	nir
	else if((ADC0->SR&ADC12_READY)==ADC12_READY)
    4ec6:	9348      	ld.w      	r2, (r3, 0x20)
    4ec8:	3102      	movi      	r1, 2
    4eca:	6884      	and      	r2, r1
    4ecc:	3a40      	cmpnei      	r2, 0
    4ece:	0c03      	bf      	0x4ed4	// 4ed4 <ADCIntHandler+0x28>
		ADC0->CSR = ADC12_READY;
    4ed0:	3202      	movi      	r2, 2
    4ed2:	07f7      	br      	0x4ec0	// 4ec0 <ADCIntHandler+0x14>
	else if((ADC0->SR&ADC12_OVR)==ADC12_OVR)
    4ed4:	9348      	ld.w      	r2, (r3, 0x20)
    4ed6:	3104      	movi      	r1, 4
    4ed8:	6884      	and      	r2, r1
    4eda:	3a40      	cmpnei      	r2, 0
    4edc:	0c03      	bf      	0x4ee2	// 4ee2 <ADCIntHandler+0x36>
		ADC0->CSR = ADC12_OVR;
    4ede:	3204      	movi      	r2, 4
    4ee0:	07f0      	br      	0x4ec0	// 4ec0 <ADCIntHandler+0x14>
	else if((ADC0->SR&ADC12_CMP0H)==ADC12_CMP0H)
    4ee2:	9348      	ld.w      	r2, (r3, 0x20)
    4ee4:	3110      	movi      	r1, 16
    4ee6:	6884      	and      	r2, r1
    4ee8:	3a40      	cmpnei      	r2, 0
    4eea:	0c03      	bf      	0x4ef0	// 4ef0 <ADCIntHandler+0x44>
		ADC0->CSR = ADC12_CMP0H;
    4eec:	3210      	movi      	r2, 16
    4eee:	07e9      	br      	0x4ec0	// 4ec0 <ADCIntHandler+0x14>
	else if((ADC0->SR&ADC12_CMP0L)==ADC12_CMP0L)
    4ef0:	9348      	ld.w      	r2, (r3, 0x20)
    4ef2:	3120      	movi      	r1, 32
    4ef4:	6884      	and      	r2, r1
    4ef6:	3a40      	cmpnei      	r2, 0
    4ef8:	0c03      	bf      	0x4efe	// 4efe <ADCIntHandler+0x52>
		ADC0->CSR = ADC12_CMP0L;
    4efa:	3220      	movi      	r2, 32
    4efc:	07e2      	br      	0x4ec0	// 4ec0 <ADCIntHandler+0x14>
	else if((ADC0->SR&ADC12_CMP1H)==ADC12_CMP1H)
    4efe:	9348      	ld.w      	r2, (r3, 0x20)
    4f00:	3140      	movi      	r1, 64
    4f02:	6884      	and      	r2, r1
    4f04:	3a40      	cmpnei      	r2, 0
    4f06:	0c03      	bf      	0x4f0c	// 4f0c <ADCIntHandler+0x60>
		ADC0->CSR = ADC12_CMP1H;
    4f08:	3240      	movi      	r2, 64
    4f0a:	07db      	br      	0x4ec0	// 4ec0 <ADCIntHandler+0x14>
	else if((ADC0->SR&ADC12_CMP1L)==ADC12_CMP1L)
    4f0c:	9348      	ld.w      	r2, (r3, 0x20)
    4f0e:	3180      	movi      	r1, 128
    4f10:	6884      	and      	r2, r1
    4f12:	3a40      	cmpnei      	r2, 0
    4f14:	0fd7      	bf      	0x4ec2	// 4ec2 <ADCIntHandler+0x16>
		ADC0->CSR = ADC12_CMP1L;
    4f16:	3280      	movi      	r2, 128
    4f18:	07d4      	br      	0x4ec0	// 4ec0 <ADCIntHandler+0x14>

00004f1a <LEDIntHandler>:
//LED Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LEDIntHandler(void) 
{
    4f1a:	1460      	nie
    4f1c:	1462      	ipush
    // ISR content ...
	if ((LED0->MISR &ICEND)==ICEND) 
    4f1e:	1073      	lrw      	r3, 0x20000018	// 4f68 <SPIIntHandler+0x26>
    4f20:	3101      	movi      	r1, 1
    4f22:	9360      	ld.w      	r3, (r3, 0)
    4f24:	9344      	ld.w      	r2, (r3, 0x10)
    4f26:	6884      	and      	r2, r1
    4f28:	3a40      	cmpnei      	r2, 0
    4f2a:	0c05      	bf      	0x4f34	// 4f34 <LEDIntHandler+0x1a>
    {
        LED0->ICR = ICEND;
    4f2c:	3201      	movi      	r2, 1
    } 
    else if((LED0->MISR &IPEND)==IPEND) 
    {
        LED0->ICR = IPEND;
    4f2e:	b345      	st.w      	r2, (r3, 0x14)
    } 
}
    4f30:	1463      	ipop
    4f32:	1461      	nir
    else if((LED0->MISR &IPEND)==IPEND) 
    4f34:	9344      	ld.w      	r2, (r3, 0x10)
    4f36:	3102      	movi      	r1, 2
    4f38:	6884      	and      	r2, r1
    4f3a:	3a40      	cmpnei      	r2, 0
    4f3c:	0ffa      	bf      	0x4f30	// 4f30 <LEDIntHandler+0x16>
        LED0->ICR = IPEND;
    4f3e:	3202      	movi      	r2, 2
    4f40:	07f7      	br      	0x4f2e	// 4f2e <LEDIntHandler+0x14>

00004f42 <SPIIntHandler>:
//SPI Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPIIntHandler(void) 
{
    4f42:	1460      	nie
    4f44:	1462      	ipush
    // ISR content ...
	if((SPI0->MISR&SPI_PORIM)==SPI_PORIM)					//接收溢出中断
    4f46:	106a      	lrw      	r3, 0x2000000c	// 4f6c <SPIIntHandler+0x2a>
    4f48:	3101      	movi      	r1, 1
    4f4a:	9360      	ld.w      	r3, (r3, 0)
    4f4c:	9347      	ld.w      	r2, (r3, 0x1c)
    4f4e:	6884      	and      	r2, r1
    4f50:	3a40      	cmpnei      	r2, 0
    4f52:	040f      	br      	0x4f70	// 4f70 <SPIIntHandler+0x2e>
    4f54:	2000004c 	.long	0x2000004c
    4f58:	20000028 	.long	0x20000028
    4f5c:	20000024 	.long	0x20000024
    4f60:	20000020 	.long	0x20000020
    4f64:	20000054 	.long	0x20000054
    4f68:	20000018 	.long	0x20000018
    4f6c:	2000000c 	.long	0x2000000c
    4f70:	0c05      	bf      	0x4f7a	// 4f7a <SPIIntHandler+0x38>
	{
		SPI0->ICR = SPI_PORIM;
    4f72:	3201      	movi      	r2, 1
		SPI_DATA[7]=SPI0->DR;
		nop;*/
	}
	else if((SPI0->MISR&SPI_TXIM)==SPI_TXIM)				//发送FIFO中断
	{
		SPI0->ICR = SPI_TXIM;
    4f74:	b348      	st.w      	r2, (r3, 0x20)
	}
}
    4f76:	1463      	ipop
    4f78:	1461      	nir
	else if((SPI0->MISR&SPI_RTIM)==SPI_RTIM)				//接收超时中断
    4f7a:	9347      	ld.w      	r2, (r3, 0x1c)
    4f7c:	3102      	movi      	r1, 2
    4f7e:	6884      	and      	r2, r1
    4f80:	3a40      	cmpnei      	r2, 0
    4f82:	0c03      	bf      	0x4f88	// 4f88 <SPIIntHandler+0x46>
		SPI0->ICR = SPI_RTIM;
    4f84:	3202      	movi      	r2, 2
    4f86:	07f7      	br      	0x4f74	// 4f74 <SPIIntHandler+0x32>
	else if((SPI0->MISR&SPI_RXIM)==SPI_RXIM)				//接收FIFO中断,FIFO占用1/8,1/4,1/2中断
    4f88:	9347      	ld.w      	r2, (r3, 0x1c)
    4f8a:	3104      	movi      	r1, 4
    4f8c:	6884      	and      	r2, r1
    4f8e:	3a40      	cmpnei      	r2, 0
    4f90:	0c03      	bf      	0x4f96	// 4f96 <SPIIntHandler+0x54>
		SPI0->ICR = SPI_RXIM;
    4f92:	3204      	movi      	r2, 4
    4f94:	07f0      	br      	0x4f74	// 4f74 <SPIIntHandler+0x32>
	else if((SPI0->MISR&SPI_TXIM)==SPI_TXIM)				//发送FIFO中断
    4f96:	9347      	ld.w      	r2, (r3, 0x1c)
    4f98:	3108      	movi      	r1, 8
    4f9a:	6884      	and      	r2, r1
    4f9c:	3a40      	cmpnei      	r2, 0
    4f9e:	0fec      	bf      	0x4f76	// 4f76 <SPIIntHandler+0x34>
		SPI0->ICR = SPI_TXIM;
    4fa0:	3208      	movi      	r2, 8
    4fa2:	07e9      	br      	0x4f74	// 4f74 <SPIIntHandler+0x32>

00004fa4 <EPWMIntHandler>:
//EPWM Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPWMIntHandler(void) 
{
    4fa4:	1460      	nie
    4fa6:	1462      	ipush
    // ISR content ...
	if ((EPWM->MISR & EPWM_START0)==EPWM_START0) 
    4fa8:	136c      	lrw      	r3, 0x2000001c	// 5158 <CMP1IntHandler+0x28>
    4faa:	3080      	movi      	r0, 128
    4fac:	9360      	ld.w      	r3, (r3, 0)
    4fae:	60c0      	addu      	r3, r0
    4fb0:	9351      	ld.w      	r2, (r3, 0x44)
    4fb2:	3101      	movi      	r1, 1
    4fb4:	6884      	and      	r2, r1
    4fb6:	3a40      	cmpnei      	r2, 0
    4fb8:	0c04      	bf      	0x4fc0	// 4fc0 <EPWMIntHandler+0x1c>
    {
        EPWM->ICR = EPWM_START0;
    4fba:	3201      	movi      	r2, 1
    {
        EPWM->ICR = EPWM1_SLPA_OVF;
    }
	else if((EPWM->MISR & EPWM1_SLPB_OVF)==EPWM1_SLPB_OVF) 
    {
        EPWM->ICR = EPWM1_SLPB_OVF;
    4fbc:	b34f      	st.w      	r2, (r3, 0x3c)
    }
}
    4fbe:	04a3      	br      	0x5104	// 5104 <EPWMIntHandler+0x160>
    else if((EPWM->MISR & EPWM_STOP0)==EPWM_STOP0) 
    4fc0:	9351      	ld.w      	r2, (r3, 0x44)
    4fc2:	3102      	movi      	r1, 2
    4fc4:	6884      	and      	r2, r1
    4fc6:	3a40      	cmpnei      	r2, 0
    4fc8:	0c03      	bf      	0x4fce	// 4fce <EPWMIntHandler+0x2a>
        EPWM->ICR = EPWM_STOP0;
    4fca:	3202      	movi      	r2, 2
    4fcc:	07f8      	br      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM_PEND0)==EPWM_PEND0) 
    4fce:	9351      	ld.w      	r2, (r3, 0x44)
    4fd0:	3104      	movi      	r1, 4
    4fd2:	6884      	and      	r2, r1
    4fd4:	3a40      	cmpnei      	r2, 0
    4fd6:	0c03      	bf      	0x4fdc	// 4fdc <EPWMIntHandler+0x38>
        EPWM->ICR = EPWM_PEND0;
    4fd8:	3204      	movi      	r2, 4
    4fda:	07f1      	br      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM_CENTER0)==EPWM_CENTER0) 
    4fdc:	9351      	ld.w      	r2, (r3, 0x44)
    4fde:	3108      	movi      	r1, 8
    4fe0:	6884      	and      	r2, r1
    4fe2:	3a40      	cmpnei      	r2, 0
    4fe4:	0c03      	bf      	0x4fea	// 4fea <EPWMIntHandler+0x46>
        EPWM->ICR = EPWM_CENTER0;
    4fe6:	3208      	movi      	r2, 8
    4fe8:	07ea      	br      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if ((EPWM->MISR & EPWM_START1)==EPWM_START1) 
    4fea:	9331      	ld.w      	r1, (r3, 0x44)
    4fec:	3210      	movi      	r2, 16
    4fee:	6848      	and      	r1, r2
    4ff0:	3940      	cmpnei      	r1, 0
    4ff2:	0be5      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
    else if((EPWM->MISR & EPWM_STOP1)==EPWM_STOP1) 
    4ff4:	9331      	ld.w      	r1, (r3, 0x44)
    4ff6:	3220      	movi      	r2, 32
    4ff8:	6848      	and      	r1, r2
    4ffa:	3940      	cmpnei      	r1, 0
    4ffc:	0be0      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM_PEND1)==EPWM_PEND1) 
    4ffe:	9331      	ld.w      	r1, (r3, 0x44)
    5000:	3240      	movi      	r2, 64
    5002:	6848      	and      	r1, r2
    5004:	3940      	cmpnei      	r1, 0
    5006:	0bdb      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM_CENTER1)==EPWM_CENTER1) 
    5008:	9351      	ld.w      	r2, (r3, 0x44)
    500a:	6880      	and      	r2, r0
    500c:	3a40      	cmpnei      	r2, 0
    500e:	0c03      	bf      	0x5014	// 5014 <EPWMIntHandler+0x70>
        EPWM->ICR = EPWM_CENTER1;
    5010:	3280      	movi      	r2, 128
    5012:	07d5      	br      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if ((EPWM->MISR & EPWM_START2)==EPWM_START2) 
    5014:	3280      	movi      	r2, 128
    5016:	9331      	ld.w      	r1, (r3, 0x44)
    5018:	4241      	lsli      	r2, r2, 1
    501a:	6848      	and      	r1, r2
    501c:	3940      	cmpnei      	r1, 0
    501e:	0bcf      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
    else if((EPWM->MISR & EPWM_STOP2)==EPWM_STOP2) 
    5020:	3280      	movi      	r2, 128
    5022:	9331      	ld.w      	r1, (r3, 0x44)
    5024:	4242      	lsli      	r2, r2, 2
    5026:	6848      	and      	r1, r2
    5028:	3940      	cmpnei      	r1, 0
    502a:	0bc9      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM_PEND2)==EPWM_PEND2) 
    502c:	3280      	movi      	r2, 128
    502e:	9331      	ld.w      	r1, (r3, 0x44)
    5030:	4243      	lsli      	r2, r2, 3
    5032:	6848      	and      	r1, r2
    5034:	3940      	cmpnei      	r1, 0
    5036:	0bc3      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM_CENTER2)==EPWM_CENTER2) 
    5038:	3280      	movi      	r2, 128
    503a:	9331      	ld.w      	r1, (r3, 0x44)
    503c:	4244      	lsli      	r2, r2, 4
    503e:	6848      	and      	r1, r2
    5040:	3940      	cmpnei      	r1, 0
    5042:	0bbd      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM0_CMPAUM)==EPWM0_CMPAUM) 
    5044:	3280      	movi      	r2, 128
    5046:	9331      	ld.w      	r1, (r3, 0x44)
    5048:	4245      	lsli      	r2, r2, 5
    504a:	6848      	and      	r1, r2
    504c:	3940      	cmpnei      	r1, 0
    504e:	0bb7      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM0_CMPADM)==EPWM0_CMPADM) 
    5050:	3280      	movi      	r2, 128
    5052:	9331      	ld.w      	r1, (r3, 0x44)
    5054:	4246      	lsli      	r2, r2, 6
    5056:	6848      	and      	r1, r2
    5058:	3940      	cmpnei      	r1, 0
    505a:	0bb1      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM0_CMPBUM)==EPWM0_CMPBUM) 
    505c:	3280      	movi      	r2, 128
    505e:	9331      	ld.w      	r1, (r3, 0x44)
    5060:	4247      	lsli      	r2, r2, 7
    5062:	6848      	and      	r1, r2
    5064:	3940      	cmpnei      	r1, 0
    5066:	0bab      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM0_CMPBDM)==EPWM0_CMPBDM) 
    5068:	3280      	movi      	r2, 128
    506a:	9331      	ld.w      	r1, (r3, 0x44)
    506c:	4248      	lsli      	r2, r2, 8
    506e:	6848      	and      	r1, r2
    5070:	3940      	cmpnei      	r1, 0
    5072:	0ba5      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM1_CMPAUM)==EPWM1_CMPAUM) 
    5074:	3280      	movi      	r2, 128
    5076:	9331      	ld.w      	r1, (r3, 0x44)
    5078:	4249      	lsli      	r2, r2, 9
    507a:	6848      	and      	r1, r2
    507c:	3940      	cmpnei      	r1, 0
    507e:	0b9f      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM1_CMPADM)==EPWM1_CMPADM) 
    5080:	3280      	movi      	r2, 128
    5082:	9331      	ld.w      	r1, (r3, 0x44)
    5084:	424a      	lsli      	r2, r2, 10
    5086:	6848      	and      	r1, r2
    5088:	3940      	cmpnei      	r1, 0
    508a:	0b99      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM1_CMPBUM)==EPWM1_CMPBUM) 
    508c:	3280      	movi      	r2, 128
    508e:	9331      	ld.w      	r1, (r3, 0x44)
    5090:	424b      	lsli      	r2, r2, 11
    5092:	6848      	and      	r1, r2
    5094:	3940      	cmpnei      	r1, 0
    5096:	0b93      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM1_CMPBDM)==EPWM1_CMPBDM) 
    5098:	3280      	movi      	r2, 128
    509a:	9331      	ld.w      	r1, (r3, 0x44)
    509c:	424c      	lsli      	r2, r2, 12
    509e:	6848      	and      	r1, r2
    50a0:	3940      	cmpnei      	r1, 0
    50a2:	0b8d      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM2_CMPAUM)==EPWM2_CMPAUM) 
    50a4:	3280      	movi      	r2, 128
    50a6:	9331      	ld.w      	r1, (r3, 0x44)
    50a8:	424d      	lsli      	r2, r2, 13
    50aa:	6848      	and      	r1, r2
    50ac:	3940      	cmpnei      	r1, 0
    50ae:	0b87      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM2_CMPADM)==EPWM2_CMPADM) 
    50b0:	3280      	movi      	r2, 128
    50b2:	9331      	ld.w      	r1, (r3, 0x44)
    50b4:	424e      	lsli      	r2, r2, 14
    50b6:	6848      	and      	r1, r2
    50b8:	3940      	cmpnei      	r1, 0
    50ba:	0b81      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM2_CMPBUM)==EPWM2_CMPBUM) 
    50bc:	3280      	movi      	r2, 128
    50be:	9331      	ld.w      	r1, (r3, 0x44)
    50c0:	424f      	lsli      	r2, r2, 15
    50c2:	6848      	and      	r1, r2
    50c4:	3940      	cmpnei      	r1, 0
    50c6:	0b7b      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM2_CMPBDM)==EPWM2_CMPBDM) 
    50c8:	3280      	movi      	r2, 128
    50ca:	9331      	ld.w      	r1, (r3, 0x44)
    50cc:	4250      	lsli      	r2, r2, 16
    50ce:	6848      	and      	r1, r2
    50d0:	3940      	cmpnei      	r1, 0
    50d2:	0b75      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM0_SLPA_OVF)==EPWM0_SLPA_OVF) 
    50d4:	3280      	movi      	r2, 128
    50d6:	9331      	ld.w      	r1, (r3, 0x44)
    50d8:	4251      	lsli      	r2, r2, 17
    50da:	6848      	and      	r1, r2
    50dc:	3940      	cmpnei      	r1, 0
    50de:	0b6f      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM0_SLPB_OVF)==EPWM0_SLPB_OVF) 
    50e0:	3280      	movi      	r2, 128
    50e2:	9331      	ld.w      	r1, (r3, 0x44)
    50e4:	4252      	lsli      	r2, r2, 18
    50e6:	6848      	and      	r1, r2
    50e8:	3940      	cmpnei      	r1, 0
    50ea:	0b69      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM1_SLPA_OVF)==EPWM1_SLPA_OVF) 
    50ec:	3280      	movi      	r2, 128
    50ee:	9331      	ld.w      	r1, (r3, 0x44)
    50f0:	4253      	lsli      	r2, r2, 19
    50f2:	6848      	and      	r1, r2
    50f4:	3940      	cmpnei      	r1, 0
    50f6:	0b63      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
	else if((EPWM->MISR & EPWM1_SLPB_OVF)==EPWM1_SLPB_OVF) 
    50f8:	3280      	movi      	r2, 128
    50fa:	9331      	ld.w      	r1, (r3, 0x44)
    50fc:	4254      	lsli      	r2, r2, 20
    50fe:	6848      	and      	r1, r2
    5100:	3940      	cmpnei      	r1, 0
    5102:	0b5d      	bt      	0x4fbc	// 4fbc <EPWMIntHandler+0x18>
}
    5104:	1463      	ipop
    5106:	1461      	nir

00005108 <CMP0IntHandler>:
//CMP0,CMP2 interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CMP0IntHandler(void) 
{
    5108:	1460      	nie
    510a:	1462      	ipush
    // ISR content ...
	if ((CMP->MISR & EDGEDET0)==EDGEDET0) 
    510c:	1074      	lrw      	r3, 0x20000004	// 515c <CMP1IntHandler+0x2c>
    510e:	3101      	movi      	r1, 1
    5110:	9360      	ld.w      	r3, (r3, 0)
    5112:	9356      	ld.w      	r2, (r3, 0x58)
    5114:	6884      	and      	r2, r1
    5116:	3a40      	cmpnei      	r2, 0
    5118:	0c05      	bf      	0x5122	// 5122 <CMP0IntHandler+0x1a>
	{
		CMP->ICR =	EDGEDET0;
    511a:	3201      	movi      	r2, 1
	}
	else if ((CMP->MISR & EDGEDET2)==EDGEDET2) 
	{
		CMP->ICR =	EDGEDET2;
    511c:	b357      	st.w      	r2, (r3, 0x5c)
	}
}
    511e:	1463      	ipop
    5120:	1461      	nir
	else if ((CMP->MISR & EDGEDET2)==EDGEDET2) 
    5122:	9356      	ld.w      	r2, (r3, 0x58)
    5124:	3104      	movi      	r1, 4
    5126:	6884      	and      	r2, r1
    5128:	3a40      	cmpnei      	r2, 0
    512a:	0ffa      	bf      	0x511e	// 511e <CMP0IntHandler+0x16>
		CMP->ICR =	EDGEDET2;
    512c:	3204      	movi      	r2, 4
    512e:	07f7      	br      	0x511c	// 511c <CMP0IntHandler+0x14>

00005130 <CMP1IntHandler>:
//CMP1,CMP3,CMP4 interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CMP1IntHandler(void) 
{
    5130:	1460      	nie
    5132:	1462      	ipush
    // ISR content ...
	if((CMP->MISR & EDGEDET1)==EDGEDET1)
    5134:	106a      	lrw      	r3, 0x20000004	// 515c <CMP1IntHandler+0x2c>
    5136:	3102      	movi      	r1, 2
    5138:	9360      	ld.w      	r3, (r3, 0)
    513a:	9356      	ld.w      	r2, (r3, 0x58)
    513c:	6884      	and      	r2, r1
    513e:	3a40      	cmpnei      	r2, 0
    5140:	0c05      	bf      	0x514a	// 514a <CMP1IntHandler+0x1a>
	{
		CMP->ICR =	EDGEDET1;
    5142:	3202      	movi      	r2, 2
	{
		CMP->ICR =	EDGEDET3;				
	}
	else if((CMP->MISR & EDGEDET4)==EDGEDET4)
	{
		CMP->ICR =	EDGEDET4;
    5144:	b357      	st.w      	r2, (r3, 0x5c)
	}
}
    5146:	1463      	ipop
    5148:	1461      	nir
	else if((CMP->MISR & EDGEDET3)==EDGEDET3)
    514a:	9356      	ld.w      	r2, (r3, 0x58)
    514c:	3108      	movi      	r1, 8
    514e:	6884      	and      	r2, r1
    5150:	3a40      	cmpnei      	r2, 0
    5152:	0c07      	bf      	0x5160	// 5160 <CMP1IntHandler+0x30>
		CMP->ICR =	EDGEDET3;				
    5154:	3208      	movi      	r2, 8
    5156:	07f7      	br      	0x5144	// 5144 <CMP1IntHandler+0x14>
    5158:	2000001c 	.long	0x2000001c
    515c:	20000004 	.long	0x20000004
	else if((CMP->MISR & EDGEDET4)==EDGEDET4)
    5160:	9356      	ld.w      	r2, (r3, 0x58)
    5162:	3110      	movi      	r1, 16
    5164:	6884      	and      	r2, r1
    5166:	3a40      	cmpnei      	r2, 0
    5168:	0fef      	bf      	0x5146	// 5146 <CMP1IntHandler+0x16>
		CMP->ICR =	EDGEDET4;
    516a:	3210      	movi      	r2, 16
    516c:	07ec      	br      	0x5144	// 5144 <CMP1IntHandler+0x14>

0000516e <PriviledgeVioHandler>:
}

void PriviledgeVioHandler(void) 
{
    // ISR content ...
	nop;
    516e:	6c03      	mov      	r0, r0
}
    5170:	783c      	rts

00005172 <TKEYIntHandler>:
    // ISR content ...
	nop;
}

void TKEYIntHandler(void)
{
    5172:	1460      	nie
    5174:	1462      	ipush
	// ISR content ...
	nop;
    5176:	6c03      	mov      	r0, r0
}
    5178:	1463      	ipop
    517a:	1461      	nir

0000517c <PendTrapHandler>:
    517c:	1460      	nie
    517e:	1462      	ipush
    5180:	14d0      	push      	r15
    5182:	e3fffff8 	bsr      	0x5172	// 5172 <TKEYIntHandler>
    5186:	d9ee2000 	ld.w      	r15, (sp, 0)
    518a:	1401      	addi      	sp, sp, 4
    518c:	1463      	ipop
    518e:	1461      	nir

00005190 <Trap3Handler>:
    5190:	1460      	nie
    5192:	1462      	ipush
    5194:	14d0      	push      	r15
    5196:	e3ffffee 	bsr      	0x5172	// 5172 <TKEYIntHandler>
    519a:	d9ee2000 	ld.w      	r15, (sp, 0)
    519e:	1401      	addi      	sp, sp, 4
    51a0:	1463      	ipop
    51a2:	1461      	nir

000051a4 <Trap2Handler>:
    51a4:	1460      	nie
    51a6:	1462      	ipush
    51a8:	14d0      	push      	r15
    51aa:	e3ffffe4 	bsr      	0x5172	// 5172 <TKEYIntHandler>
    51ae:	d9ee2000 	ld.w      	r15, (sp, 0)
    51b2:	1401      	addi      	sp, sp, 4
    51b4:	1463      	ipop
    51b6:	1461      	nir

000051b8 <Trap1Handler>:
    51b8:	1460      	nie
    51ba:	1462      	ipush
    51bc:	14d0      	push      	r15
    51be:	e3ffffda 	bsr      	0x5172	// 5172 <TKEYIntHandler>
    51c2:	d9ee2000 	ld.w      	r15, (sp, 0)
    51c6:	1401      	addi      	sp, sp, 4
    51c8:	1463      	ipop
    51ca:	1461      	nir

000051cc <Trap0Handler>:
    51cc:	1460      	nie
    51ce:	1462      	ipush
    51d0:	14d0      	push      	r15
    51d2:	e3ffffd0 	bsr      	0x5172	// 5172 <TKEYIntHandler>
    51d6:	d9ee2000 	ld.w      	r15, (sp, 0)
    51da:	1401      	addi      	sp, sp, 4
    51dc:	1463      	ipop
    51de:	1461      	nir

000051e0 <UnrecExecpHandler>:
    51e0:	1460      	nie
    51e2:	1462      	ipush
    51e4:	14d0      	push      	r15
    51e6:	e3ffffc6 	bsr      	0x5172	// 5172 <TKEYIntHandler>
    51ea:	d9ee2000 	ld.w      	r15, (sp, 0)
    51ee:	1401      	addi      	sp, sp, 4
    51f0:	1463      	ipop
    51f2:	1461      	nir

000051f4 <BreakPointHandler>:
    51f4:	1460      	nie
    51f6:	1462      	ipush
    51f8:	14d0      	push      	r15
    51fa:	e3ffffbc 	bsr      	0x5172	// 5172 <TKEYIntHandler>
    51fe:	d9ee2000 	ld.w      	r15, (sp, 0)
    5202:	1401      	addi      	sp, sp, 4
    5204:	1463      	ipop
    5206:	1461      	nir

00005208 <AccessErrHandler>:
    5208:	1460      	nie
    520a:	1462      	ipush
    520c:	14d0      	push      	r15
    520e:	e3ffffb2 	bsr      	0x5172	// 5172 <TKEYIntHandler>
    5212:	d9ee2000 	ld.w      	r15, (sp, 0)
    5216:	1401      	addi      	sp, sp, 4
    5218:	1463      	ipop
    521a:	1461      	nir

0000521c <IllegalInstrHandler>:
    521c:	1460      	nie
    521e:	1462      	ipush
    5220:	14d0      	push      	r15
    5222:	e3ffffa8 	bsr      	0x5172	// 5172 <TKEYIntHandler>
    5226:	d9ee2000 	ld.w      	r15, (sp, 0)
    522a:	1401      	addi      	sp, sp, 4
    522c:	1463      	ipop
    522e:	1461      	nir

00005230 <MisalignedHandler>:
    5230:	1460      	nie
    5232:	1462      	ipush
    5234:	14d0      	push      	r15
    5236:	e3ffff9e 	bsr      	0x5172	// 5172 <TKEYIntHandler>
    523a:	d9ee2000 	ld.w      	r15, (sp, 0)
    523e:	1401      	addi      	sp, sp, 4
    5240:	1463      	ipop
    5242:	1461      	nir

00005244 <__udiv32>:
    5244:	3940      	cmpnei      	r1, 0
    5246:	0803      	bt      	0x524c	// 524c <__udiv32+0x8>
    5248:	c0002c20 	trap      	3
    524c:	3840      	cmpnei      	r0, 0
    524e:	0802      	bt      	0x5252	// 5252 <__udiv32+0xe>
    5250:	783c      	rts
    5252:	14c1      	push      	r4
    5254:	3201      	movi      	r2, 1
    5256:	6cc3      	mov      	r3, r0
    5258:	3420      	movi      	r4, 32
    525a:	3b00      	cmphsi      	r3, 1
    525c:	0c04      	bf      	0x5264	// 5264 <__udiv32+0x20>
    525e:	2c00      	subi      	r4, 1
    5260:	4b61      	lsri      	r3, r3, 1
    5262:	07fc      	br      	0x525a	// 525a <__udiv32+0x16>
    5264:	7090      	lsl      	r2, r4
    5266:	7010      	lsl      	r0, r4
    5268:	6cc7      	mov      	r3, r1
    526a:	3420      	movi      	r4, 32
    526c:	3b00      	cmphsi      	r3, 1
    526e:	0c04      	bf      	0x5276	// 5276 <__udiv32+0x32>
    5270:	2c00      	subi      	r4, 1
    5272:	4b61      	lsri      	r3, r3, 1
    5274:	07fc      	br      	0x526c	// 526c <__udiv32+0x28>
    5276:	2400      	addi      	r4, 1
    5278:	6cc3      	mov      	r3, r0
    527a:	70d1      	lsr      	r3, r4
    527c:	6d12      	nor      	r4, r4
    527e:	2420      	addi      	r4, 33
    5280:	7090      	lsl      	r2, r4
    5282:	7010      	lsl      	r0, r4
    5284:	3a40      	cmpnei      	r2, 0
    5286:	0c09      	bf      	0x5298	// 5298 <__udiv32+0x54>
    5288:	6402      	cmpne      	r0, r0
    528a:	6001      	addc      	r0, r0
    528c:	60cd      	addc      	r3, r3
    528e:	644c      	cmphs      	r3, r1
    5290:	0c02      	bf      	0x5294	// 5294 <__udiv32+0x50>
    5292:	60c6      	subu      	r3, r1
    5294:	6089      	addc      	r2, r2
    5296:	0ff9      	bf      	0x5288	// 5288 <__udiv32+0x44>
    5298:	6c0b      	mov      	r0, r2
    529a:	6c4f      	mov      	r1, r3
    529c:	1481      	pop      	r4
	...

000052a0 <___gnu_csky_case_uqi>:
    52a0:	1421      	subi      	sp, sp, 4
    52a2:	b820      	st.w      	r1, (sp, 0)
    52a4:	6c7f      	mov      	r1, r15
    52a6:	6040      	addu      	r1, r0
    52a8:	8120      	ld.b      	r1, (r1, 0)
    52aa:	4121      	lsli      	r1, r1, 1
    52ac:	63c4      	addu      	r15, r1
    52ae:	9820      	ld.w      	r1, (sp, 0)
    52b0:	1401      	addi      	sp, sp, 4
    52b2:	783c      	rts

000052b4 <___gnu_csky_case_uhi>:
    52b4:	1422      	subi      	sp, sp, 8
    52b6:	b801      	st.w      	r0, (sp, 0x4)
    52b8:	b820      	st.w      	r1, (sp, 0)
    52ba:	6c7f      	mov      	r1, r15
    52bc:	4001      	lsli      	r0, r0, 1
    52be:	6040      	addu      	r1, r0
    52c0:	8920      	ld.h      	r1, (r1, 0)
    52c2:	4121      	lsli      	r1, r1, 1
    52c4:	63c4      	addu      	r15, r1
    52c6:	9801      	ld.w      	r0, (sp, 0x4)
    52c8:	9820      	ld.w      	r1, (sp, 0)
    52ca:	1402      	addi      	sp, sp, 8
    52cc:	783c      	rts
	...

000052d0 <__memcpy_fast>:
    52d0:	14c3      	push      	r4-r6
    52d2:	6d83      	mov      	r6, r0
    52d4:	6d07      	mov      	r4, r1
    52d6:	6d18      	or      	r4, r6
    52d8:	3303      	movi      	r3, 3
    52da:	690c      	and      	r4, r3
    52dc:	3c40      	cmpnei      	r4, 0
    52de:	0c0b      	bf      	0x52f4	// 52f4 <__memcpy_fast+0x24>
    52e0:	3a40      	cmpnei      	r2, 0
    52e2:	0c08      	bf      	0x52f2	// 52f2 <__memcpy_fast+0x22>
    52e4:	8160      	ld.b      	r3, (r1, 0)
    52e6:	2100      	addi      	r1, 1
    52e8:	2a00      	subi      	r2, 1
    52ea:	a660      	st.b      	r3, (r6, 0)
    52ec:	2600      	addi      	r6, 1
    52ee:	3a40      	cmpnei      	r2, 0
    52f0:	0bfa      	bt      	0x52e4	// 52e4 <__memcpy_fast+0x14>
    52f2:	1483      	pop      	r4-r6
    52f4:	3a2f      	cmplti      	r2, 16
    52f6:	080e      	bt      	0x5312	// 5312 <__memcpy_fast+0x42>
    52f8:	91a0      	ld.w      	r5, (r1, 0)
    52fa:	9161      	ld.w      	r3, (r1, 0x4)
    52fc:	9182      	ld.w      	r4, (r1, 0x8)
    52fe:	b6a0      	st.w      	r5, (r6, 0)
    5300:	91a3      	ld.w      	r5, (r1, 0xc)
    5302:	b661      	st.w      	r3, (r6, 0x4)
    5304:	b682      	st.w      	r4, (r6, 0x8)
    5306:	b6a3      	st.w      	r5, (r6, 0xc)
    5308:	2a0f      	subi      	r2, 16
    530a:	210f      	addi      	r1, 16
    530c:	260f      	addi      	r6, 16
    530e:	3a2f      	cmplti      	r2, 16
    5310:	0ff4      	bf      	0x52f8	// 52f8 <__memcpy_fast+0x28>
    5312:	3a23      	cmplti      	r2, 4
    5314:	0808      	bt      	0x5324	// 5324 <__memcpy_fast+0x54>
    5316:	9160      	ld.w      	r3, (r1, 0)
    5318:	2a03      	subi      	r2, 4
    531a:	2103      	addi      	r1, 4
    531c:	b660      	st.w      	r3, (r6, 0)
    531e:	2603      	addi      	r6, 4
    5320:	3a23      	cmplti      	r2, 4
    5322:	0ffa      	bf      	0x5316	// 5316 <__memcpy_fast+0x46>
    5324:	3a40      	cmpnei      	r2, 0
    5326:	0fe6      	bf      	0x52f2	// 52f2 <__memcpy_fast+0x22>
    5328:	8160      	ld.b      	r3, (r1, 0)
    532a:	2100      	addi      	r1, 1
    532c:	2a00      	subi      	r2, 1
    532e:	a660      	st.b      	r3, (r6, 0)
    5330:	2600      	addi      	r6, 1
    5332:	07f9      	br      	0x5324	// 5324 <__memcpy_fast+0x54>

00005334 <__memset_fast>:
    5334:	14c3      	push      	r4-r6
    5336:	3a40      	cmpnei      	r2, 0
    5338:	0c1f      	bf      	0x5376	// 5376 <__memset_fast+0x42>
    533a:	6d43      	mov      	r5, r0
    533c:	6d03      	mov      	r4, r0
    533e:	3603      	movi      	r6, 3
    5340:	6918      	and      	r4, r6
    5342:	3c40      	cmpnei      	r4, 0
    5344:	0c1a      	bf      	0x5378	// 5378 <__memset_fast+0x44>
    5346:	a520      	st.b      	r1, (r5, 0)
    5348:	2a00      	subi      	r2, 1
    534a:	3a40      	cmpnei      	r2, 0
    534c:	0c15      	bf      	0x5376	// 5376 <__memset_fast+0x42>
    534e:	2500      	addi      	r5, 1
    5350:	6d17      	mov      	r4, r5
    5352:	3603      	movi      	r6, 3
    5354:	6918      	and      	r4, r6
    5356:	3c40      	cmpnei      	r4, 0
    5358:	0c10      	bf      	0x5378	// 5378 <__memset_fast+0x44>
    535a:	a520      	st.b      	r1, (r5, 0)
    535c:	2a00      	subi      	r2, 1
    535e:	3a40      	cmpnei      	r2, 0
    5360:	0c0b      	bf      	0x5376	// 5376 <__memset_fast+0x42>
    5362:	2500      	addi      	r5, 1
    5364:	6d17      	mov      	r4, r5
    5366:	3603      	movi      	r6, 3
    5368:	6918      	and      	r4, r6
    536a:	3c40      	cmpnei      	r4, 0
    536c:	0c06      	bf      	0x5378	// 5378 <__memset_fast+0x44>
    536e:	a520      	st.b      	r1, (r5, 0)
    5370:	2a00      	subi      	r2, 1
    5372:	2500      	addi      	r5, 1
    5374:	0402      	br      	0x5378	// 5378 <__memset_fast+0x44>
    5376:	1483      	pop      	r4-r6
    5378:	4168      	lsli      	r3, r1, 8
    537a:	6c4c      	or      	r1, r3
    537c:	4170      	lsli      	r3, r1, 16
    537e:	6c4c      	or      	r1, r3
    5380:	3a2f      	cmplti      	r2, 16
    5382:	0809      	bt      	0x5394	// 5394 <__memset_fast+0x60>
    5384:	b520      	st.w      	r1, (r5, 0)
    5386:	b521      	st.w      	r1, (r5, 0x4)
    5388:	b522      	st.w      	r1, (r5, 0x8)
    538a:	b523      	st.w      	r1, (r5, 0xc)
    538c:	2a0f      	subi      	r2, 16
    538e:	250f      	addi      	r5, 16
    5390:	3a2f      	cmplti      	r2, 16
    5392:	0ff9      	bf      	0x5384	// 5384 <__memset_fast+0x50>
    5394:	3a23      	cmplti      	r2, 4
    5396:	0806      	bt      	0x53a2	// 53a2 <__memset_fast+0x6e>
    5398:	2a03      	subi      	r2, 4
    539a:	b520      	st.w      	r1, (r5, 0)
    539c:	2503      	addi      	r5, 4
    539e:	3a23      	cmplti      	r2, 4
    53a0:	0ffc      	bf      	0x5398	// 5398 <__memset_fast+0x64>
    53a2:	3a40      	cmpnei      	r2, 0
    53a4:	0fe9      	bf      	0x5376	// 5376 <__memset_fast+0x42>
    53a6:	2a00      	subi      	r2, 1
    53a8:	a520      	st.b      	r1, (r5, 0)
    53aa:	3a40      	cmpnei      	r2, 0
    53ac:	0fe5      	bf      	0x5376	// 5376 <__memset_fast+0x42>
    53ae:	2a00      	subi      	r2, 1
    53b0:	a521      	st.b      	r1, (r5, 0x1)
    53b2:	3a40      	cmpnei      	r2, 0
    53b4:	0fe1      	bf      	0x5376	// 5376 <__memset_fast+0x42>
    53b6:	a522      	st.b      	r1, (r5, 0x2)
    53b8:	1483      	pop      	r4-r6

Disassembly of section .text.startup:

000053bc <main>:

/*************************************************************/
//main
/*************************************************************/
int main(void) 
{
    53bc:	14d0      	push      	r15
	APT32F172_init();
    53be:	e3fffa74 	bsr      	0x48a6	// 48a6 <APT32F172_init>
	GPIO_Init(GPIOA1,0,0);			
    53c2:	1065      	lrw      	r3, 0x2000004c	// 53d4 <main+0x18>
    53c4:	3200      	movi      	r2, 0
    53c6:	9300      	ld.w      	r0, (r3, 0)
    53c8:	3100      	movi      	r1, 0
    53ca:	e3ffec97 	bsr      	0x2cf8	// 2cf8 <GPIO_Init>
    while(1)
	{
		SYSCON_IWDCNT_Reload();                 	//清狗
    53ce:	e3ffe456 	bsr      	0x1c7a	// 1c7a <SYSCON_IWDCNT_Reload>
    53d2:	07fe      	br      	0x53ce	// 53ce <main+0x12>
    53d4:	2000004c 	.long	0x2000004c
